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Jamie Iles1b8873a2010-02-02 20:25:44 +01001#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
Will Deacon43eab872010-11-13 19:04:32 +00007 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
Jean PIHET796d1292010-01-26 18:51:05 +01008 *
Jamie Iles1b8873a2010-02-02 20:25:44 +01009 * This code is based on the sparc64 perf event code, which is in turn based
Mark Rutlandd39976f2014-09-29 17:15:32 +010010 * on the x86 code.
Jamie Iles1b8873a2010-02-02 20:25:44 +010011 */
12#define pr_fmt(fmt) "hw perfevents: " fmt
13
Mark Rutland74cf0bc2015-05-26 17:23:39 +010014#include <linux/bitmap.h>
Mark Rutlandcc88116d2015-05-13 17:12:25 +010015#include <linux/cpumask.h>
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +000016#include <linux/cpu_pm.h>
Mark Rutland74cf0bc2015-05-26 17:23:39 +010017#include <linux/export.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010018#include <linux/kernel.h>
Sudeep Hollabc1e3c42015-06-30 13:56:57 +010019#include <linux/of_device.h>
Mark Rutlandfa8ad782015-07-06 12:23:53 +010020#include <linux/perf/arm_pmu.h>
Will Deacon49c006b2010-04-29 17:13:24 +010021#include <linux/platform_device.h>
Mark Rutland74cf0bc2015-05-26 17:23:39 +010022#include <linux/slab.h>
23#include <linux/spinlock.h>
Stephen Boydbbd64552014-02-07 21:01:19 +000024#include <linux/irq.h>
25#include <linux/irqdesc.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010026
Mark Rutland74cf0bc2015-05-26 17:23:39 +010027#include <asm/cputype.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010028#include <asm/irq_regs.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010029
Jamie Iles1b8873a2010-02-02 20:25:44 +010030static int
Mark Rutlande1f431b2011-04-28 15:47:10 +010031armpmu_map_cache_event(const unsigned (*cache_map)
32 [PERF_COUNT_HW_CACHE_MAX]
33 [PERF_COUNT_HW_CACHE_OP_MAX]
34 [PERF_COUNT_HW_CACHE_RESULT_MAX],
35 u64 config)
Jamie Iles1b8873a2010-02-02 20:25:44 +010036{
37 unsigned int cache_type, cache_op, cache_result, ret;
38
39 cache_type = (config >> 0) & 0xff;
40 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
41 return -EINVAL;
42
43 cache_op = (config >> 8) & 0xff;
44 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
45 return -EINVAL;
46
47 cache_result = (config >> 16) & 0xff;
48 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
49 return -EINVAL;
50
Mark Rutlande1f431b2011-04-28 15:47:10 +010051 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
Jamie Iles1b8873a2010-02-02 20:25:44 +010052
53 if (ret == CACHE_OP_UNSUPPORTED)
54 return -ENOENT;
55
56 return ret;
57}
58
59static int
Will Deacon6dbc0022012-07-29 12:36:28 +010060armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
Will Deacon84fee972010-11-13 17:13:56 +000061{
Stephen Boydd9f96632013-08-08 18:41:59 +010062 int mapping;
63
64 if (config >= PERF_COUNT_HW_MAX)
65 return -EINVAL;
66
67 mapping = (*event_map)[config];
Mark Rutlande1f431b2011-04-28 15:47:10 +010068 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
Will Deacon84fee972010-11-13 17:13:56 +000069}
70
71static int
Mark Rutlande1f431b2011-04-28 15:47:10 +010072armpmu_map_raw_event(u32 raw_event_mask, u64 config)
Will Deacon84fee972010-11-13 17:13:56 +000073{
Mark Rutlande1f431b2011-04-28 15:47:10 +010074 return (int)(config & raw_event_mask);
75}
76
Will Deacon6dbc0022012-07-29 12:36:28 +010077int
78armpmu_map_event(struct perf_event *event,
79 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
80 const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
84 u32 raw_event_mask)
Mark Rutlande1f431b2011-04-28 15:47:10 +010085{
86 u64 config = event->attr.config;
Mark Rutland67b43052012-09-12 10:53:23 +010087 int type = event->attr.type;
Mark Rutlande1f431b2011-04-28 15:47:10 +010088
Mark Rutland67b43052012-09-12 10:53:23 +010089 if (type == event->pmu->type)
90 return armpmu_map_raw_event(raw_event_mask, config);
91
92 switch (type) {
Mark Rutlande1f431b2011-04-28 15:47:10 +010093 case PERF_TYPE_HARDWARE:
Will Deacon6dbc0022012-07-29 12:36:28 +010094 return armpmu_map_hw_event(event_map, config);
Mark Rutlande1f431b2011-04-28 15:47:10 +010095 case PERF_TYPE_HW_CACHE:
96 return armpmu_map_cache_event(cache_map, config);
97 case PERF_TYPE_RAW:
98 return armpmu_map_raw_event(raw_event_mask, config);
99 }
100
101 return -ENOENT;
Will Deacon84fee972010-11-13 17:13:56 +0000102}
103
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100104int armpmu_event_set_period(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100105{
Mark Rutland8a16b342011-04-28 16:27:54 +0100106 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100107 struct hw_perf_event *hwc = &event->hw;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200108 s64 left = local64_read(&hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100109 s64 period = hwc->sample_period;
110 int ret = 0;
111
112 if (unlikely(left <= -period)) {
113 left = period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200114 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100115 hwc->last_period = period;
116 ret = 1;
117 }
118
119 if (unlikely(left <= 0)) {
120 left += period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200121 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100122 hwc->last_period = period;
123 ret = 1;
124 }
125
Daniel Thompson2d9ed742015-01-05 15:58:54 +0100126 /*
127 * Limit the maximum period to prevent the counter value
128 * from overtaking the one we are about to program. In
129 * effect we are reducing max_period to account for
130 * interrupt latency (and we are being very conservative).
131 */
132 if (left > (armpmu->max_period >> 1))
133 left = armpmu->max_period >> 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100134
Peter Zijlstrae7850592010-05-21 14:43:08 +0200135 local64_set(&hwc->prev_count, (u64)-left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100136
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100137 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100138
139 perf_event_update_userpage(event);
140
141 return ret;
142}
143
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100144u64 armpmu_event_update(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100145{
Mark Rutland8a16b342011-04-28 16:27:54 +0100146 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100147 struct hw_perf_event *hwc = &event->hw;
Will Deacona7378232011-03-25 17:12:37 +0100148 u64 delta, prev_raw_count, new_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100149
150again:
Peter Zijlstrae7850592010-05-21 14:43:08 +0200151 prev_raw_count = local64_read(&hwc->prev_count);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100152 new_raw_count = armpmu->read_counter(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100153
Peter Zijlstrae7850592010-05-21 14:43:08 +0200154 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100155 new_raw_count) != prev_raw_count)
156 goto again;
157
Will Deacon57273472012-03-06 17:33:17 +0100158 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100159
Peter Zijlstrae7850592010-05-21 14:43:08 +0200160 local64_add(delta, &event->count);
161 local64_sub(delta, &hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100162
163 return new_raw_count;
164}
165
166static void
Jamie Iles1b8873a2010-02-02 20:25:44 +0100167armpmu_read(struct perf_event *event)
168{
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100169 armpmu_event_update(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100170}
171
172static void
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200173armpmu_stop(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100174{
Mark Rutland8a16b342011-04-28 16:27:54 +0100175 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100176 struct hw_perf_event *hwc = &event->hw;
177
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200178 /*
179 * ARM pmu always has to update the counter, so ignore
180 * PERF_EF_UPDATE, see comments in armpmu_start().
181 */
182 if (!(hwc->state & PERF_HES_STOPPED)) {
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100183 armpmu->disable(event);
184 armpmu_event_update(event);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200185 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
186 }
187}
188
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100189static void armpmu_start(struct perf_event *event, int flags)
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200190{
Mark Rutland8a16b342011-04-28 16:27:54 +0100191 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200192 struct hw_perf_event *hwc = &event->hw;
193
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200194 /*
195 * ARM pmu always has to reprogram the period, so ignore
196 * PERF_EF_RELOAD, see the comment below.
197 */
198 if (flags & PERF_EF_RELOAD)
199 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
200
201 hwc->state = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100202 /*
203 * Set the period again. Some counters can't be stopped, so when we
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200204 * were stopped we simply disabled the IRQ source and the counter
Jamie Iles1b8873a2010-02-02 20:25:44 +0100205 * may have been left counting. If we don't do this step then we may
206 * get an interrupt too soon or *way* too late if the overflow has
207 * happened since disabling.
208 */
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100209 armpmu_event_set_period(event);
210 armpmu->enable(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100211}
212
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200213static void
214armpmu_del(struct perf_event *event, int flags)
215{
Mark Rutland8a16b342011-04-28 16:27:54 +0100216 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100217 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200218 struct hw_perf_event *hwc = &event->hw;
219 int idx = hwc->idx;
220
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200221 armpmu_stop(event, PERF_EF_UPDATE);
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100222 hw_events->events[idx] = NULL;
223 clear_bit(idx, hw_events->used_mask);
Stephen Boydeab443e2014-02-07 21:01:22 +0000224 if (armpmu->clear_event_idx)
225 armpmu->clear_event_idx(hw_events, event);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200226
227 perf_event_update_userpage(event);
228}
229
Jamie Iles1b8873a2010-02-02 20:25:44 +0100230static int
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200231armpmu_add(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100232{
Mark Rutland8a16b342011-04-28 16:27:54 +0100233 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100234 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100235 struct hw_perf_event *hwc = &event->hw;
236 int idx;
237 int err = 0;
238
Mark Rutlandcc88116d2015-05-13 17:12:25 +0100239 /* An event following a process won't be stopped earlier */
240 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
241 return -ENOENT;
242
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200243 perf_pmu_disable(event->pmu);
Peter Zijlstra24cd7f52010-06-11 17:32:03 +0200244
Jamie Iles1b8873a2010-02-02 20:25:44 +0100245 /* If we don't have a space for the counter then finish early. */
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100246 idx = armpmu->get_event_idx(hw_events, event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100247 if (idx < 0) {
248 err = idx;
249 goto out;
250 }
251
252 /*
253 * If there is an event in the counter we are going to use then make
254 * sure it is disabled.
255 */
256 event->hw.idx = idx;
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100257 armpmu->disable(event);
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100258 hw_events->events[idx] = event;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100259
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200260 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
261 if (flags & PERF_EF_START)
262 armpmu_start(event, PERF_EF_RELOAD);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100263
264 /* Propagate our changes to the userspace mapping. */
265 perf_event_update_userpage(event);
266
267out:
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200268 perf_pmu_enable(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100269 return err;
270}
271
Jamie Iles1b8873a2010-02-02 20:25:44 +0100272static int
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000273validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
274 struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100275{
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000276 struct arm_pmu *armpmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100277
Will Deaconc95eb312013-08-07 23:39:41 +0100278 if (is_software_event(event))
279 return 1;
280
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000281 /*
282 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
283 * core perf code won't check that the pmu->ctx == leader->ctx
284 * until after pmu->event_init(event).
285 */
286 if (event->pmu != pmu)
287 return 0;
288
Will Deacon2dfcb802013-10-09 13:51:29 +0100289 if (event->state < PERF_EVENT_STATE_OFF)
Will Deaconcb2d8b32013-04-12 19:04:19 +0100290 return 1;
291
292 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
Will Deacon65b47112010-09-02 09:32:08 +0100293 return 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100294
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000295 armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100296 return armpmu->get_event_idx(hw_events, event) >= 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100297}
298
299static int
300validate_group(struct perf_event *event)
301{
302 struct perf_event *sibling, *leader = event->group_leader;
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100303 struct pmu_hw_events fake_pmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100304
Will Deaconbce34d12011-11-17 15:05:14 +0000305 /*
306 * Initialise the fake PMU. We only need to populate the
307 * used_mask for the purposes of validation.
308 */
Mark Rutlanda4560842014-05-13 19:08:19 +0100309 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
Jamie Iles1b8873a2010-02-02 20:25:44 +0100310
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000311 if (!validate_event(event->pmu, &fake_pmu, leader))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100312 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100313
314 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000315 if (!validate_event(event->pmu, &fake_pmu, sibling))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100316 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100317 }
318
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000319 if (!validate_event(event->pmu, &fake_pmu, event))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100320 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100321
322 return 0;
323}
324
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100325static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530326{
Stephen Boydbbd64552014-02-07 21:01:19 +0000327 struct arm_pmu *armpmu;
328 struct platform_device *plat_device;
329 struct arm_pmu_platdata *plat;
Will Deacon5f5092e2014-02-11 18:08:41 +0000330 int ret;
331 u64 start_clock, finish_clock;
Stephen Boydbbd64552014-02-07 21:01:19 +0000332
Mark Rutland5ebd9202014-05-13 19:46:10 +0100333 /*
334 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
335 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
336 * do any necessary shifting, we just need to perform the first
337 * dereference.
338 */
339 armpmu = *(void **)dev;
Stephen Boydbbd64552014-02-07 21:01:19 +0000340 plat_device = armpmu->plat_device;
341 plat = dev_get_platdata(&plat_device->dev);
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530342
Will Deacon5f5092e2014-02-11 18:08:41 +0000343 start_clock = sched_clock();
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100344 if (plat && plat->handle_irq)
Mark Rutland5ebd9202014-05-13 19:46:10 +0100345 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100346 else
Mark Rutland5ebd9202014-05-13 19:46:10 +0100347 ret = armpmu->handle_irq(irq, armpmu);
Will Deacon5f5092e2014-02-11 18:08:41 +0000348 finish_clock = sched_clock();
349
350 perf_sample_event_took(finish_clock - start_clock);
351 return ret;
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530352}
353
Will Deacon0b390e22011-07-27 15:18:59 +0100354static void
Mark Rutland8a16b342011-04-28 16:27:54 +0100355armpmu_release_hardware(struct arm_pmu *armpmu)
Will Deacon0b390e22011-07-27 15:18:59 +0100356{
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100357 armpmu->free_irq(armpmu);
Will Deacon0b390e22011-07-27 15:18:59 +0100358}
359
Jamie Iles1b8873a2010-02-02 20:25:44 +0100360static int
Mark Rutland8a16b342011-04-28 16:27:54 +0100361armpmu_reserve_hardware(struct arm_pmu *armpmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100362{
Mark Rutlanded61f982015-05-26 17:23:34 +0100363 int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100364 if (err) {
365 armpmu_release_hardware(armpmu);
366 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100367 }
368
Will Deacon0b390e22011-07-27 15:18:59 +0100369 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100370}
371
Jamie Iles1b8873a2010-02-02 20:25:44 +0100372static void
373hw_perf_event_destroy(struct perf_event *event)
374{
Mark Rutland8a16b342011-04-28 16:27:54 +0100375 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland03b78982011-04-27 11:20:11 +0100376 atomic_t *active_events = &armpmu->active_events;
377 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
378
379 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
Mark Rutland8a16b342011-04-28 16:27:54 +0100380 armpmu_release_hardware(armpmu);
Mark Rutland03b78982011-04-27 11:20:11 +0100381 mutex_unlock(pmu_reserve_mutex);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100382 }
383}
384
385static int
Will Deacon05d22fd2011-07-19 11:57:30 +0100386event_requires_mode_exclusion(struct perf_event_attr *attr)
387{
388 return attr->exclude_idle || attr->exclude_user ||
389 attr->exclude_kernel || attr->exclude_hv;
390}
391
392static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100393__hw_perf_event_init(struct perf_event *event)
394{
Mark Rutland8a16b342011-04-28 16:27:54 +0100395 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100396 struct hw_perf_event *hwc = &event->hw;
Mark Rutland9dcbf462013-01-18 16:10:06 +0000397 int mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100398
Mark Rutlande1f431b2011-04-28 15:47:10 +0100399 mapping = armpmu->map_event(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100400
401 if (mapping < 0) {
402 pr_debug("event %x:%llx not supported\n", event->attr.type,
403 event->attr.config);
404 return mapping;
405 }
406
407 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100408 * We don't assign an index until we actually place the event onto
409 * hardware. Use -1 to signify that we haven't decided where to put it
410 * yet. For SMP systems, each core has it's own PMU so we can't do any
411 * clever allocation or constraints checking at this point.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100412 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100413 hwc->idx = -1;
414 hwc->config_base = 0;
415 hwc->config = 0;
416 hwc->event_base = 0;
417
418 /*
419 * Check whether we need to exclude the counter from certain modes.
420 */
421 if ((!armpmu->set_event_filter ||
422 armpmu->set_event_filter(hwc, &event->attr)) &&
423 event_requires_mode_exclusion(&event->attr)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100424 pr_debug("ARM performance counters do not support "
425 "mode exclusion\n");
Will Deaconfdeb8e32012-07-04 18:15:42 +0100426 return -EOPNOTSUPP;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100427 }
428
429 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100430 * Store the event encoding into the config_base field.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100431 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100432 hwc->config_base |= (unsigned long)mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100433
Vince Weaveredcb4d32014-05-16 17:15:49 -0400434 if (!is_sampling_event(event)) {
Will Deacon57273472012-03-06 17:33:17 +0100435 /*
436 * For non-sampling runs, limit the sample_period to half
437 * of the counter width. That way, the new counter value
438 * is far less likely to overtake the previous one unless
439 * you have some serious IRQ latency issues.
440 */
441 hwc->sample_period = armpmu->max_period >> 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100442 hwc->last_period = hwc->sample_period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200443 local64_set(&hwc->period_left, hwc->sample_period);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100444 }
445
Jamie Iles1b8873a2010-02-02 20:25:44 +0100446 if (event->group_leader != event) {
Chen Gange595ede2013-02-28 17:51:29 +0100447 if (validate_group(event) != 0)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100448 return -EINVAL;
449 }
450
Mark Rutland9dcbf462013-01-18 16:10:06 +0000451 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100452}
453
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200454static int armpmu_event_init(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100455{
Mark Rutland8a16b342011-04-28 16:27:54 +0100456 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100457 int err = 0;
Mark Rutland03b78982011-04-27 11:20:11 +0100458 atomic_t *active_events = &armpmu->active_events;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100459
Mark Rutlandcc88116d2015-05-13 17:12:25 +0100460 /*
461 * Reject CPU-affine events for CPUs that are of a different class to
462 * that which this PMU handles. Process-following events (where
463 * event->cpu == -1) can be migrated between CPUs, and thus we have to
464 * reject them later (in armpmu_add) if they're scheduled on a
465 * different class of CPU.
466 */
467 if (event->cpu != -1 &&
468 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
469 return -ENOENT;
470
Stephane Eranian2481c5f2012-02-09 23:20:59 +0100471 /* does not support taken branch sampling */
472 if (has_branch_stack(event))
473 return -EOPNOTSUPP;
474
Mark Rutlande1f431b2011-04-28 15:47:10 +0100475 if (armpmu->map_event(event) == -ENOENT)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200476 return -ENOENT;
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200477
Jamie Iles1b8873a2010-02-02 20:25:44 +0100478 event->destroy = hw_perf_event_destroy;
479
Mark Rutland03b78982011-04-27 11:20:11 +0100480 if (!atomic_inc_not_zero(active_events)) {
481 mutex_lock(&armpmu->reserve_mutex);
482 if (atomic_read(active_events) == 0)
Mark Rutland8a16b342011-04-28 16:27:54 +0100483 err = armpmu_reserve_hardware(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100484
485 if (!err)
Mark Rutland03b78982011-04-27 11:20:11 +0100486 atomic_inc(active_events);
487 mutex_unlock(&armpmu->reserve_mutex);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100488 }
489
490 if (err)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200491 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100492
493 err = __hw_perf_event_init(event);
494 if (err)
495 hw_perf_event_destroy(event);
496
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200497 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100498}
499
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200500static void armpmu_enable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100501{
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100502 struct arm_pmu *armpmu = to_arm_pmu(pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100503 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Mark Rutland7325eae2011-08-23 11:59:49 +0100504 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100505
Mark Rutlandcc88116d2015-05-13 17:12:25 +0100506 /* For task-bound events we may be called on other CPUs */
507 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
508 return;
509
Will Deaconf4f38432011-07-01 14:38:12 +0100510 if (enabled)
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100511 armpmu->start(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100512}
513
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200514static void armpmu_disable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100515{
Mark Rutland8a16b342011-04-28 16:27:54 +0100516 struct arm_pmu *armpmu = to_arm_pmu(pmu);
Mark Rutlandcc88116d2015-05-13 17:12:25 +0100517
518 /* For task-bound events we may be called on other CPUs */
519 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
520 return;
521
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100522 armpmu->stop(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100523}
524
Mark Rutlandc904e322015-05-13 17:12:26 +0100525/*
526 * In heterogeneous systems, events are specific to a particular
527 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
528 * the same microarchitecture.
529 */
530static int armpmu_filter_match(struct perf_event *event)
531{
532 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
533 unsigned int cpu = smp_processor_id();
534 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
535}
536
Stephen Boyd44d6b1f2013-03-05 03:54:06 +0100537static void armpmu_init(struct arm_pmu *armpmu)
Mark Rutland03b78982011-04-27 11:20:11 +0100538{
539 atomic_set(&armpmu->active_events, 0);
540 mutex_init(&armpmu->reserve_mutex);
Mark Rutland8a16b342011-04-28 16:27:54 +0100541
542 armpmu->pmu = (struct pmu) {
543 .pmu_enable = armpmu_enable,
544 .pmu_disable = armpmu_disable,
545 .event_init = armpmu_event_init,
546 .add = armpmu_add,
547 .del = armpmu_del,
548 .start = armpmu_start,
549 .stop = armpmu_stop,
550 .read = armpmu_read,
Mark Rutlandc904e322015-05-13 17:12:26 +0100551 .filter_match = armpmu_filter_match,
Mark Rutland8a16b342011-04-28 16:27:54 +0100552 };
553}
554
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100555/* Set at runtime when we know what CPU type we are. */
556static struct arm_pmu *__oprofile_cpu_pmu;
557
558/*
559 * Despite the names, these two functions are CPU-specific and are used
560 * by the OProfile/perf code.
561 */
562const char *perf_pmu_name(void)
563{
564 if (!__oprofile_cpu_pmu)
565 return NULL;
566
567 return __oprofile_cpu_pmu->name;
568}
569EXPORT_SYMBOL_GPL(perf_pmu_name);
570
571int perf_num_counters(void)
572{
573 int max_events = 0;
574
575 if (__oprofile_cpu_pmu != NULL)
576 max_events = __oprofile_cpu_pmu->num_events;
577
578 return max_events;
579}
580EXPORT_SYMBOL_GPL(perf_num_counters);
581
582static void cpu_pmu_enable_percpu_irq(void *data)
583{
584 int irq = *(int *)data;
585
586 enable_percpu_irq(irq, IRQ_TYPE_NONE);
587}
588
589static void cpu_pmu_disable_percpu_irq(void *data)
590{
591 int irq = *(int *)data;
592
593 disable_percpu_irq(irq);
594}
595
596static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
597{
598 int i, irq, irqs;
599 struct platform_device *pmu_device = cpu_pmu->plat_device;
600 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
601
602 irqs = min(pmu_device->num_resources, num_possible_cpus());
603
604 irq = platform_get_irq(pmu_device, 0);
605 if (irq >= 0 && irq_is_percpu(irq)) {
Marc Zyngier19a469a2016-07-08 15:56:04 +0100606 on_each_cpu_mask(&cpu_pmu->supported_cpus,
607 cpu_pmu_disable_percpu_irq, &irq, 1);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100608 free_percpu_irq(irq, &hw_events->percpu_pmu);
609 } else {
610 for (i = 0; i < irqs; ++i) {
611 int cpu = i;
612
613 if (cpu_pmu->irq_affinity)
614 cpu = cpu_pmu->irq_affinity[i];
615
616 if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
617 continue;
618 irq = platform_get_irq(pmu_device, i);
619 if (irq >= 0)
620 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
621 }
622 }
623}
624
625static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
626{
627 int i, err, irq, irqs;
628 struct platform_device *pmu_device = cpu_pmu->plat_device;
629 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
630
631 if (!pmu_device)
632 return -ENODEV;
633
634 irqs = min(pmu_device->num_resources, num_possible_cpus());
635 if (irqs < 1) {
636 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
637 return 0;
638 }
639
640 irq = platform_get_irq(pmu_device, 0);
641 if (irq >= 0 && irq_is_percpu(irq)) {
642 err = request_percpu_irq(irq, handler, "arm-pmu",
643 &hw_events->percpu_pmu);
644 if (err) {
645 pr_err("unable to request IRQ%d for ARM PMU counters\n",
646 irq);
647 return err;
648 }
Marc Zyngier19a469a2016-07-08 15:56:04 +0100649
650 on_each_cpu_mask(&cpu_pmu->supported_cpus,
651 cpu_pmu_enable_percpu_irq, &irq, 1);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100652 } else {
653 for (i = 0; i < irqs; ++i) {
654 int cpu = i;
655
656 err = 0;
657 irq = platform_get_irq(pmu_device, i);
658 if (irq < 0)
659 continue;
660
661 if (cpu_pmu->irq_affinity)
662 cpu = cpu_pmu->irq_affinity[i];
663
664 /*
665 * If we have a single PMU interrupt that we can't shift,
666 * assume that we're running on a uniprocessor machine and
667 * continue. Otherwise, continue without this interrupt.
668 */
669 if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
670 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
671 irq, cpu);
672 continue;
673 }
674
675 err = request_irq(irq, handler,
676 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
677 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
678 if (err) {
679 pr_err("unable to request IRQ%d for ARM PMU counters\n",
680 irq);
681 return err;
682 }
683
684 cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
685 }
686 }
687
688 return 0;
689}
690
691/*
692 * PMU hardware loses all context when a CPU goes offline.
693 * When a CPU is hotplugged back in, since some hardware registers are
694 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
695 * junk values out of them.
696 */
697static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
698 void *hcpu)
699{
700 int cpu = (unsigned long)hcpu;
701 struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
702
703 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
704 return NOTIFY_DONE;
705
706 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
707 return NOTIFY_DONE;
708
709 if (pmu->reset)
710 pmu->reset(pmu);
711 else
712 return NOTIFY_DONE;
713
714 return NOTIFY_OK;
715}
716
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +0000717#ifdef CONFIG_CPU_PM
718static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
719{
720 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
721 struct perf_event *event;
722 int idx;
723
724 for (idx = 0; idx < armpmu->num_events; idx++) {
725 /*
726 * If the counter is not used skip it, there is no
727 * need of stopping/restarting it.
728 */
729 if (!test_bit(idx, hw_events->used_mask))
730 continue;
731
732 event = hw_events->events[idx];
733
734 switch (cmd) {
735 case CPU_PM_ENTER:
736 /*
737 * Stop and update the counter
738 */
739 armpmu_stop(event, PERF_EF_UPDATE);
740 break;
741 case CPU_PM_EXIT:
742 case CPU_PM_ENTER_FAILED:
Lorenzo Pieralisicbcc72e2016-04-21 10:24:34 +0100743 /*
744 * Restore and enable the counter.
745 * armpmu_start() indirectly calls
746 *
747 * perf_event_update_userpage()
748 *
749 * that requires RCU read locking to be functional,
750 * wrap the call within RCU_NONIDLE to make the
751 * RCU subsystem aware this cpu is not idle from
752 * an RCU perspective for the armpmu_start() call
753 * duration.
754 */
755 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +0000756 break;
757 default:
758 break;
759 }
760 }
761}
762
763static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
764 void *v)
765{
766 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
767 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
768 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
769
770 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
771 return NOTIFY_DONE;
772
773 /*
774 * Always reset the PMU registers on power-up even if
775 * there are no events running.
776 */
777 if (cmd == CPU_PM_EXIT && armpmu->reset)
778 armpmu->reset(armpmu);
779
780 if (!enabled)
781 return NOTIFY_OK;
782
783 switch (cmd) {
784 case CPU_PM_ENTER:
785 armpmu->stop(armpmu);
786 cpu_pm_pmu_setup(armpmu, cmd);
787 break;
788 case CPU_PM_EXIT:
789 cpu_pm_pmu_setup(armpmu, cmd);
790 case CPU_PM_ENTER_FAILED:
791 armpmu->start(armpmu);
792 break;
793 default:
794 return NOTIFY_DONE;
795 }
796
797 return NOTIFY_OK;
798}
799
800static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
801{
802 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
803 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
804}
805
806static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
807{
808 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
809}
810#else
811static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
812static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
813#endif
814
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100815static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
816{
817 int err;
818 int cpu;
819 struct pmu_hw_events __percpu *cpu_hw_events;
820
821 cpu_hw_events = alloc_percpu(struct pmu_hw_events);
822 if (!cpu_hw_events)
823 return -ENOMEM;
824
825 cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
826 err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
827 if (err)
828 goto out_hw_events;
829
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +0000830 err = cpu_pm_pmu_register(cpu_pmu);
831 if (err)
832 goto out_unregister;
833
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100834 for_each_possible_cpu(cpu) {
835 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
836 raw_spin_lock_init(&events->pmu_lock);
837 events->percpu_pmu = cpu_pmu;
838 }
839
840 cpu_pmu->hw_events = cpu_hw_events;
841 cpu_pmu->request_irq = cpu_pmu_request_irq;
842 cpu_pmu->free_irq = cpu_pmu_free_irq;
843
844 /* Ensure the PMU has sane values out of reset. */
845 if (cpu_pmu->reset)
846 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
847 cpu_pmu, 1);
848
849 /* If no interrupts available, set the corresponding capability flag */
850 if (!platform_get_irq(cpu_pmu->plat_device, 0))
851 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
852
Mark Rutland5101ef22016-04-26 11:33:46 +0100853 /*
854 * This is a CPU PMU potentially in a heterogeneous configuration (e.g.
855 * big.LITTLE). This is not an uncore PMU, and we have taken ctx
856 * sharing into account (e.g. with our pmu::filter_match callback and
857 * pmu::event_init group validation).
858 */
859 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
860
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100861 return 0;
862
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +0000863out_unregister:
864 unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100865out_hw_events:
866 free_percpu(cpu_hw_events);
867 return err;
868}
869
870static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
871{
Lorenzo Pieralisida4e4f12016-02-23 18:22:39 +0000872 cpu_pm_pmu_unregister(cpu_pmu);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100873 unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
874 free_percpu(cpu_pmu->hw_events);
875}
876
877/*
878 * CPU PMU identification and probing.
879 */
880static int probe_current_pmu(struct arm_pmu *pmu,
881 const struct pmu_probe_info *info)
882{
883 int cpu = get_cpu();
884 unsigned int cpuid = read_cpuid_id();
885 int ret = -ENODEV;
886
887 pr_info("probing PMU on CPU %d\n", cpu);
888
889 for (; info->init != NULL; info++) {
890 if ((cpuid & info->mask) != info->cpuid)
891 continue;
892 ret = info->init(pmu);
893 break;
894 }
895
896 put_cpu();
897 return ret;
898}
899
900static int of_pmu_irq_cfg(struct arm_pmu *pmu)
901{
Will Deaconb6c084d2015-06-29 13:59:01 +0100902 int *irqs, i = 0;
903 bool using_spi = false;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100904 struct platform_device *pdev = pmu->plat_device;
905
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100906 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
907 if (!irqs)
908 return -ENOMEM;
909
Will Deaconb6c084d2015-06-29 13:59:01 +0100910 do {
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100911 struct device_node *dn;
Will Deaconb6c084d2015-06-29 13:59:01 +0100912 int cpu, irq;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100913
Will Deaconb6c084d2015-06-29 13:59:01 +0100914 /* See if we have an affinity entry */
915 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
916 if (!dn)
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100917 break;
Will Deaconb6c084d2015-06-29 13:59:01 +0100918
919 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
920 irq = platform_get_irq(pdev, i);
921 if (irq >= 0) {
922 bool spi = !irq_is_percpu(irq);
923
924 if (i > 0 && spi != using_spi) {
925 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
926 dn->name);
927 kfree(irqs);
928 return -EINVAL;
929 }
930
931 using_spi = spi;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100932 }
933
Will Deaconb6c084d2015-06-29 13:59:01 +0100934 /* Now look up the logical CPU number */
Will Deaconfb659882015-10-12 14:48:39 +0100935 for_each_possible_cpu(cpu) {
936 struct device_node *cpu_dn;
937
938 cpu_dn = of_cpu_device_node_get(cpu);
939 of_node_put(cpu_dn);
940
941 if (dn == cpu_dn)
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100942 break;
Will Deaconfb659882015-10-12 14:48:39 +0100943 }
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100944
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100945 if (cpu >= nr_cpu_ids) {
946 pr_warn("Failed to find logical CPU for %s\n",
947 dn->name);
Stephen Boyd8e0c34b2015-07-07 18:17:05 +0100948 of_node_put(dn);
Will Deaconb6c084d2015-06-29 13:59:01 +0100949 cpumask_setall(&pmu->supported_cpus);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100950 break;
951 }
Stephen Boyd8e0c34b2015-07-07 18:17:05 +0100952 of_node_put(dn);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100953
Will Deaconb6c084d2015-06-29 13:59:01 +0100954 /* For SPIs, we need to track the affinity per IRQ */
955 if (using_spi) {
Julien Grall121323a2016-05-31 12:41:21 +0100956 if (i >= pdev->num_resources)
Will Deaconb6c084d2015-06-29 13:59:01 +0100957 break;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100958
Will Deaconb6c084d2015-06-29 13:59:01 +0100959 irqs[i] = cpu;
960 }
961
962 /* Keep track of the CPUs containing this PMU type */
963 cpumask_set_cpu(cpu, &pmu->supported_cpus);
Will Deaconb6c084d2015-06-29 13:59:01 +0100964 i++;
965 } while (1);
966
Marc Zyngier19a469a2016-07-08 15:56:04 +0100967 /* If we didn't manage to parse anything, try the interrupt affinity */
968 if (cpumask_weight(&pmu->supported_cpus) == 0) {
969 if (!using_spi) {
970 /* If using PPIs, check the affinity of the partition */
971 int ret, irq;
972
973 irq = platform_get_irq(pdev, 0);
974 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
975 if (ret) {
976 kfree(irqs);
977 return ret;
978 }
979 } else {
980 /* Otherwise default to all CPUs */
981 cpumask_setall(&pmu->supported_cpus);
982 }
983 }
Will Deaconb6c084d2015-06-29 13:59:01 +0100984
985 /* If we matched up the IRQ affinities, use them to route the SPIs */
986 if (using_spi && i == pdev->num_resources)
987 pmu->irq_affinity = irqs;
988 else
989 kfree(irqs);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100990
991 return 0;
992}
993
994int arm_pmu_device_probe(struct platform_device *pdev,
995 const struct of_device_id *of_table,
996 const struct pmu_probe_info *probe_table)
997{
998 const struct of_device_id *of_id;
999 const int (*init_fn)(struct arm_pmu *);
1000 struct device_node *node = pdev->dev.of_node;
1001 struct arm_pmu *pmu;
1002 int ret = -ENODEV;
1003
1004 pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
1005 if (!pmu) {
1006 pr_info("failed to allocate PMU device!\n");
1007 return -ENOMEM;
1008 }
1009
Mark Rutlandb916b782015-10-28 12:32:17 +00001010 armpmu_init(pmu);
1011
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001012 pmu->plat_device = pdev;
1013
1014 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1015 init_fn = of_id->data;
1016
Martin Fuzzey8d1a0ae2016-01-13 23:36:26 -05001017 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1018 "secure-reg-access");
1019
1020 /* arm64 systems boot only as non-secure */
1021 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1022 pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1023 pmu->secure_access = false;
1024 }
1025
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001026 ret = of_pmu_irq_cfg(pmu);
1027 if (!ret)
1028 ret = init_fn(pmu);
1029 } else {
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001030 cpumask_setall(&pmu->supported_cpus);
Mark Salterf7a6c142016-06-07 11:32:21 -05001031 ret = probe_current_pmu(pmu, probe_table);
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001032 }
1033
1034 if (ret) {
Will Deacon357b5652016-03-21 11:07:15 +00001035 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001036 goto out_free;
1037 }
1038
1039 ret = cpu_pmu_init(pmu);
1040 if (ret)
1041 goto out_free;
1042
Mark Rutlandb916b782015-10-28 12:32:17 +00001043 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001044 if (ret)
1045 goto out_destroy;
1046
Julien Grall0f254c72016-05-31 12:41:22 +01001047 if (!__oprofile_cpu_pmu)
1048 __oprofile_cpu_pmu = pmu;
1049
Mark Rutlandb916b782015-10-28 12:32:17 +00001050 pr_info("enabled with %s PMU driver, %d counters available\n",
1051 pmu->name, pmu->num_events);
1052
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001053 return 0;
1054
1055out_destroy:
1056 cpu_pmu_destroy(pmu);
1057out_free:
Will Deacon357b5652016-03-21 11:07:15 +00001058 pr_info("%s: failed to register PMU devices!\n",
1059 of_node_full_name(node));
Julien Grall5988a362016-05-31 12:41:23 +01001060 kfree(pmu->irq_affinity);
Mark Rutland74cf0bc2015-05-26 17:23:39 +01001061 kfree(pmu);
1062 return ret;
1063}