Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 1 | #undef DEBUG |
| 2 | |
| 3 | /* |
| 4 | * ARM performance counter support. |
| 5 | * |
| 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 8 | * |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
| 10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace |
| 11 | * code. |
| 12 | */ |
| 13 | #define pr_fmt(fmt) "hw perfevents: " fmt |
| 14 | |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/kernel.h> |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 17 | #include <linux/module.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 18 | #include <linux/perf_event.h> |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/uaccess.h> |
| 22 | |
| 23 | #include <asm/cputype.h> |
| 24 | #include <asm/irq.h> |
| 25 | #include <asm/irq_regs.h> |
| 26 | #include <asm/pmu.h> |
| 27 | #include <asm/stacktrace.h> |
| 28 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 29 | static struct platform_device *pmu_device; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Hardware lock to serialize accesses to PMU registers. Needed for the |
| 33 | * read/modify/write sequences. |
| 34 | */ |
Will Deacon | 961ec6da | 2010-12-02 18:01:49 +0100 | [diff] [blame] | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 36 | |
| 37 | /* |
Will Deacon | ecf5a89 | 2011-07-19 22:43:28 +0100 | [diff] [blame] | 38 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 39 | * another platform that supports more, we need to increase this to be the |
| 40 | * largest of all platforms. |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 41 | * |
| 42 | * ARMv7 supports up to 32 events: |
| 43 | * cycle counter CCNT + 31 events counters CNT0..30. |
| 44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 45 | */ |
Will Deacon | ecf5a89 | 2011-07-19 22:43:28 +0100 | [diff] [blame] | 46 | #define ARMPMU_MAX_HWEVENTS 32 |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 47 | |
| 48 | /* The events for a given CPU. */ |
| 49 | struct cpu_hw_events { |
| 50 | /* |
Will Deacon | ecf5a89 | 2011-07-19 22:43:28 +0100 | [diff] [blame] | 51 | * The events that are active on the CPU for the given index. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 52 | */ |
| 53 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; |
| 54 | |
| 55 | /* |
| 56 | * A 1 bit for an index indicates that the counter is being used for |
| 57 | * an event. A 0 means that the counter can be used. |
| 58 | */ |
| 59 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 60 | }; |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 61 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 62 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 63 | struct arm_pmu { |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 64 | enum arm_perf_pmu_ids id; |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 65 | cpumask_t active_irqs; |
Will Deacon | 6299483 | 2010-11-13 18:45:27 +0000 | [diff] [blame] | 66 | const char *name; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 67 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
| 68 | void (*enable)(struct hw_perf_event *evt, int idx); |
| 69 | void (*disable)(struct hw_perf_event *evt, int idx); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 70 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
| 71 | struct hw_perf_event *hwc); |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 72 | int (*set_event_filter)(struct hw_perf_event *evt, |
| 73 | struct perf_event_attr *attr); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 74 | u32 (*read_counter)(int idx); |
| 75 | void (*write_counter)(int idx, u32 val); |
| 76 | void (*start)(void); |
| 77 | void (*stop)(void); |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 78 | void (*reset)(void *); |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 79 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
| 80 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 81 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 82 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; |
| 83 | u32 raw_event_mask; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 84 | int num_events; |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 85 | atomic_t active_events; |
| 86 | struct mutex reserve_mutex; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 87 | u64 max_period; |
| 88 | }; |
| 89 | |
| 90 | /* Set at runtime when we know what CPU type we are. */ |
Mark Rutland | a6c93af | 2011-04-15 11:14:38 +0100 | [diff] [blame] | 91 | static struct arm_pmu *armpmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 92 | |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 93 | enum arm_perf_pmu_ids |
| 94 | armpmu_get_pmu_id(void) |
| 95 | { |
| 96 | int id = -ENODEV; |
| 97 | |
| 98 | if (armpmu != NULL) |
| 99 | id = armpmu->id; |
| 100 | |
| 101 | return id; |
| 102 | } |
| 103 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); |
| 104 | |
Will Deacon | 929f519 | 2010-04-30 11:34:26 +0100 | [diff] [blame] | 105 | int |
| 106 | armpmu_get_max_events(void) |
| 107 | { |
| 108 | int max_events = 0; |
| 109 | |
| 110 | if (armpmu != NULL) |
| 111 | max_events = armpmu->num_events; |
| 112 | |
| 113 | return max_events; |
| 114 | } |
| 115 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); |
| 116 | |
Matt Fleming | 3bf101b | 2010-09-27 20:22:24 +0100 | [diff] [blame] | 117 | int perf_num_counters(void) |
| 118 | { |
| 119 | return armpmu_get_max_events(); |
| 120 | } |
| 121 | EXPORT_SYMBOL_GPL(perf_num_counters); |
| 122 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 123 | #define HW_OP_UNSUPPORTED 0xFFFF |
| 124 | |
| 125 | #define C(_x) \ |
| 126 | PERF_COUNT_HW_CACHE_##_x |
| 127 | |
| 128 | #define CACHE_OP_UNSUPPORTED 0xFFFF |
| 129 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 130 | static int |
| 131 | armpmu_map_cache_event(u64 config) |
| 132 | { |
| 133 | unsigned int cache_type, cache_op, cache_result, ret; |
| 134 | |
| 135 | cache_type = (config >> 0) & 0xff; |
| 136 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 137 | return -EINVAL; |
| 138 | |
| 139 | cache_op = (config >> 8) & 0xff; |
| 140 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 141 | return -EINVAL; |
| 142 | |
| 143 | cache_result = (config >> 16) & 0xff; |
| 144 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 145 | return -EINVAL; |
| 146 | |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 147 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 148 | |
| 149 | if (ret == CACHE_OP_UNSUPPORTED) |
| 150 | return -ENOENT; |
| 151 | |
| 152 | return ret; |
| 153 | } |
| 154 | |
| 155 | static int |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 156 | armpmu_map_event(u64 config) |
| 157 | { |
| 158 | int mapping = (*armpmu->event_map)[config]; |
| 159 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; |
| 160 | } |
| 161 | |
| 162 | static int |
| 163 | armpmu_map_raw_event(u64 config) |
| 164 | { |
| 165 | return (int)(config & armpmu->raw_event_mask); |
| 166 | } |
| 167 | |
| 168 | static int |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 169 | armpmu_event_set_period(struct perf_event *event, |
| 170 | struct hw_perf_event *hwc, |
| 171 | int idx) |
| 172 | { |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 173 | s64 left = local64_read(&hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 174 | s64 period = hwc->sample_period; |
| 175 | int ret = 0; |
| 176 | |
| 177 | if (unlikely(left <= -period)) { |
| 178 | left = period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 179 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 180 | hwc->last_period = period; |
| 181 | ret = 1; |
| 182 | } |
| 183 | |
| 184 | if (unlikely(left <= 0)) { |
| 185 | left += period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 186 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 187 | hwc->last_period = period; |
| 188 | ret = 1; |
| 189 | } |
| 190 | |
| 191 | if (left > (s64)armpmu->max_period) |
| 192 | left = armpmu->max_period; |
| 193 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 194 | local64_set(&hwc->prev_count, (u64)-left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 195 | |
| 196 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); |
| 197 | |
| 198 | perf_event_update_userpage(event); |
| 199 | |
| 200 | return ret; |
| 201 | } |
| 202 | |
| 203 | static u64 |
| 204 | armpmu_event_update(struct perf_event *event, |
| 205 | struct hw_perf_event *hwc, |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 206 | int idx, int overflow) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 207 | { |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 208 | u64 delta, prev_raw_count, new_raw_count; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 209 | |
| 210 | again: |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 211 | prev_raw_count = local64_read(&hwc->prev_count); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 212 | new_raw_count = armpmu->read_counter(idx); |
| 213 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 214 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 215 | new_raw_count) != prev_raw_count) |
| 216 | goto again; |
| 217 | |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 218 | new_raw_count &= armpmu->max_period; |
| 219 | prev_raw_count &= armpmu->max_period; |
| 220 | |
| 221 | if (overflow) |
Will Deacon | 6759788 | 2011-04-05 14:01:24 +0100 | [diff] [blame] | 222 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 223 | else |
| 224 | delta = new_raw_count - prev_raw_count; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 225 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 226 | local64_add(delta, &event->count); |
| 227 | local64_sub(delta, &hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 228 | |
| 229 | return new_raw_count; |
| 230 | } |
| 231 | |
| 232 | static void |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 233 | armpmu_read(struct perf_event *event) |
| 234 | { |
| 235 | struct hw_perf_event *hwc = &event->hw; |
| 236 | |
| 237 | /* Don't read disabled counters! */ |
| 238 | if (hwc->idx < 0) |
| 239 | return; |
| 240 | |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 241 | armpmu_event_update(event, hwc, hwc->idx, 0); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | static void |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 245 | armpmu_stop(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 246 | { |
| 247 | struct hw_perf_event *hwc = &event->hw; |
| 248 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 249 | /* |
| 250 | * ARM pmu always has to update the counter, so ignore |
| 251 | * PERF_EF_UPDATE, see comments in armpmu_start(). |
| 252 | */ |
| 253 | if (!(hwc->state & PERF_HES_STOPPED)) { |
| 254 | armpmu->disable(hwc, hwc->idx); |
| 255 | barrier(); /* why? */ |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 256 | armpmu_event_update(event, hwc, hwc->idx, 0); |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 257 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | static void |
| 262 | armpmu_start(struct perf_event *event, int flags) |
| 263 | { |
| 264 | struct hw_perf_event *hwc = &event->hw; |
| 265 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 266 | /* |
| 267 | * ARM pmu always has to reprogram the period, so ignore |
| 268 | * PERF_EF_RELOAD, see the comment below. |
| 269 | */ |
| 270 | if (flags & PERF_EF_RELOAD) |
| 271 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 272 | |
| 273 | hwc->state = 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 274 | /* |
| 275 | * Set the period again. Some counters can't be stopped, so when we |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 276 | * were stopped we simply disabled the IRQ source and the counter |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 277 | * may have been left counting. If we don't do this step then we may |
| 278 | * get an interrupt too soon or *way* too late if the overflow has |
| 279 | * happened since disabling. |
| 280 | */ |
| 281 | armpmu_event_set_period(event, hwc, hwc->idx); |
| 282 | armpmu->enable(hwc, hwc->idx); |
| 283 | } |
| 284 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 285 | static void |
| 286 | armpmu_del(struct perf_event *event, int flags) |
| 287 | { |
| 288 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 289 | struct hw_perf_event *hwc = &event->hw; |
| 290 | int idx = hwc->idx; |
| 291 | |
| 292 | WARN_ON(idx < 0); |
| 293 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 294 | armpmu_stop(event, PERF_EF_UPDATE); |
| 295 | cpuc->events[idx] = NULL; |
| 296 | clear_bit(idx, cpuc->used_mask); |
| 297 | |
| 298 | perf_event_update_userpage(event); |
| 299 | } |
| 300 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 301 | static int |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 302 | armpmu_add(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 303 | { |
| 304 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 305 | struct hw_perf_event *hwc = &event->hw; |
| 306 | int idx; |
| 307 | int err = 0; |
| 308 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 309 | perf_pmu_disable(event->pmu); |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 310 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 311 | /* If we don't have a space for the counter then finish early. */ |
| 312 | idx = armpmu->get_event_idx(cpuc, hwc); |
| 313 | if (idx < 0) { |
| 314 | err = idx; |
| 315 | goto out; |
| 316 | } |
| 317 | |
| 318 | /* |
| 319 | * If there is an event in the counter we are going to use then make |
| 320 | * sure it is disabled. |
| 321 | */ |
| 322 | event->hw.idx = idx; |
| 323 | armpmu->disable(hwc, idx); |
| 324 | cpuc->events[idx] = event; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 325 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 326 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 327 | if (flags & PERF_EF_START) |
| 328 | armpmu_start(event, PERF_EF_RELOAD); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 329 | |
| 330 | /* Propagate our changes to the userspace mapping. */ |
| 331 | perf_event_update_userpage(event); |
| 332 | |
| 333 | out: |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 334 | perf_pmu_enable(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 335 | return err; |
| 336 | } |
| 337 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 338 | static struct pmu pmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 339 | |
| 340 | static int |
| 341 | validate_event(struct cpu_hw_events *cpuc, |
| 342 | struct perf_event *event) |
| 343 | { |
| 344 | struct hw_perf_event fake_event = event->hw; |
Mark Rutland | 7b9f72c | 2011-04-27 16:22:21 +0100 | [diff] [blame] | 345 | struct pmu *leader_pmu = event->group_leader->pmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 346 | |
Mark Rutland | 7b9f72c | 2011-04-27 16:22:21 +0100 | [diff] [blame] | 347 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
Will Deacon | 65b4711 | 2010-09-02 09:32:08 +0100 | [diff] [blame] | 348 | return 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 349 | |
| 350 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; |
| 351 | } |
| 352 | |
| 353 | static int |
| 354 | validate_group(struct perf_event *event) |
| 355 | { |
| 356 | struct perf_event *sibling, *leader = event->group_leader; |
| 357 | struct cpu_hw_events fake_pmu; |
| 358 | |
| 359 | memset(&fake_pmu, 0, sizeof(fake_pmu)); |
| 360 | |
| 361 | if (!validate_event(&fake_pmu, leader)) |
| 362 | return -ENOSPC; |
| 363 | |
| 364 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
| 365 | if (!validate_event(&fake_pmu, sibling)) |
| 366 | return -ENOSPC; |
| 367 | } |
| 368 | |
| 369 | if (!validate_event(&fake_pmu, event)) |
| 370 | return -ENOSPC; |
| 371 | |
| 372 | return 0; |
| 373 | } |
| 374 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 375 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
| 376 | { |
| 377 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); |
| 378 | |
| 379 | return plat->handle_irq(irq, dev, armpmu->handle_irq); |
| 380 | } |
| 381 | |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 382 | static void |
| 383 | armpmu_release_hardware(void) |
| 384 | { |
| 385 | int i, irq, irqs; |
| 386 | |
| 387 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
| 388 | |
| 389 | for (i = 0; i < irqs; ++i) { |
| 390 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) |
| 391 | continue; |
| 392 | irq = platform_get_irq(pmu_device, i); |
| 393 | if (irq >= 0) |
| 394 | free_irq(irq, NULL); |
| 395 | } |
| 396 | |
| 397 | armpmu->stop(); |
| 398 | release_pmu(ARM_PMU_DEVICE_CPU); |
| 399 | } |
| 400 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 401 | static int |
| 402 | armpmu_reserve_hardware(void) |
| 403 | { |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 404 | struct arm_pmu_platdata *plat; |
| 405 | irq_handler_t handle_irq; |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 406 | int i, err, irq, irqs; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 407 | |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 408 | err = reserve_pmu(ARM_PMU_DEVICE_CPU); |
| 409 | if (err) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 410 | pr_warning("unable to reserve pmu\n"); |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 411 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 412 | } |
| 413 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 414 | plat = dev_get_platdata(&pmu_device->dev); |
| 415 | if (plat && plat->handle_irq) |
| 416 | handle_irq = armpmu_platform_irq; |
| 417 | else |
| 418 | handle_irq = armpmu->handle_irq; |
| 419 | |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 420 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 421 | if (irqs < 1) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 422 | pr_err("no irqs for PMUs defined\n"); |
| 423 | return -ENODEV; |
| 424 | } |
| 425 | |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 426 | for (i = 0; i < irqs; ++i) { |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 427 | err = 0; |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 428 | irq = platform_get_irq(pmu_device, i); |
| 429 | if (irq < 0) |
| 430 | continue; |
| 431 | |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 432 | /* |
| 433 | * If we have a single PMU interrupt that we can't shift, |
| 434 | * assume that we're running on a uniprocessor machine and |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 435 | * continue. Otherwise, continue without this interrupt. |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 436 | */ |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 437 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
| 438 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", |
| 439 | irq, i); |
| 440 | continue; |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 441 | } |
| 442 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 443 | err = request_irq(irq, handle_irq, |
Will Deacon | ddee87f | 2010-02-25 15:04:14 +0100 | [diff] [blame] | 444 | IRQF_DISABLED | IRQF_NOBALANCING, |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 445 | "arm-pmu", NULL); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 446 | if (err) { |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 447 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
| 448 | irq); |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 449 | armpmu_release_hardware(); |
| 450 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 451 | } |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 452 | |
| 453 | cpumask_set_cpu(i, &armpmu->active_irqs); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 454 | } |
| 455 | |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 456 | return 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 457 | } |
| 458 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 459 | static void |
| 460 | hw_perf_event_destroy(struct perf_event *event) |
| 461 | { |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 462 | atomic_t *active_events = &armpmu->active_events; |
| 463 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; |
| 464 | |
| 465 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 466 | armpmu_release_hardware(); |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 467 | mutex_unlock(pmu_reserve_mutex); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 468 | } |
| 469 | } |
| 470 | |
| 471 | static int |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 472 | event_requires_mode_exclusion(struct perf_event_attr *attr) |
| 473 | { |
| 474 | return attr->exclude_idle || attr->exclude_user || |
| 475 | attr->exclude_kernel || attr->exclude_hv; |
| 476 | } |
| 477 | |
| 478 | static int |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 479 | __hw_perf_event_init(struct perf_event *event) |
| 480 | { |
| 481 | struct hw_perf_event *hwc = &event->hw; |
| 482 | int mapping, err; |
| 483 | |
| 484 | /* Decode the generic type into an ARM event identifier. */ |
| 485 | if (PERF_TYPE_HARDWARE == event->attr.type) { |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 486 | mapping = armpmu_map_event(event->attr.config); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 487 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
| 488 | mapping = armpmu_map_cache_event(event->attr.config); |
| 489 | } else if (PERF_TYPE_RAW == event->attr.type) { |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 490 | mapping = armpmu_map_raw_event(event->attr.config); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 491 | } else { |
| 492 | pr_debug("event type %x not supported\n", event->attr.type); |
| 493 | return -EOPNOTSUPP; |
| 494 | } |
| 495 | |
| 496 | if (mapping < 0) { |
| 497 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 498 | event->attr.config); |
| 499 | return mapping; |
| 500 | } |
| 501 | |
| 502 | /* |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 503 | * We don't assign an index until we actually place the event onto |
| 504 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 505 | * yet. For SMP systems, each core has it's own PMU so we can't do any |
| 506 | * clever allocation or constraints checking at this point. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 507 | */ |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 508 | hwc->idx = -1; |
| 509 | hwc->config_base = 0; |
| 510 | hwc->config = 0; |
| 511 | hwc->event_base = 0; |
| 512 | |
| 513 | /* |
| 514 | * Check whether we need to exclude the counter from certain modes. |
| 515 | */ |
| 516 | if ((!armpmu->set_event_filter || |
| 517 | armpmu->set_event_filter(hwc, &event->attr)) && |
| 518 | event_requires_mode_exclusion(&event->attr)) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 519 | pr_debug("ARM performance counters do not support " |
| 520 | "mode exclusion\n"); |
| 521 | return -EPERM; |
| 522 | } |
| 523 | |
| 524 | /* |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 525 | * Store the event encoding into the config_base field. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 526 | */ |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 527 | hwc->config_base |= (unsigned long)mapping; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 528 | |
| 529 | if (!hwc->sample_period) { |
| 530 | hwc->sample_period = armpmu->max_period; |
| 531 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 532 | local64_set(&hwc->period_left, hwc->sample_period); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | err = 0; |
| 536 | if (event->group_leader != event) { |
| 537 | err = validate_group(event); |
| 538 | if (err) |
| 539 | return -EINVAL; |
| 540 | } |
| 541 | |
| 542 | return err; |
| 543 | } |
| 544 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 545 | static int armpmu_event_init(struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 546 | { |
| 547 | int err = 0; |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 548 | atomic_t *active_events = &armpmu->active_events; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 549 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 550 | switch (event->attr.type) { |
| 551 | case PERF_TYPE_RAW: |
| 552 | case PERF_TYPE_HARDWARE: |
| 553 | case PERF_TYPE_HW_CACHE: |
| 554 | break; |
| 555 | |
| 556 | default: |
| 557 | return -ENOENT; |
| 558 | } |
| 559 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 560 | event->destroy = hw_perf_event_destroy; |
| 561 | |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 562 | if (!atomic_inc_not_zero(active_events)) { |
| 563 | mutex_lock(&armpmu->reserve_mutex); |
| 564 | if (atomic_read(active_events) == 0) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 565 | err = armpmu_reserve_hardware(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 566 | |
| 567 | if (!err) |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 568 | atomic_inc(active_events); |
| 569 | mutex_unlock(&armpmu->reserve_mutex); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | if (err) |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 573 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 574 | |
| 575 | err = __hw_perf_event_init(event); |
| 576 | if (err) |
| 577 | hw_perf_event_destroy(event); |
| 578 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 579 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 580 | } |
| 581 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 582 | static void armpmu_enable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 583 | { |
| 584 | /* Enable all of the perf events on hardware. */ |
Will Deacon | f4f3843 | 2011-07-01 14:38:12 +0100 | [diff] [blame] | 585 | int idx, enabled = 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 586 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 587 | |
Will Deacon | ecf5a89 | 2011-07-19 22:43:28 +0100 | [diff] [blame] | 588 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 589 | struct perf_event *event = cpuc->events[idx]; |
| 590 | |
| 591 | if (!event) |
| 592 | continue; |
| 593 | |
| 594 | armpmu->enable(&event->hw, idx); |
Will Deacon | f4f3843 | 2011-07-01 14:38:12 +0100 | [diff] [blame] | 595 | enabled = 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 596 | } |
| 597 | |
Will Deacon | f4f3843 | 2011-07-01 14:38:12 +0100 | [diff] [blame] | 598 | if (enabled) |
| 599 | armpmu->start(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 600 | } |
| 601 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 602 | static void armpmu_disable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 603 | { |
Mark Rutland | 4895715 | 2011-04-27 10:31:51 +0100 | [diff] [blame] | 604 | armpmu->stop(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 605 | } |
| 606 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 607 | static struct pmu pmu = { |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 608 | .pmu_enable = armpmu_enable, |
| 609 | .pmu_disable = armpmu_disable, |
| 610 | .event_init = armpmu_event_init, |
| 611 | .add = armpmu_add, |
| 612 | .del = armpmu_del, |
| 613 | .start = armpmu_start, |
| 614 | .stop = armpmu_stop, |
| 615 | .read = armpmu_read, |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 616 | }; |
| 617 | |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 618 | static void __init armpmu_init(struct arm_pmu *armpmu) |
| 619 | { |
| 620 | atomic_set(&armpmu->active_events, 0); |
| 621 | mutex_init(&armpmu->reserve_mutex); |
| 622 | } |
| 623 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 624 | /* Include the PMU-specific implementations. */ |
| 625 | #include "perf_event_xscale.c" |
| 626 | #include "perf_event_v6.c" |
| 627 | #include "perf_event_v7.c" |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 628 | |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 629 | /* |
| 630 | * Ensure the PMU has sane values out of reset. |
| 631 | * This requires SMP to be available, so exists as a separate initcall. |
| 632 | */ |
| 633 | static int __init |
| 634 | armpmu_reset(void) |
| 635 | { |
| 636 | if (armpmu && armpmu->reset) |
| 637 | return on_each_cpu(armpmu->reset, NULL, 1); |
| 638 | return 0; |
| 639 | } |
| 640 | arch_initcall(armpmu_reset); |
| 641 | |
Will Deacon | b0e8959 | 2011-07-26 22:10:28 +0100 | [diff] [blame] | 642 | /* |
| 643 | * PMU platform driver and devicetree bindings. |
| 644 | */ |
| 645 | static struct of_device_id armpmu_of_device_ids[] = { |
| 646 | {.compatible = "arm,cortex-a9-pmu"}, |
| 647 | {.compatible = "arm,cortex-a8-pmu"}, |
| 648 | {.compatible = "arm,arm1136-pmu"}, |
| 649 | {.compatible = "arm,arm1176-pmu"}, |
| 650 | {}, |
| 651 | }; |
| 652 | |
| 653 | static struct platform_device_id armpmu_plat_device_ids[] = { |
| 654 | {.name = "arm-pmu"}, |
| 655 | {}, |
| 656 | }; |
| 657 | |
| 658 | static int __devinit armpmu_device_probe(struct platform_device *pdev) |
| 659 | { |
| 660 | pmu_device = pdev; |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | static struct platform_driver armpmu_driver = { |
| 665 | .driver = { |
| 666 | .name = "arm-pmu", |
| 667 | .of_match_table = armpmu_of_device_ids, |
| 668 | }, |
| 669 | .probe = armpmu_device_probe, |
| 670 | .id_table = armpmu_plat_device_ids, |
| 671 | }; |
| 672 | |
| 673 | static int __init register_pmu_driver(void) |
| 674 | { |
| 675 | return platform_driver_register(&armpmu_driver); |
| 676 | } |
| 677 | device_initcall(register_pmu_driver); |
| 678 | |
| 679 | /* |
| 680 | * CPU PMU identification and registration. |
| 681 | */ |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 682 | static int __init |
| 683 | init_hw_perf_events(void) |
| 684 | { |
| 685 | unsigned long cpuid = read_cpuid_id(); |
| 686 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; |
| 687 | unsigned long part_number = (cpuid & 0xFFF0); |
| 688 | |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 689 | /* ARM Ltd CPUs. */ |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 690 | if (0x41 == implementor) { |
| 691 | switch (part_number) { |
| 692 | case 0xB360: /* ARM1136 */ |
| 693 | case 0xB560: /* ARM1156 */ |
| 694 | case 0xB760: /* ARM1176 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 695 | armpmu = armv6pmu_init(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 696 | break; |
| 697 | case 0xB020: /* ARM11mpcore */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 698 | armpmu = armv6mpcore_pmu_init(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 699 | break; |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 700 | case 0xC080: /* Cortex-A8 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 701 | armpmu = armv7_a8_pmu_init(); |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 702 | break; |
| 703 | case 0xC090: /* Cortex-A9 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 704 | armpmu = armv7_a9_pmu_init(); |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 705 | break; |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 706 | case 0xC050: /* Cortex-A5 */ |
| 707 | armpmu = armv7_a5_pmu_init(); |
| 708 | break; |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 709 | case 0xC0F0: /* Cortex-A15 */ |
| 710 | armpmu = armv7_a15_pmu_init(); |
| 711 | break; |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 712 | } |
| 713 | /* Intel CPUs [xscale]. */ |
| 714 | } else if (0x69 == implementor) { |
| 715 | part_number = (cpuid >> 13) & 0x7; |
| 716 | switch (part_number) { |
| 717 | case 1: |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 718 | armpmu = xscale1pmu_init(); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 719 | break; |
| 720 | case 2: |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 721 | armpmu = xscale2pmu_init(); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 722 | break; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 723 | } |
| 724 | } |
| 725 | |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 726 | if (armpmu) { |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 727 | pr_info("enabled with %s PMU driver, %d counters available\n", |
Will Deacon | 6299483 | 2010-11-13 18:45:27 +0000 | [diff] [blame] | 728 | armpmu->name, armpmu->num_events); |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame^] | 729 | armpmu_init(armpmu); |
Mark Rutland | 4895715 | 2011-04-27 10:31:51 +0100 | [diff] [blame] | 730 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 731 | } else { |
| 732 | pr_info("no hardware support available\n"); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 733 | } |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 734 | |
| 735 | return 0; |
| 736 | } |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 737 | early_initcall(init_hw_perf_events); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 738 | |
| 739 | /* |
| 740 | * Callchain handling code. |
| 741 | */ |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 742 | |
| 743 | /* |
| 744 | * The registers we're interested in are at the end of the variable |
| 745 | * length saved register structure. The fp points at the end of this |
| 746 | * structure so the address of this struct is: |
| 747 | * (struct frame_tail *)(xxx->fp)-1 |
| 748 | * |
| 749 | * This code has been adapted from the ARM OProfile support. |
| 750 | */ |
| 751 | struct frame_tail { |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 752 | struct frame_tail __user *fp; |
| 753 | unsigned long sp; |
| 754 | unsigned long lr; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 755 | } __attribute__((packed)); |
| 756 | |
| 757 | /* |
| 758 | * Get the return address for a single stackframe and return a pointer to the |
| 759 | * next frame tail. |
| 760 | */ |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 761 | static struct frame_tail __user * |
| 762 | user_backtrace(struct frame_tail __user *tail, |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 763 | struct perf_callchain_entry *entry) |
| 764 | { |
| 765 | struct frame_tail buftail; |
| 766 | |
| 767 | /* Also check accessibility of one struct frame_tail beyond */ |
| 768 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) |
| 769 | return NULL; |
| 770 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) |
| 771 | return NULL; |
| 772 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 773 | perf_callchain_store(entry, buftail.lr); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 774 | |
| 775 | /* |
| 776 | * Frame pointers should strictly progress back up the stack |
| 777 | * (towards higher addresses). |
| 778 | */ |
Rabin Vincent | cb06199 | 2011-02-09 11:35:12 +0100 | [diff] [blame] | 779 | if (tail + 1 >= buftail.fp) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 780 | return NULL; |
| 781 | |
| 782 | return buftail.fp - 1; |
| 783 | } |
| 784 | |
Frederic Weisbecker | 56962b444 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 785 | void |
| 786 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 787 | { |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 788 | struct frame_tail __user *tail; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 789 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 790 | |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 791 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 792 | |
Sonny Rao | 860ad78 | 2011-04-18 22:12:59 +0100 | [diff] [blame] | 793 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
| 794 | tail && !((unsigned long)tail & 0x3)) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 795 | tail = user_backtrace(tail, entry); |
| 796 | } |
| 797 | |
| 798 | /* |
| 799 | * Gets called by walk_stackframe() for every stackframe. This will be called |
| 800 | * whist unwinding the stackframe and is like a subroutine return so we use |
| 801 | * the PC. |
| 802 | */ |
| 803 | static int |
| 804 | callchain_trace(struct stackframe *fr, |
| 805 | void *data) |
| 806 | { |
| 807 | struct perf_callchain_entry *entry = data; |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 808 | perf_callchain_store(entry, fr->pc); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 809 | return 0; |
| 810 | } |
| 811 | |
Frederic Weisbecker | 56962b444 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 812 | void |
| 813 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 814 | { |
| 815 | struct stackframe fr; |
| 816 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 817 | fr.fp = regs->ARM_fp; |
| 818 | fr.sp = regs->ARM_sp; |
| 819 | fr.lr = regs->ARM_lr; |
| 820 | fr.pc = regs->ARM_pc; |
| 821 | walk_stackframe(&fr, callchain_trace, entry); |
| 822 | } |