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Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001/*
2 * omap iommu: tlb and pagetable primitives
3 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08004 * Copyright (C) 2008-2010 Nokia Corporation
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02005 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020016#include <linux/interrupt.h>
17#include <linux/ioport.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020018#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030019#include <linux/iommu.h>
Tony Lindgrenc8d35c82012-11-02 12:24:03 -070020#include <linux/omap-iommu.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030021#include <linux/mutex.h>
22#include <linux/spinlock.h>
Tony Lindgrened1c7de2012-11-02 12:24:06 -070023#include <linux/io.h>
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -060024#include <linux/pm_runtime.h>
Florian Vaussard3c927482014-02-28 14:42:36 -060025#include <linux/of.h>
26#include <linux/of_iommu.h>
27#include <linux/of_irq.h>
Suman Anna7d682772014-09-04 17:27:30 -050028#include <linux/of_platform.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020029
30#include <asm/cacheflush.h>
31
Tony Lindgren2ab7c842012-11-02 12:24:14 -070032#include <linux/platform_data/iommu-omap.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020033
Ido Yariv2f7702a2012-11-02 12:24:00 -070034#include "omap-iopgtable.h"
Tony Lindgrened1c7de2012-11-02 12:24:06 -070035#include "omap-iommu.h"
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020036
Suman Anna5acc97d2014-03-17 20:31:34 -050037#define to_iommu(dev) \
38 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)))
39
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020040/* bitmap of the page sizes currently supported */
41#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
42
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030043/**
44 * struct omap_iommu_domain - omap iommu domain
45 * @pgtable: the page table
46 * @iommu_dev: an omap iommu device attached to this domain. only a single
47 * iommu device can be attached for now.
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050048 * @dev: Device using this domain.
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030049 * @lock: domain lock, should be taken when attaching/detaching
50 */
51struct omap_iommu_domain {
52 u32 *pgtable;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030053 struct omap_iommu *iommu_dev;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050054 struct device *dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030055 spinlock_t lock;
Joerg Roedel8cf851e2015-03-26 13:43:09 +010056 struct iommu_domain domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030057};
58
Ido Yariv7bd9e252012-11-02 12:24:09 -070059#define MMU_LOCK_BASE_SHIFT 10
60#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
61#define MMU_LOCK_BASE(x) \
62 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
63
64#define MMU_LOCK_VICT_SHIFT 4
65#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
66#define MMU_LOCK_VICT(x) \
67 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
68
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020069static struct platform_driver omap_iommu_driver;
70static struct kmem_cache *iopte_cachep;
71
72/**
Joerg Roedel8cf851e2015-03-26 13:43:09 +010073 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
74 * @dom: generic iommu domain handle
75 **/
76static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
77{
78 return container_of(dom, struct omap_iommu_domain, domain);
79}
80
81/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030082 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020083 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020084 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020085void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020086{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020087 struct omap_iommu *obj = dev_to_omap_iommu(dev);
Suman Annabd4396f2014-10-22 17:22:27 -050088 u32 *p = obj->ctx;
89 int i;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020090
Suman Annabd4396f2014-10-22 17:22:27 -050091 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
92 p[i] = iommu_read_reg(obj, i * sizeof(u32));
93 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
94 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020095}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030096EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020097
98/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030099 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200100 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200101 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200102void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200103{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200104 struct omap_iommu *obj = dev_to_omap_iommu(dev);
Suman Annabd4396f2014-10-22 17:22:27 -0500105 u32 *p = obj->ctx;
106 int i;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200107
Suman Annabd4396f2014-10-22 17:22:27 -0500108 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
109 iommu_write_reg(obj, p[i], i * sizeof(u32));
110 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
111 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200112}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300113EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200114
Suman Annabd4396f2014-10-22 17:22:27 -0500115static void __iommu_set_twl(struct omap_iommu *obj, bool on)
116{
117 u32 l = iommu_read_reg(obj, MMU_CNTL);
118
119 if (on)
120 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
121 else
122 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
123
124 l &= ~MMU_CNTL_MASK;
125 if (on)
126 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
127 else
128 l |= (MMU_CNTL_MMU_EN);
129
130 iommu_write_reg(obj, l, MMU_CNTL);
131}
132
133static int omap2_iommu_enable(struct omap_iommu *obj)
134{
135 u32 l, pa;
136
137 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
138 return -EINVAL;
139
140 pa = virt_to_phys(obj->iopgd);
141 if (!IS_ALIGNED(pa, SZ_16K))
142 return -EINVAL;
143
144 l = iommu_read_reg(obj, MMU_REVISION);
145 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
146 (l >> 4) & 0xf, l & 0xf);
147
148 iommu_write_reg(obj, pa, MMU_TTB);
149
150 if (obj->has_bus_err_back)
151 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
152
153 __iommu_set_twl(obj, true);
154
155 return 0;
156}
157
158static void omap2_iommu_disable(struct omap_iommu *obj)
159{
160 u32 l = iommu_read_reg(obj, MMU_CNTL);
161
162 l &= ~MMU_CNTL_MASK;
163 iommu_write_reg(obj, l, MMU_CNTL);
164
165 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
166}
167
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300168static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200169{
170 int err;
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600171 struct platform_device *pdev = to_platform_device(obj->dev);
Kiran Padwal99cb9ae2014-10-30 11:59:47 +0530172 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200173
Florian Vaussard90e569c2014-02-28 14:42:34 -0600174 if (pdata && pdata->deassert_reset) {
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600175 err = pdata->deassert_reset(pdev, pdata->reset_name);
176 if (err) {
177 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
178 return err;
179 }
180 }
181
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600182 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200183
Suman Annabd4396f2014-10-22 17:22:27 -0500184 err = omap2_iommu_enable(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200185
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200186 return err;
187}
188
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300189static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200190{
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600191 struct platform_device *pdev = to_platform_device(obj->dev);
Kiran Padwal99cb9ae2014-10-30 11:59:47 +0530192 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600193
Suman Annabd4396f2014-10-22 17:22:27 -0500194 omap2_iommu_disable(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200195
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600196 pm_runtime_put_sync(obj->dev);
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600197
Florian Vaussard90e569c2014-02-28 14:42:34 -0600198 if (pdata && pdata->assert_reset)
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600199 pdata->assert_reset(pdev, pdata->reset_name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200200}
201
202/*
203 * TLB operations
204 */
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300205static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200206{
Suman Annabd4396f2014-10-22 17:22:27 -0500207 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
208 u32 mask = get_cam_va_mask(cr->cam & page_size);
209
210 return cr->cam & mask;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200211}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200212
213static u32 get_iopte_attr(struct iotlb_entry *e)
214{
Suman Annabd4396f2014-10-22 17:22:27 -0500215 u32 attr;
216
217 attr = e->mixed << 5;
218 attr |= e->endian;
219 attr |= e->elsz >> 3;
220 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
221 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
222 return attr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200223}
224
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300225static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200226{
Suman Annabd4396f2014-10-22 17:22:27 -0500227 u32 status, fault_addr;
228
229 status = iommu_read_reg(obj, MMU_IRQSTATUS);
230 status &= MMU_IRQ_MASK;
231 if (!status) {
232 *da = 0;
233 return 0;
234 }
235
236 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
237 *da = fault_addr;
238
239 iommu_write_reg(obj, status, MMU_IRQSTATUS);
240
241 return status;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200242}
243
Suman Anna69c2c192015-07-20 17:33:25 -0500244void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200245{
246 u32 val;
247
248 val = iommu_read_reg(obj, MMU_LOCK);
249
250 l->base = MMU_LOCK_BASE(val);
251 l->vict = MMU_LOCK_VICT(val);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200252}
253
Suman Anna69c2c192015-07-20 17:33:25 -0500254void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200255{
256 u32 val;
257
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200258 val = (l->base << MMU_LOCK_BASE_SHIFT);
259 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
260
261 iommu_write_reg(obj, val, MMU_LOCK);
262}
263
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300264static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200265{
Suman Annabd4396f2014-10-22 17:22:27 -0500266 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
267 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200268}
269
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300270static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200271{
Suman Annabd4396f2014-10-22 17:22:27 -0500272 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
273 iommu_write_reg(obj, cr->ram, MMU_RAM);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200274
275 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
276 iommu_write_reg(obj, 1, MMU_LD_TLB);
277}
278
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000279/* only used in iotlb iteration for-loop */
Suman Anna69c2c192015-07-20 17:33:25 -0500280struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000281{
282 struct cr_regs cr;
283 struct iotlb_lock l;
284
285 iotlb_lock_get(obj, &l);
286 l.vict = n;
287 iotlb_lock_set(obj, &l);
288 iotlb_read_cr(obj, &cr);
289
290 return cr;
291}
292
Suman Annabd4396f2014-10-22 17:22:27 -0500293#ifdef PREFETCH_IOTLB
294static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
295 struct iotlb_entry *e)
296{
297 struct cr_regs *cr;
298
299 if (!e)
300 return NULL;
301
302 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
303 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
304 e->da);
305 return ERR_PTR(-EINVAL);
306 }
307
308 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
309 if (!cr)
310 return ERR_PTR(-ENOMEM);
311
312 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
313 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
314
315 return cr;
316}
317
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200318/**
319 * load_iotlb_entry - Set an iommu tlb entry
320 * @obj: target iommu
321 * @e: an iommu tlb entry info
322 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300323static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200324{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200325 int err = 0;
326 struct iotlb_lock l;
327 struct cr_regs *cr;
328
329 if (!obj || !obj->nr_tlb_entries || !e)
330 return -EINVAL;
331
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600332 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200333
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000334 iotlb_lock_get(obj, &l);
335 if (l.base == obj->nr_tlb_entries) {
336 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200337 err = -EBUSY;
338 goto out;
339 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000340 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000341 int i;
342 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000343
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000344 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000345 if (!iotlb_cr_valid(&tmp))
346 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000347
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000348 if (i == obj->nr_tlb_entries) {
349 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
350 err = -EBUSY;
351 goto out;
352 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000353
354 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000355 } else {
356 l.vict = l.base;
357 iotlb_lock_set(obj, &l);
358 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200359
360 cr = iotlb_alloc_cr(obj, e);
361 if (IS_ERR(cr)) {
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600362 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200363 return PTR_ERR(cr);
364 }
365
366 iotlb_load_cr(obj, cr);
367 kfree(cr);
368
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000369 if (e->prsvd)
370 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200371 /* increment victim for next tlb load */
372 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000373 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200374 iotlb_lock_set(obj, &l);
375out:
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600376 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200377 return err;
378}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200379
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300380#else /* !PREFETCH_IOTLB */
381
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300382static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300383{
384 return 0;
385}
386
387#endif /* !PREFETCH_IOTLB */
388
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300389static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300390{
391 return load_iotlb_entry(obj, e);
392}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200393
394/**
395 * flush_iotlb_page - Clear an iommu tlb entry
396 * @obj: target iommu
397 * @da: iommu device virtual address
398 *
399 * Clear an iommu tlb entry which includes 'da' address.
400 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300401static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200402{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200403 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000404 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200405
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600406 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200407
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000408 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200409 u32 start;
410 size_t bytes;
411
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200412 if (!iotlb_cr_valid(&cr))
413 continue;
414
415 start = iotlb_cr_to_virt(&cr);
416 bytes = iopgsz_to_bytes(cr.cam & 3);
417
418 if ((start <= da) && (da < start + bytes)) {
419 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
420 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000421 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200422 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
Laurent Pinchartf7129a02014-03-07 23:47:03 +0100423 break;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200424 }
425 }
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600426 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200427
428 if (i == obj->nr_tlb_entries)
429 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
430}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200431
432/**
433 * flush_iotlb_all - Clear all iommu tlb entries
434 * @obj: target iommu
435 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300436static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200437{
438 struct iotlb_lock l;
439
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600440 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200441
442 l.base = 0;
443 l.vict = 0;
444 iotlb_lock_set(obj, &l);
445
446 iommu_write_reg(obj, 1, MMU_GFLUSH);
447
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600448 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200449}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200450
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200451/*
452 * H/W pagetable operations
453 */
454static void flush_iopgd_range(u32 *first, u32 *last)
455{
456 /* FIXME: L2 cache should be taken care of if it exists */
457 do {
458 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
459 : : "r" (first));
460 first += L1_CACHE_BYTES / sizeof(*first);
461 } while (first <= last);
462}
463
464static void flush_iopte_range(u32 *first, u32 *last)
465{
466 /* FIXME: L2 cache should be taken care of if it exists */
467 do {
468 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
469 : : "r" (first));
470 first += L1_CACHE_BYTES / sizeof(*first);
471 } while (first <= last);
472}
473
474static void iopte_free(u32 *iopte)
475{
476 /* Note: freed iopte's must be clean ready for re-use */
Zhouyi Zhoue28045a2014-03-05 18:20:19 +0800477 if (iopte)
478 kmem_cache_free(iopte_cachep, iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200479}
480
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300481static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200482{
483 u32 *iopte;
484
485 /* a table has already existed */
486 if (*iopgd)
487 goto pte_ready;
488
489 /*
490 * do the allocation outside the page table lock
491 */
492 spin_unlock(&obj->page_table_lock);
493 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
494 spin_lock(&obj->page_table_lock);
495
496 if (!*iopgd) {
497 if (!iopte)
498 return ERR_PTR(-ENOMEM);
499
500 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
501 flush_iopgd_range(iopgd, iopgd);
502
503 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
504 } else {
505 /* We raced, free the reduniovant table */
506 iopte_free(iopte);
507 }
508
509pte_ready:
510 iopte = iopte_offset(iopgd, da);
511
512 dev_vdbg(obj->dev,
513 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
514 __func__, da, iopgd, *iopgd, iopte, *iopte);
515
516 return iopte;
517}
518
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300519static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200520{
521 u32 *iopgd = iopgd_offset(obj, da);
522
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300523 if ((da | pa) & ~IOSECTION_MASK) {
524 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
525 __func__, da, pa, IOSECTION_SIZE);
526 return -EINVAL;
527 }
528
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200529 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
530 flush_iopgd_range(iopgd, iopgd);
531 return 0;
532}
533
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300534static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200535{
536 u32 *iopgd = iopgd_offset(obj, da);
537 int i;
538
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300539 if ((da | pa) & ~IOSUPER_MASK) {
540 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
541 __func__, da, pa, IOSUPER_SIZE);
542 return -EINVAL;
543 }
544
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200545 for (i = 0; i < 16; i++)
546 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
547 flush_iopgd_range(iopgd, iopgd + 15);
548 return 0;
549}
550
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300551static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200552{
553 u32 *iopgd = iopgd_offset(obj, da);
554 u32 *iopte = iopte_alloc(obj, iopgd, da);
555
556 if (IS_ERR(iopte))
557 return PTR_ERR(iopte);
558
559 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
560 flush_iopte_range(iopte, iopte);
561
562 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
563 __func__, da, pa, iopte, *iopte);
564
565 return 0;
566}
567
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300568static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200569{
570 u32 *iopgd = iopgd_offset(obj, da);
571 u32 *iopte = iopte_alloc(obj, iopgd, da);
572 int i;
573
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300574 if ((da | pa) & ~IOLARGE_MASK) {
575 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
576 __func__, da, pa, IOLARGE_SIZE);
577 return -EINVAL;
578 }
579
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200580 if (IS_ERR(iopte))
581 return PTR_ERR(iopte);
582
583 for (i = 0; i < 16; i++)
584 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
585 flush_iopte_range(iopte, iopte + 15);
586 return 0;
587}
588
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300589static int
590iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200591{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300592 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200593 u32 prot;
594 int err;
595
596 if (!obj || !e)
597 return -EINVAL;
598
599 switch (e->pgsz) {
600 case MMU_CAM_PGSZ_16M:
601 fn = iopgd_alloc_super;
602 break;
603 case MMU_CAM_PGSZ_1M:
604 fn = iopgd_alloc_section;
605 break;
606 case MMU_CAM_PGSZ_64K:
607 fn = iopte_alloc_large;
608 break;
609 case MMU_CAM_PGSZ_4K:
610 fn = iopte_alloc_page;
611 break;
612 default:
613 fn = NULL;
614 BUG();
615 break;
616 }
617
618 prot = get_iopte_attr(e);
619
620 spin_lock(&obj->page_table_lock);
621 err = fn(obj, e->da, e->pa, prot);
622 spin_unlock(&obj->page_table_lock);
623
624 return err;
625}
626
627/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300628 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200629 * @obj: target iommu
630 * @e: an iommu tlb entry info
631 **/
Suman Anna4899a562014-10-22 17:22:32 -0500632static int
633omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200634{
635 int err;
636
637 flush_iotlb_page(obj, e->da);
638 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200639 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300640 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200641 return err;
642}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200643
644/**
645 * iopgtable_lookup_entry - Lookup an iommu pte entry
646 * @obj: target iommu
647 * @da: iommu device virtual address
648 * @ppgd: iommu pgd entry pointer to be returned
649 * @ppte: iommu pte entry pointer to be returned
650 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300651static void
652iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200653{
654 u32 *iopgd, *iopte = NULL;
655
656 iopgd = iopgd_offset(obj, da);
657 if (!*iopgd)
658 goto out;
659
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300660 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200661 iopte = iopte_offset(iopgd, da);
662out:
663 *ppgd = iopgd;
664 *ppte = iopte;
665}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200666
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300667static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200668{
669 size_t bytes;
670 u32 *iopgd = iopgd_offset(obj, da);
671 int nent = 1;
672
673 if (!*iopgd)
674 return 0;
675
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300676 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200677 int i;
678 u32 *iopte = iopte_offset(iopgd, da);
679
680 bytes = IOPTE_SIZE;
681 if (*iopte & IOPTE_LARGE) {
682 nent *= 16;
683 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800684 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200685 }
686 bytes *= nent;
687 memset(iopte, 0, nent * sizeof(*iopte));
688 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
689
690 /*
691 * do table walk to check if this table is necessary or not
692 */
693 iopte = iopte_offset(iopgd, 0);
694 for (i = 0; i < PTRS_PER_IOPTE; i++)
695 if (iopte[i])
696 goto out;
697
698 iopte_free(iopte);
699 nent = 1; /* for the next L1 entry */
700 } else {
701 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700702 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200703 nent *= 16;
704 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800705 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200706 }
707 bytes *= nent;
708 }
709 memset(iopgd, 0, nent * sizeof(*iopgd));
710 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
711out:
712 return bytes;
713}
714
715/**
716 * iopgtable_clear_entry - Remove an iommu pte entry
717 * @obj: target iommu
718 * @da: iommu device virtual address
719 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300720static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200721{
722 size_t bytes;
723
724 spin_lock(&obj->page_table_lock);
725
726 bytes = iopgtable_clear_entry_core(obj, da);
727 flush_iotlb_page(obj, da);
728
729 spin_unlock(&obj->page_table_lock);
730
731 return bytes;
732}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200733
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300734static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200735{
736 int i;
737
738 spin_lock(&obj->page_table_lock);
739
740 for (i = 0; i < PTRS_PER_IOPGD; i++) {
741 u32 da;
742 u32 *iopgd;
743
744 da = i << IOPGD_SHIFT;
745 iopgd = iopgd_offset(obj, da);
746
747 if (!*iopgd)
748 continue;
749
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300750 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200751 iopte_free(iopte_offset(iopgd, 0));
752
753 *iopgd = 0;
754 flush_iopgd_range(iopgd, iopgd);
755 }
756
757 flush_iotlb_all(obj);
758
759 spin_unlock(&obj->page_table_lock);
760}
761
762/*
763 * Device IOMMU generic operations
764 */
765static irqreturn_t iommu_fault_handler(int irq, void *data)
766{
David Cohend594f1f2011-02-16 19:35:51 +0000767 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200768 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300769 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400770 struct iommu_domain *domain = obj->domain;
Joerg Roedel8cf851e2015-03-26 13:43:09 +0100771 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200772
Suman Anna2088ecb2014-10-22 17:22:19 -0500773 if (!omap_domain->iommu_dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200774 return IRQ_NONE;
775
David Cohend594f1f2011-02-16 19:35:51 +0000776 errs = iommu_report_fault(obj, &da);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200777 if (errs == 0)
778 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000779
780 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400781 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200782 return IRQ_HANDLED;
783
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000784 iommu_disable(obj);
785
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200786 iopgd = iopgd_offset(obj, da);
787
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300788 if (!iopgd_is_table(*iopgd)) {
Suman Annab6c2e092013-05-30 18:10:59 -0500789 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
Suman Anna5835b6a2015-07-20 17:33:32 -0500790 obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200791 return IRQ_NONE;
792 }
793
794 iopte = iopte_offset(iopgd, da);
795
Suman Annab6c2e092013-05-30 18:10:59 -0500796 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
Suman Anna5835b6a2015-07-20 17:33:32 -0500797 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200798
799 return IRQ_NONE;
800}
801
802static int device_match_by_alias(struct device *dev, void *data)
803{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300804 struct omap_iommu *obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200805 const char *name = data;
806
807 pr_debug("%s: %s %s\n", __func__, obj->name, name);
808
809 return strcmp(obj->name, name) == 0;
810}
811
812/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300813 * omap_iommu_attach() - attach iommu device to an iommu domain
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200814 * @name: name of target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300815 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200816 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200817static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200818{
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600819 int err;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200820 struct device *dev;
821 struct omap_iommu *obj;
822
Suman Anna5835b6a2015-07-20 17:33:32 -0500823 dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
824 device_match_by_alias);
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200825 if (!dev)
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600826 return ERR_PTR(-ENODEV);
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200827
828 obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200829
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300830 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200831
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300832 obj->iopgd = iopgd;
833 err = iommu_enable(obj);
834 if (err)
835 goto err_enable;
836 flush_iotlb_all(obj);
837
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300838 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200839
840 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
841 return obj;
842
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200843err_enable:
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300844 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200845 return ERR_PTR(err);
846}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200847
848/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300849 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200850 * @obj: target iommu
851 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300852static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200853{
Roel Kluinacf9d462010-01-08 10:29:05 -0800854 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200855 return;
856
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300857 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200858
Suman Anna2088ecb2014-10-22 17:22:19 -0500859 iommu_disable(obj);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300860 obj->iopgd = NULL;
861
862 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200863
864 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
865}
David Cohend594f1f2011-02-16 19:35:51 +0000866
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200867/*
868 * OMAP Device MMU(IOMMU) detection
869 */
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800870static int omap_iommu_probe(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200871{
872 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200873 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300874 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200875 struct resource *res;
Kiran Padwal99cb9ae2014-10-30 11:59:47 +0530876 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
Florian Vaussard3c927482014-02-28 14:42:36 -0600877 struct device_node *of = pdev->dev.of_node;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200878
Suman Annaf129b3d2014-02-28 14:42:32 -0600879 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200880 if (!obj)
881 return -ENOMEM;
882
Florian Vaussard3c927482014-02-28 14:42:36 -0600883 if (of) {
884 obj->name = dev_name(&pdev->dev);
885 obj->nr_tlb_entries = 32;
886 err = of_property_read_u32(of, "ti,#tlb-entries",
887 &obj->nr_tlb_entries);
888 if (err && err != -EINVAL)
889 return err;
890 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
891 return -EINVAL;
Suman Annab148d5f2014-02-28 14:42:37 -0600892 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
893 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
Florian Vaussard3c927482014-02-28 14:42:36 -0600894 } else {
895 obj->nr_tlb_entries = pdata->nr_tlb_entries;
896 obj->name = pdata->name;
Florian Vaussard3c927482014-02-28 14:42:36 -0600897 }
Florian Vaussard3c927482014-02-28 14:42:36 -0600898
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200899 obj->dev = &pdev->dev;
900 obj->ctx = (void *)obj + sizeof(*obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200901
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300902 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200903 spin_lock_init(&obj->page_table_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200904
905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -0600906 obj->regbase = devm_ioremap_resource(obj->dev, res);
907 if (IS_ERR(obj->regbase))
908 return PTR_ERR(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000909
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200910 irq = platform_get_irq(pdev, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -0600911 if (irq < 0)
912 return -ENODEV;
913
914 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
915 dev_name(obj->dev), obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200916 if (err < 0)
Suman Annaf129b3d2014-02-28 14:42:32 -0600917 return err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200918 platform_set_drvdata(pdev, obj);
919
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600920 pm_runtime_irq_safe(obj->dev);
921 pm_runtime_enable(obj->dev);
922
Suman Anna61c75352014-10-22 17:22:30 -0500923 omap_iommu_debugfs_add(obj);
924
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200925 dev_info(&pdev->dev, "%s registered\n", obj->name);
926 return 0;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200927}
928
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800929static int omap_iommu_remove(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200930{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300931 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200932
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200933 iopgtable_clear_entry_all(obj);
Suman Anna61c75352014-10-22 17:22:30 -0500934 omap_iommu_debugfs_remove(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200935
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600936 pm_runtime_disable(obj->dev);
937
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200938 dev_info(&pdev->dev, "%s removed\n", obj->name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200939 return 0;
940}
941
Kiran Padwald943b0f2014-09-11 19:07:36 +0530942static const struct of_device_id omap_iommu_of_match[] = {
Florian Vaussard3c927482014-02-28 14:42:36 -0600943 { .compatible = "ti,omap2-iommu" },
944 { .compatible = "ti,omap4-iommu" },
945 { .compatible = "ti,dra7-iommu" },
946 {},
947};
Florian Vaussard3c927482014-02-28 14:42:36 -0600948
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200949static struct platform_driver omap_iommu_driver = {
950 .probe = omap_iommu_probe,
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800951 .remove = omap_iommu_remove,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200952 .driver = {
953 .name = "omap-iommu",
Florian Vaussard3c927482014-02-28 14:42:36 -0600954 .of_match_table = of_match_ptr(omap_iommu_of_match),
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200955 },
956};
957
958static void iopte_cachep_ctor(void *iopte)
959{
960 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
961}
962
Laurent Pinchart286f6002014-03-08 00:44:38 +0100963static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700964{
965 memset(e, 0, sizeof(*e));
966
967 e->da = da;
968 e->pa = pa;
Suman Annad760e3e2014-03-17 20:31:32 -0500969 e->valid = MMU_CAM_V;
Laurent Pinchart286f6002014-03-08 00:44:38 +0100970 e->pgsz = pgsz;
971 e->endian = MMU_RAM_ENDIAN_LITTLE;
972 e->elsz = MMU_RAM_ELSZ_8;
973 e->mixed = 0;
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700974
975 return iopgsz_to_bytes(e->pgsz);
976}
977
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300978static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Suman Anna5835b6a2015-07-20 17:33:32 -0500979 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300980{
Joerg Roedel8cf851e2015-03-26 13:43:09 +0100981 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300982 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300983 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300984 struct iotlb_entry e;
985 int omap_pgsz;
Laurent Pinchart286f6002014-03-08 00:44:38 +0100986 u32 ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300987
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300988 omap_pgsz = bytes_to_iopgsz(bytes);
989 if (omap_pgsz < 0) {
990 dev_err(dev, "invalid size to map: %d\n", bytes);
991 return -EINVAL;
992 }
993
Joerg Roedel1d7f4492015-01-22 14:42:06 +0100994 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300995
Laurent Pinchart286f6002014-03-08 00:44:38 +0100996 iotlb_init_entry(&e, da, pa, omap_pgsz);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300997
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300998 ret = omap_iopgtable_store_entry(oiommu, &e);
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -0400999 if (ret)
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001000 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001001
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001002 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001003}
1004
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001005static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
Suman Anna5835b6a2015-07-20 17:33:32 -05001006 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001007{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001008 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001009 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001010 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001011
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001012 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001013
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001014 return iopgtable_clear_entry(oiommu, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001015}
1016
1017static int
1018omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1019{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001020 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001021 struct omap_iommu *oiommu;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001022 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001023 int ret = 0;
1024
Suman Annae3f595b2014-09-04 17:27:29 -05001025 if (!arch_data || !arch_data->name) {
1026 dev_err(dev, "device doesn't have an associated iommu\n");
1027 return -EINVAL;
1028 }
1029
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001030 spin_lock(&omap_domain->lock);
1031
1032 /* only a single device is supported per domain for now */
1033 if (omap_domain->iommu_dev) {
1034 dev_err(dev, "iommu domain is already attached\n");
1035 ret = -EBUSY;
1036 goto out;
1037 }
1038
1039 /* get a handle to and enable the omap iommu */
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001040 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001041 if (IS_ERR(oiommu)) {
1042 ret = PTR_ERR(oiommu);
1043 dev_err(dev, "can't get omap iommu: %d\n", ret);
1044 goto out;
1045 }
1046
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001047 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001048 omap_domain->dev = dev;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -04001049 oiommu->domain = domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001050
1051out:
1052 spin_unlock(&omap_domain->lock);
1053 return ret;
1054}
1055
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001056static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001057 struct device *dev)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001058{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001059 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001060 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001061
1062 /* only a single device is supported per domain for now */
1063 if (omap_domain->iommu_dev != oiommu) {
1064 dev_err(dev, "invalid iommu device\n");
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001065 return;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001066 }
1067
1068 iopgtable_clear_entry_all(oiommu);
1069
1070 omap_iommu_detach(oiommu);
1071
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001072 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001073 omap_domain->dev = NULL;
Suman Annaf24d9ad2014-10-22 17:22:33 -05001074 oiommu->domain = NULL;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001075}
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001076
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001077static void omap_iommu_detach_dev(struct iommu_domain *domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001078 struct device *dev)
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001079{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001080 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001081
1082 spin_lock(&omap_domain->lock);
1083 _omap_iommu_detach_dev(omap_domain, dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001084 spin_unlock(&omap_domain->lock);
1085}
1086
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001087static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001088{
1089 struct omap_iommu_domain *omap_domain;
1090
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001091 if (type != IOMMU_DOMAIN_UNMANAGED)
1092 return NULL;
1093
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001094 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
Suman Anna99ee98d2015-07-20 17:33:29 -05001095 if (!omap_domain)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001096 goto out;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001097
1098 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
Suman Anna99ee98d2015-07-20 17:33:29 -05001099 if (!omap_domain->pgtable)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001100 goto fail_nomem;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001101
1102 /*
1103 * should never fail, but please keep this around to ensure
1104 * we keep the hardware happy
1105 */
1106 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1107
1108 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1109 spin_lock_init(&omap_domain->lock);
1110
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001111 omap_domain->domain.geometry.aperture_start = 0;
1112 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1113 omap_domain->domain.geometry.force_aperture = true;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001114
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001115 return &omap_domain->domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001116
1117fail_nomem:
1118 kfree(omap_domain);
1119out:
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001120 return NULL;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001121}
1122
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001123static void omap_iommu_domain_free(struct iommu_domain *domain)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001124{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001125 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001126
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001127 /*
1128 * An iommu device is still attached
1129 * (currently, only one device can be attached) ?
1130 */
1131 if (omap_domain->iommu_dev)
1132 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1133
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001134 kfree(omap_domain->pgtable);
1135 kfree(omap_domain);
1136}
1137
1138static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001139 dma_addr_t da)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001140{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001141 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001142 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001143 struct device *dev = oiommu->dev;
1144 u32 *pgd, *pte;
1145 phys_addr_t ret = 0;
1146
1147 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1148
1149 if (pte) {
1150 if (iopte_is_small(*pte))
1151 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1152 else if (iopte_is_large(*pte))
1153 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1154 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001155 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
Suman Anna5835b6a2015-07-20 17:33:32 -05001156 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001157 } else {
1158 if (iopgd_is_section(*pgd))
1159 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1160 else if (iopgd_is_super(*pgd))
1161 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1162 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001163 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
Suman Anna5835b6a2015-07-20 17:33:32 -05001164 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001165 }
1166
1167 return ret;
1168}
1169
Laurent Pinchart07a02032014-02-28 14:42:38 -06001170static int omap_iommu_add_device(struct device *dev)
1171{
1172 struct omap_iommu_arch_data *arch_data;
1173 struct device_node *np;
Suman Anna7d682772014-09-04 17:27:30 -05001174 struct platform_device *pdev;
Laurent Pinchart07a02032014-02-28 14:42:38 -06001175
1176 /*
1177 * Allocate the archdata iommu structure for DT-based devices.
1178 *
1179 * TODO: Simplify this when removing non-DT support completely from the
1180 * IOMMU users.
1181 */
1182 if (!dev->of_node)
1183 return 0;
1184
1185 np = of_parse_phandle(dev->of_node, "iommus", 0);
1186 if (!np)
1187 return 0;
1188
Suman Anna7d682772014-09-04 17:27:30 -05001189 pdev = of_find_device_by_node(np);
1190 if (WARN_ON(!pdev)) {
1191 of_node_put(np);
1192 return -EINVAL;
1193 }
1194
Laurent Pinchart07a02032014-02-28 14:42:38 -06001195 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL);
1196 if (!arch_data) {
1197 of_node_put(np);
1198 return -ENOMEM;
1199 }
1200
Suman Anna7d682772014-09-04 17:27:30 -05001201 arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL);
Laurent Pinchart07a02032014-02-28 14:42:38 -06001202 dev->archdata.iommu = arch_data;
1203
1204 of_node_put(np);
1205
1206 return 0;
1207}
1208
1209static void omap_iommu_remove_device(struct device *dev)
1210{
1211 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1212
1213 if (!dev->of_node || !arch_data)
1214 return;
1215
1216 kfree(arch_data->name);
1217 kfree(arch_data);
1218}
1219
Thierry Redingb22f6432014-06-27 09:03:12 +02001220static const struct iommu_ops omap_iommu_ops = {
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001221 .domain_alloc = omap_iommu_domain_alloc,
1222 .domain_free = omap_iommu_domain_free,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001223 .attach_dev = omap_iommu_attach_dev,
1224 .detach_dev = omap_iommu_detach_dev,
1225 .map = omap_iommu_map,
1226 .unmap = omap_iommu_unmap,
Olav Haugan315786e2014-10-25 09:55:16 -07001227 .map_sg = default_iommu_map_sg,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001228 .iova_to_phys = omap_iommu_iova_to_phys,
Laurent Pinchart07a02032014-02-28 14:42:38 -06001229 .add_device = omap_iommu_add_device,
1230 .remove_device = omap_iommu_remove_device,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001231 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001232};
1233
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001234static int __init omap_iommu_init(void)
1235{
1236 struct kmem_cache *p;
1237 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1238 size_t align = 1 << 10; /* L2 pagetable alignement */
Thierry Redingf938aab2015-02-06 11:44:06 +01001239 struct device_node *np;
1240
1241 np = of_find_matching_node(NULL, omap_iommu_of_match);
1242 if (!np)
1243 return 0;
1244
1245 of_node_put(np);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001246
1247 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1248 iopte_cachep_ctor);
1249 if (!p)
1250 return -ENOMEM;
1251 iopte_cachep = p;
1252
Joerg Roedela65bc642011-09-06 17:56:07 +02001253 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001254
Suman Anna61c75352014-10-22 17:22:30 -05001255 omap_iommu_debugfs_init();
1256
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001257 return platform_driver_register(&omap_iommu_driver);
1258}
Ohad Ben-Cohen435792d2012-02-26 12:14:14 +02001259subsys_initcall(omap_iommu_init);
Suman Anna0cdbf722015-07-20 17:33:24 -05001260/* must be ready before omap3isp is probed */