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Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001/*
2 * omap iommu: tlb and pagetable primitives
3 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08004 * Copyright (C) 2008-2010 Nokia Corporation
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02005 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090016#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020017#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/clk.h>
20#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030021#include <linux/iommu.h>
Tony Lindgrenc8d35c82012-11-02 12:24:03 -070022#include <linux/omap-iommu.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030023#include <linux/mutex.h>
24#include <linux/spinlock.h>
Tony Lindgrened1c7de2012-11-02 12:24:06 -070025#include <linux/io.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020026
27#include <asm/cacheflush.h>
28
Tony Lindgren2ab7c842012-11-02 12:24:14 -070029#include <linux/platform_data/iommu-omap.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020030
Ido Yariv2f7702a2012-11-02 12:24:00 -070031#include "omap-iopgtable.h"
Tony Lindgrened1c7de2012-11-02 12:24:06 -070032#include "omap-iommu.h"
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020033
Hiroshi DOYU37c28362010-04-27 05:37:12 +000034#define for_each_iotlb_cr(obj, n, __i, cr) \
35 for (__i = 0; \
36 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
37 __i++)
38
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020039/* bitmap of the page sizes currently supported */
40#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
41
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030042/**
43 * struct omap_iommu_domain - omap iommu domain
44 * @pgtable: the page table
45 * @iommu_dev: an omap iommu device attached to this domain. only a single
46 * iommu device can be attached for now.
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050047 * @dev: Device using this domain.
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030048 * @lock: domain lock, should be taken when attaching/detaching
49 */
50struct omap_iommu_domain {
51 u32 *pgtable;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030052 struct omap_iommu *iommu_dev;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050053 struct device *dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030054 spinlock_t lock;
55};
56
Ido Yariv7bd9e252012-11-02 12:24:09 -070057#define MMU_LOCK_BASE_SHIFT 10
58#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
59#define MMU_LOCK_BASE(x) \
60 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
61
62#define MMU_LOCK_VICT_SHIFT 4
63#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
64#define MMU_LOCK_VICT(x) \
65 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
66
67struct iotlb_lock {
68 short base;
69 short vict;
70};
71
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020072/* accommodate the difference between omap1 and omap2/3 */
73static const struct iommu_functions *arch_iommu;
74
75static struct platform_driver omap_iommu_driver;
76static struct kmem_cache *iopte_cachep;
77
78/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030079 * omap_install_iommu_arch - Install archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020080 * @ops: a pointer to architecture specific iommu functions
81 *
82 * There are several kind of iommu algorithm(tlb, pagetable) among
83 * omap series. This interface installs such an iommu algorighm.
84 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030085int omap_install_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020086{
87 if (arch_iommu)
88 return -EBUSY;
89
90 arch_iommu = ops;
91 return 0;
92}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030093EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020094
95/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030096 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020097 * @ops: a pointer to architecture specific iommu functions
98 *
99 * This interface uninstalls the iommu algorighm installed previously.
100 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300101void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200102{
103 if (arch_iommu != ops)
104 pr_err("%s: not your arch\n", __func__);
105
106 arch_iommu = NULL;
107}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300108EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200109
110/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300111 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200112 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200113 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200114void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200115{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200116 struct omap_iommu *obj = dev_to_omap_iommu(dev);
117
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200118 arch_iommu->save_ctx(obj);
119}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300120EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200121
122/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300123 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200124 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200125 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200126void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200127{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200128 struct omap_iommu *obj = dev_to_omap_iommu(dev);
129
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200130 arch_iommu->restore_ctx(obj);
131}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300132EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200133
134/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300135 * omap_iommu_arch_version - Return running iommu arch version
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200136 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300137u32 omap_iommu_arch_version(void)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200138{
139 return arch_iommu->version;
140}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300141EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200142
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300143static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200144{
145 int err;
146
147 if (!obj)
148 return -EINVAL;
149
Martin Hostettleref4815a2011-02-24 12:51:31 -0800150 if (!arch_iommu)
151 return -ENODEV;
152
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200153 clk_enable(obj->clk);
154
155 err = arch_iommu->enable(obj);
156
157 clk_disable(obj->clk);
158 return err;
159}
160
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300161static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200162{
163 if (!obj)
164 return;
165
166 clk_enable(obj->clk);
167
168 arch_iommu->disable(obj);
169
170 clk_disable(obj->clk);
171}
172
173/*
174 * TLB operations
175 */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300176void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200177{
178 BUG_ON(!cr || !e);
179
180 arch_iommu->cr_to_e(cr, e);
181}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300182EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200183
184static inline int iotlb_cr_valid(struct cr_regs *cr)
185{
186 if (!cr)
187 return -EINVAL;
188
189 return arch_iommu->cr_valid(cr);
190}
191
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300192static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200193 struct iotlb_entry *e)
194{
195 if (!e)
196 return NULL;
197
198 return arch_iommu->alloc_cr(obj, e);
199}
200
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300201static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200202{
203 return arch_iommu->cr_to_virt(cr);
204}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200205
206static u32 get_iopte_attr(struct iotlb_entry *e)
207{
208 return arch_iommu->get_pte_attr(e);
209}
210
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300211static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200212{
213 return arch_iommu->fault_isr(obj, da);
214}
215
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300216static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200217{
218 u32 val;
219
220 val = iommu_read_reg(obj, MMU_LOCK);
221
222 l->base = MMU_LOCK_BASE(val);
223 l->vict = MMU_LOCK_VICT(val);
224
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200225}
226
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300227static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200228{
229 u32 val;
230
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200231 val = (l->base << MMU_LOCK_BASE_SHIFT);
232 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
233
234 iommu_write_reg(obj, val, MMU_LOCK);
235}
236
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300237static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200238{
239 arch_iommu->tlb_read_cr(obj, cr);
240}
241
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300242static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200243{
244 arch_iommu->tlb_load_cr(obj, cr);
245
246 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
247 iommu_write_reg(obj, 1, MMU_LD_TLB);
248}
249
250/**
251 * iotlb_dump_cr - Dump an iommu tlb entry into buf
252 * @obj: target iommu
253 * @cr: contents of cam and ram register
254 * @buf: output buffer
255 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300256static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200257 char *buf)
258{
259 BUG_ON(!cr || !buf);
260
261 return arch_iommu->dump_cr(obj, cr, buf);
262}
263
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000264/* only used in iotlb iteration for-loop */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300265static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000266{
267 struct cr_regs cr;
268 struct iotlb_lock l;
269
270 iotlb_lock_get(obj, &l);
271 l.vict = n;
272 iotlb_lock_set(obj, &l);
273 iotlb_read_cr(obj, &cr);
274
275 return cr;
276}
277
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200278/**
279 * load_iotlb_entry - Set an iommu tlb entry
280 * @obj: target iommu
281 * @e: an iommu tlb entry info
282 **/
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300283#ifdef PREFETCH_IOTLB
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300284static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200285{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200286 int err = 0;
287 struct iotlb_lock l;
288 struct cr_regs *cr;
289
290 if (!obj || !obj->nr_tlb_entries || !e)
291 return -EINVAL;
292
293 clk_enable(obj->clk);
294
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000295 iotlb_lock_get(obj, &l);
296 if (l.base == obj->nr_tlb_entries) {
297 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200298 err = -EBUSY;
299 goto out;
300 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000301 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000302 int i;
303 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000304
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000305 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000306 if (!iotlb_cr_valid(&tmp))
307 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000308
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000309 if (i == obj->nr_tlb_entries) {
310 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
311 err = -EBUSY;
312 goto out;
313 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000314
315 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000316 } else {
317 l.vict = l.base;
318 iotlb_lock_set(obj, &l);
319 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200320
321 cr = iotlb_alloc_cr(obj, e);
322 if (IS_ERR(cr)) {
323 clk_disable(obj->clk);
324 return PTR_ERR(cr);
325 }
326
327 iotlb_load_cr(obj, cr);
328 kfree(cr);
329
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000330 if (e->prsvd)
331 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200332 /* increment victim for next tlb load */
333 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000334 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200335 iotlb_lock_set(obj, &l);
336out:
337 clk_disable(obj->clk);
338 return err;
339}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200340
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300341#else /* !PREFETCH_IOTLB */
342
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300343static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300344{
345 return 0;
346}
347
348#endif /* !PREFETCH_IOTLB */
349
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300350static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300351{
352 return load_iotlb_entry(obj, e);
353}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200354
355/**
356 * flush_iotlb_page - Clear an iommu tlb entry
357 * @obj: target iommu
358 * @da: iommu device virtual address
359 *
360 * Clear an iommu tlb entry which includes 'da' address.
361 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300362static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200363{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200364 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000365 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200366
367 clk_enable(obj->clk);
368
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000369 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200370 u32 start;
371 size_t bytes;
372
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200373 if (!iotlb_cr_valid(&cr))
374 continue;
375
376 start = iotlb_cr_to_virt(&cr);
377 bytes = iopgsz_to_bytes(cr.cam & 3);
378
379 if ((start <= da) && (da < start + bytes)) {
380 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
381 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000382 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200383 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
384 }
385 }
386 clk_disable(obj->clk);
387
388 if (i == obj->nr_tlb_entries)
389 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
390}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200391
392/**
393 * flush_iotlb_all - Clear all iommu tlb entries
394 * @obj: target iommu
395 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300396static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200397{
398 struct iotlb_lock l;
399
400 clk_enable(obj->clk);
401
402 l.base = 0;
403 l.vict = 0;
404 iotlb_lock_set(obj, &l);
405
406 iommu_write_reg(obj, 1, MMU_GFLUSH);
407
408 clk_disable(obj->clk);
409}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200410
Arnd Bergmanne4efd942011-10-02 14:34:05 -0400411#if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
Kanigeri, Hariddfa9752010-05-24 02:01:51 +0000412
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300413ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200414{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200415 if (!obj || !buf)
416 return -EINVAL;
417
418 clk_enable(obj->clk);
419
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700420 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200421
422 clk_disable(obj->clk);
423
424 return bytes;
425}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300426EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200427
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300428static int
429__dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200430{
431 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000432 struct iotlb_lock saved;
433 struct cr_regs tmp;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200434 struct cr_regs *p = crs;
435
436 clk_enable(obj->clk);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200437 iotlb_lock_get(obj, &saved);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200438
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000439 for_each_iotlb_cr(obj, num, i, tmp) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200440 if (!iotlb_cr_valid(&tmp))
441 continue;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200442 *p++ = tmp;
443 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000444
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200445 iotlb_lock_set(obj, &saved);
446 clk_disable(obj->clk);
447
448 return p - crs;
449}
450
451/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300452 * omap_dump_tlb_entries - dump cr arrays to given buffer
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200453 * @obj: target iommu
454 * @buf: output buffer
455 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300456size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200457{
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700458 int i, num;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200459 struct cr_regs *cr;
460 char *p = buf;
461
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700462 num = bytes / sizeof(*cr);
463 num = min(obj->nr_tlb_entries, num);
464
465 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200466 if (!cr)
467 return 0;
468
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700469 num = __dump_tlb_entries(obj, cr, num);
470 for (i = 0; i < num; i++)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200471 p += iotlb_dump_cr(obj, cr + i, p);
472 kfree(cr);
473
474 return p - buf;
475}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300476EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200477
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300478int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200479{
480 return driver_for_each_device(&omap_iommu_driver.driver,
481 NULL, data, fn);
482}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300483EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200484
485#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
486
487/*
488 * H/W pagetable operations
489 */
490static void flush_iopgd_range(u32 *first, u32 *last)
491{
492 /* FIXME: L2 cache should be taken care of if it exists */
493 do {
494 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
495 : : "r" (first));
496 first += L1_CACHE_BYTES / sizeof(*first);
497 } while (first <= last);
498}
499
500static void flush_iopte_range(u32 *first, u32 *last)
501{
502 /* FIXME: L2 cache should be taken care of if it exists */
503 do {
504 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
505 : : "r" (first));
506 first += L1_CACHE_BYTES / sizeof(*first);
507 } while (first <= last);
508}
509
510static void iopte_free(u32 *iopte)
511{
512 /* Note: freed iopte's must be clean ready for re-use */
513 kmem_cache_free(iopte_cachep, iopte);
514}
515
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300516static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200517{
518 u32 *iopte;
519
520 /* a table has already existed */
521 if (*iopgd)
522 goto pte_ready;
523
524 /*
525 * do the allocation outside the page table lock
526 */
527 spin_unlock(&obj->page_table_lock);
528 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
529 spin_lock(&obj->page_table_lock);
530
531 if (!*iopgd) {
532 if (!iopte)
533 return ERR_PTR(-ENOMEM);
534
535 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
536 flush_iopgd_range(iopgd, iopgd);
537
538 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
539 } else {
540 /* We raced, free the reduniovant table */
541 iopte_free(iopte);
542 }
543
544pte_ready:
545 iopte = iopte_offset(iopgd, da);
546
547 dev_vdbg(obj->dev,
548 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
549 __func__, da, iopgd, *iopgd, iopte, *iopte);
550
551 return iopte;
552}
553
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300554static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200555{
556 u32 *iopgd = iopgd_offset(obj, da);
557
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300558 if ((da | pa) & ~IOSECTION_MASK) {
559 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
560 __func__, da, pa, IOSECTION_SIZE);
561 return -EINVAL;
562 }
563
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200564 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
565 flush_iopgd_range(iopgd, iopgd);
566 return 0;
567}
568
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300569static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200570{
571 u32 *iopgd = iopgd_offset(obj, da);
572 int i;
573
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300574 if ((da | pa) & ~IOSUPER_MASK) {
575 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
576 __func__, da, pa, IOSUPER_SIZE);
577 return -EINVAL;
578 }
579
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200580 for (i = 0; i < 16; i++)
581 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
582 flush_iopgd_range(iopgd, iopgd + 15);
583 return 0;
584}
585
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300586static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200587{
588 u32 *iopgd = iopgd_offset(obj, da);
589 u32 *iopte = iopte_alloc(obj, iopgd, da);
590
591 if (IS_ERR(iopte))
592 return PTR_ERR(iopte);
593
594 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
595 flush_iopte_range(iopte, iopte);
596
597 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
598 __func__, da, pa, iopte, *iopte);
599
600 return 0;
601}
602
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300603static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200604{
605 u32 *iopgd = iopgd_offset(obj, da);
606 u32 *iopte = iopte_alloc(obj, iopgd, da);
607 int i;
608
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300609 if ((da | pa) & ~IOLARGE_MASK) {
610 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
611 __func__, da, pa, IOLARGE_SIZE);
612 return -EINVAL;
613 }
614
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200615 if (IS_ERR(iopte))
616 return PTR_ERR(iopte);
617
618 for (i = 0; i < 16; i++)
619 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
620 flush_iopte_range(iopte, iopte + 15);
621 return 0;
622}
623
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300624static int
625iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200626{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300627 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200628 u32 prot;
629 int err;
630
631 if (!obj || !e)
632 return -EINVAL;
633
634 switch (e->pgsz) {
635 case MMU_CAM_PGSZ_16M:
636 fn = iopgd_alloc_super;
637 break;
638 case MMU_CAM_PGSZ_1M:
639 fn = iopgd_alloc_section;
640 break;
641 case MMU_CAM_PGSZ_64K:
642 fn = iopte_alloc_large;
643 break;
644 case MMU_CAM_PGSZ_4K:
645 fn = iopte_alloc_page;
646 break;
647 default:
648 fn = NULL;
649 BUG();
650 break;
651 }
652
653 prot = get_iopte_attr(e);
654
655 spin_lock(&obj->page_table_lock);
656 err = fn(obj, e->da, e->pa, prot);
657 spin_unlock(&obj->page_table_lock);
658
659 return err;
660}
661
662/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300663 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200664 * @obj: target iommu
665 * @e: an iommu tlb entry info
666 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300667int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200668{
669 int err;
670
671 flush_iotlb_page(obj, e->da);
672 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200673 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300674 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200675 return err;
676}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300677EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200678
679/**
680 * iopgtable_lookup_entry - Lookup an iommu pte entry
681 * @obj: target iommu
682 * @da: iommu device virtual address
683 * @ppgd: iommu pgd entry pointer to be returned
684 * @ppte: iommu pte entry pointer to be returned
685 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300686static void
687iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200688{
689 u32 *iopgd, *iopte = NULL;
690
691 iopgd = iopgd_offset(obj, da);
692 if (!*iopgd)
693 goto out;
694
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300695 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200696 iopte = iopte_offset(iopgd, da);
697out:
698 *ppgd = iopgd;
699 *ppte = iopte;
700}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200701
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300702static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200703{
704 size_t bytes;
705 u32 *iopgd = iopgd_offset(obj, da);
706 int nent = 1;
707
708 if (!*iopgd)
709 return 0;
710
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300711 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200712 int i;
713 u32 *iopte = iopte_offset(iopgd, da);
714
715 bytes = IOPTE_SIZE;
716 if (*iopte & IOPTE_LARGE) {
717 nent *= 16;
718 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800719 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200720 }
721 bytes *= nent;
722 memset(iopte, 0, nent * sizeof(*iopte));
723 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
724
725 /*
726 * do table walk to check if this table is necessary or not
727 */
728 iopte = iopte_offset(iopgd, 0);
729 for (i = 0; i < PTRS_PER_IOPTE; i++)
730 if (iopte[i])
731 goto out;
732
733 iopte_free(iopte);
734 nent = 1; /* for the next L1 entry */
735 } else {
736 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700737 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200738 nent *= 16;
739 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800740 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200741 }
742 bytes *= nent;
743 }
744 memset(iopgd, 0, nent * sizeof(*iopgd));
745 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
746out:
747 return bytes;
748}
749
750/**
751 * iopgtable_clear_entry - Remove an iommu pte entry
752 * @obj: target iommu
753 * @da: iommu device virtual address
754 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300755static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200756{
757 size_t bytes;
758
759 spin_lock(&obj->page_table_lock);
760
761 bytes = iopgtable_clear_entry_core(obj, da);
762 flush_iotlb_page(obj, da);
763
764 spin_unlock(&obj->page_table_lock);
765
766 return bytes;
767}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200768
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300769static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200770{
771 int i;
772
773 spin_lock(&obj->page_table_lock);
774
775 for (i = 0; i < PTRS_PER_IOPGD; i++) {
776 u32 da;
777 u32 *iopgd;
778
779 da = i << IOPGD_SHIFT;
780 iopgd = iopgd_offset(obj, da);
781
782 if (!*iopgd)
783 continue;
784
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300785 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200786 iopte_free(iopte_offset(iopgd, 0));
787
788 *iopgd = 0;
789 flush_iopgd_range(iopgd, iopgd);
790 }
791
792 flush_iotlb_all(obj);
793
794 spin_unlock(&obj->page_table_lock);
795}
796
797/*
798 * Device IOMMU generic operations
799 */
800static irqreturn_t iommu_fault_handler(int irq, void *data)
801{
David Cohend594f1f2011-02-16 19:35:51 +0000802 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200803 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300804 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400805 struct iommu_domain *domain = obj->domain;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200806
807 if (!obj->refcount)
808 return IRQ_NONE;
809
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200810 clk_enable(obj->clk);
David Cohend594f1f2011-02-16 19:35:51 +0000811 errs = iommu_report_fault(obj, &da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200812 clk_disable(obj->clk);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200813 if (errs == 0)
814 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000815
816 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400817 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200818 return IRQ_HANDLED;
819
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000820 iommu_disable(obj);
821
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200822 iopgd = iopgd_offset(obj, da);
823
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300824 if (!iopgd_is_table(*iopgd)) {
David Cohend594f1f2011-02-16 19:35:51 +0000825 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
826 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200827 return IRQ_NONE;
828 }
829
830 iopte = iopte_offset(iopgd, da);
831
David Cohend594f1f2011-02-16 19:35:51 +0000832 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
833 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
834 iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200835
836 return IRQ_NONE;
837}
838
839static int device_match_by_alias(struct device *dev, void *data)
840{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300841 struct omap_iommu *obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200842 const char *name = data;
843
844 pr_debug("%s: %s %s\n", __func__, obj->name, name);
845
846 return strcmp(obj->name, name) == 0;
847}
848
849/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300850 * omap_iommu_attach() - attach iommu device to an iommu domain
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200851 * @name: name of target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300852 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200853 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200854static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200855{
856 int err = -ENOMEM;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200857 struct device *dev;
858 struct omap_iommu *obj;
859
860 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
861 (void *)name,
862 device_match_by_alias);
863 if (!dev)
864 return NULL;
865
866 obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200867
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300868 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200869
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300870 /* an iommu device can only be attached once */
871 if (++obj->refcount > 1) {
872 dev_err(dev, "%s: already attached!\n", obj->name);
873 err = -EBUSY;
874 goto err_enable;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200875 }
876
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300877 obj->iopgd = iopgd;
878 err = iommu_enable(obj);
879 if (err)
880 goto err_enable;
881 flush_iotlb_all(obj);
882
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200883 if (!try_module_get(obj->owner))
884 goto err_module;
885
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300886 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200887
888 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
889 return obj;
890
891err_module:
892 if (obj->refcount == 1)
893 iommu_disable(obj);
894err_enable:
895 obj->refcount--;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300896 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200897 return ERR_PTR(err);
898}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200899
900/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300901 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200902 * @obj: target iommu
903 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300904static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200905{
Roel Kluinacf9d462010-01-08 10:29:05 -0800906 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200907 return;
908
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300909 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200910
911 if (--obj->refcount == 0)
912 iommu_disable(obj);
913
914 module_put(obj->owner);
915
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300916 obj->iopgd = NULL;
917
918 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200919
920 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
921}
David Cohend594f1f2011-02-16 19:35:51 +0000922
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200923/*
924 * OMAP Device MMU(IOMMU) detection
925 */
926static int __devinit omap_iommu_probe(struct platform_device *pdev)
927{
928 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200929 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300930 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200931 struct resource *res;
932 struct iommu_platform_data *pdata = pdev->dev.platform_data;
933
934 if (pdev->num_resources != 2)
935 return -EINVAL;
936
937 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
938 if (!obj)
939 return -ENOMEM;
940
941 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
942 if (IS_ERR(obj->clk))
943 goto err_clk;
944
945 obj->nr_tlb_entries = pdata->nr_tlb_entries;
946 obj->name = pdata->name;
947 obj->dev = &pdev->dev;
948 obj->ctx = (void *)obj + sizeof(*obj);
Guzman Lugo, Fernandoc7f4ab22010-12-15 00:54:03 +0000949 obj->da_start = pdata->da_start;
950 obj->da_end = pdata->da_end;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200951
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300952 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200953 mutex_init(&obj->mmap_lock);
954 spin_lock_init(&obj->page_table_lock);
955 INIT_LIST_HEAD(&obj->mmap);
956
957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
958 if (!res) {
959 err = -ENODEV;
960 goto err_mem;
961 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200962
963 res = request_mem_region(res->start, resource_size(res),
964 dev_name(&pdev->dev));
965 if (!res) {
966 err = -EIO;
967 goto err_mem;
968 }
969
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000970 obj->regbase = ioremap(res->start, resource_size(res));
971 if (!obj->regbase) {
972 err = -ENOMEM;
973 goto err_ioremap;
974 }
975
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200976 irq = platform_get_irq(pdev, 0);
977 if (irq < 0) {
978 err = -ENODEV;
979 goto err_irq;
980 }
981 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
982 dev_name(&pdev->dev), obj);
983 if (err < 0)
984 goto err_irq;
985 platform_set_drvdata(pdev, obj);
986
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200987 dev_info(&pdev->dev, "%s registered\n", obj->name);
988 return 0;
989
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200990err_irq:
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200991 iounmap(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000992err_ioremap:
993 release_mem_region(res->start, resource_size(res));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200994err_mem:
995 clk_put(obj->clk);
996err_clk:
997 kfree(obj);
998 return err;
999}
1000
1001static int __devexit omap_iommu_remove(struct platform_device *pdev)
1002{
1003 int irq;
1004 struct resource *res;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001005 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001006
1007 platform_set_drvdata(pdev, NULL);
1008
1009 iopgtable_clear_entry_all(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001010
1011 irq = platform_get_irq(pdev, 0);
1012 free_irq(irq, obj);
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1014 release_mem_region(res->start, resource_size(res));
1015 iounmap(obj->regbase);
1016
1017 clk_put(obj->clk);
1018 dev_info(&pdev->dev, "%s removed\n", obj->name);
1019 kfree(obj);
1020 return 0;
1021}
1022
1023static struct platform_driver omap_iommu_driver = {
1024 .probe = omap_iommu_probe,
1025 .remove = __devexit_p(omap_iommu_remove),
1026 .driver = {
1027 .name = "omap-iommu",
1028 },
1029};
1030
1031static void iopte_cachep_ctor(void *iopte)
1032{
1033 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1034}
1035
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001036static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
1037 u32 flags)
1038{
1039 memset(e, 0, sizeof(*e));
1040
1041 e->da = da;
1042 e->pa = pa;
1043 e->valid = 1;
1044 /* FIXME: add OMAP1 support */
1045 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
1046 e->endian = flags & MMU_RAM_ENDIAN_MASK;
1047 e->elsz = flags & MMU_RAM_ELSZ_MASK;
1048 e->mixed = flags & MMU_RAM_MIXED_MASK;
1049
1050 return iopgsz_to_bytes(e->pgsz);
1051}
1052
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001053static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001054 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001055{
1056 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001057 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001058 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001059 struct iotlb_entry e;
1060 int omap_pgsz;
1061 u32 ret, flags;
1062
1063 /* we only support mapping a single iommu page for now */
1064 omap_pgsz = bytes_to_iopgsz(bytes);
1065 if (omap_pgsz < 0) {
1066 dev_err(dev, "invalid size to map: %d\n", bytes);
1067 return -EINVAL;
1068 }
1069
1070 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1071
1072 flags = omap_pgsz | prot;
1073
1074 iotlb_init_entry(&e, da, pa, flags);
1075
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001076 ret = omap_iopgtable_store_entry(oiommu, &e);
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001077 if (ret)
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001078 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001079
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001080 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001081}
1082
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001083static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1084 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001085{
1086 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001087 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001088 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001089
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001090 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001091
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001092 return iopgtable_clear_entry(oiommu, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001093}
1094
1095static int
1096omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1097{
1098 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001099 struct omap_iommu *oiommu;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001100 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001101 int ret = 0;
1102
1103 spin_lock(&omap_domain->lock);
1104
1105 /* only a single device is supported per domain for now */
1106 if (omap_domain->iommu_dev) {
1107 dev_err(dev, "iommu domain is already attached\n");
1108 ret = -EBUSY;
1109 goto out;
1110 }
1111
1112 /* get a handle to and enable the omap iommu */
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001113 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001114 if (IS_ERR(oiommu)) {
1115 ret = PTR_ERR(oiommu);
1116 dev_err(dev, "can't get omap iommu: %d\n", ret);
1117 goto out;
1118 }
1119
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001120 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001121 omap_domain->dev = dev;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -04001122 oiommu->domain = domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001123
1124out:
1125 spin_unlock(&omap_domain->lock);
1126 return ret;
1127}
1128
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001129static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1130 struct device *dev)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001131{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001132 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001133 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001134
1135 /* only a single device is supported per domain for now */
1136 if (omap_domain->iommu_dev != oiommu) {
1137 dev_err(dev, "invalid iommu device\n");
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001138 return;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001139 }
1140
1141 iopgtable_clear_entry_all(oiommu);
1142
1143 omap_iommu_detach(oiommu);
1144
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001145 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001146 omap_domain->dev = NULL;
1147}
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001148
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001149static void omap_iommu_detach_dev(struct iommu_domain *domain,
1150 struct device *dev)
1151{
1152 struct omap_iommu_domain *omap_domain = domain->priv;
1153
1154 spin_lock(&omap_domain->lock);
1155 _omap_iommu_detach_dev(omap_domain, dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001156 spin_unlock(&omap_domain->lock);
1157}
1158
1159static int omap_iommu_domain_init(struct iommu_domain *domain)
1160{
1161 struct omap_iommu_domain *omap_domain;
1162
1163 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1164 if (!omap_domain) {
1165 pr_err("kzalloc failed\n");
1166 goto out;
1167 }
1168
1169 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1170 if (!omap_domain->pgtable) {
1171 pr_err("kzalloc failed\n");
1172 goto fail_nomem;
1173 }
1174
1175 /*
1176 * should never fail, but please keep this around to ensure
1177 * we keep the hardware happy
1178 */
1179 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1180
1181 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1182 spin_lock_init(&omap_domain->lock);
1183
1184 domain->priv = omap_domain;
1185
Joerg Roedel2c6edb02012-01-26 19:40:55 +01001186 domain->geometry.aperture_start = 0;
1187 domain->geometry.aperture_end = (1ULL << 32) - 1;
1188 domain->geometry.force_aperture = true;
1189
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001190 return 0;
1191
1192fail_nomem:
1193 kfree(omap_domain);
1194out:
1195 return -ENOMEM;
1196}
1197
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001198static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1199{
1200 struct omap_iommu_domain *omap_domain = domain->priv;
1201
1202 domain->priv = NULL;
1203
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001204 /*
1205 * An iommu device is still attached
1206 * (currently, only one device can be attached) ?
1207 */
1208 if (omap_domain->iommu_dev)
1209 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1210
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001211 kfree(omap_domain->pgtable);
1212 kfree(omap_domain);
1213}
1214
1215static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1216 unsigned long da)
1217{
1218 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001219 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001220 struct device *dev = oiommu->dev;
1221 u32 *pgd, *pte;
1222 phys_addr_t ret = 0;
1223
1224 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1225
1226 if (pte) {
1227 if (iopte_is_small(*pte))
1228 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1229 else if (iopte_is_large(*pte))
1230 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1231 else
Ohad Ben-Cohen1a36ea82011-12-06 15:22:10 +02001232 dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001233 } else {
1234 if (iopgd_is_section(*pgd))
1235 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1236 else if (iopgd_is_super(*pgd))
1237 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1238 else
Ohad Ben-Cohen1a36ea82011-12-06 15:22:10 +02001239 dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001240 }
1241
1242 return ret;
1243}
1244
1245static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1246 unsigned long cap)
1247{
1248 return 0;
1249}
1250
1251static struct iommu_ops omap_iommu_ops = {
1252 .domain_init = omap_iommu_domain_init,
1253 .domain_destroy = omap_iommu_domain_destroy,
1254 .attach_dev = omap_iommu_attach_dev,
1255 .detach_dev = omap_iommu_detach_dev,
1256 .map = omap_iommu_map,
1257 .unmap = omap_iommu_unmap,
1258 .iova_to_phys = omap_iommu_iova_to_phys,
1259 .domain_has_cap = omap_iommu_domain_has_cap,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001260 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001261};
1262
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001263static int __init omap_iommu_init(void)
1264{
1265 struct kmem_cache *p;
1266 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1267 size_t align = 1 << 10; /* L2 pagetable alignement */
1268
1269 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1270 iopte_cachep_ctor);
1271 if (!p)
1272 return -ENOMEM;
1273 iopte_cachep = p;
1274
Joerg Roedela65bc642011-09-06 17:56:07 +02001275 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001276
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001277 return platform_driver_register(&omap_iommu_driver);
1278}
Ohad Ben-Cohen435792d2012-02-26 12:14:14 +02001279/* must be ready before omap3isp is probed */
1280subsys_initcall(omap_iommu_init);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001281
1282static void __exit omap_iommu_exit(void)
1283{
1284 kmem_cache_destroy(iopte_cachep);
1285
1286 platform_driver_unregister(&omap_iommu_driver);
1287}
1288module_exit(omap_iommu_exit);
1289
1290MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1291MODULE_ALIAS("platform:omap-iommu");
1292MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1293MODULE_LICENSE("GPL v2");