Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * omap iommu: tlb and pagetable primitives |
| 3 | * |
Hiroshi DOYU | c127c7d | 2010-02-15 10:03:32 -0800 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 5 | * |
| 6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, |
| 7 | * Paul Mundt and Toshihiro Kobayashi |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 16 | #include <linux/slab.h> |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/ioport.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/platform_device.h> |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 21 | #include <linux/iommu.h> |
| 22 | #include <linux/mutex.h> |
| 23 | #include <linux/spinlock.h> |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 24 | |
| 25 | #include <asm/cacheflush.h> |
| 26 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 27 | #include <plat/iommu.h> |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 28 | |
Ohad Ben-Cohen | fcf3a6e | 2011-08-15 23:21:41 +0300 | [diff] [blame] | 29 | #include <plat/iopgtable.h> |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 30 | |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 31 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
| 32 | for (__i = 0; \ |
| 33 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ |
| 34 | __i++) |
| 35 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 36 | /** |
| 37 | * struct omap_iommu_domain - omap iommu domain |
| 38 | * @pgtable: the page table |
| 39 | * @iommu_dev: an omap iommu device attached to this domain. only a single |
| 40 | * iommu device can be attached for now. |
| 41 | * @lock: domain lock, should be taken when attaching/detaching |
| 42 | */ |
| 43 | struct omap_iommu_domain { |
| 44 | u32 *pgtable; |
| 45 | struct iommu *iommu_dev; |
| 46 | spinlock_t lock; |
| 47 | }; |
| 48 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 49 | /* accommodate the difference between omap1 and omap2/3 */ |
| 50 | static const struct iommu_functions *arch_iommu; |
| 51 | |
| 52 | static struct platform_driver omap_iommu_driver; |
| 53 | static struct kmem_cache *iopte_cachep; |
| 54 | |
| 55 | /** |
| 56 | * install_iommu_arch - Install archtecure specific iommu functions |
| 57 | * @ops: a pointer to architecture specific iommu functions |
| 58 | * |
| 59 | * There are several kind of iommu algorithm(tlb, pagetable) among |
| 60 | * omap series. This interface installs such an iommu algorighm. |
| 61 | **/ |
| 62 | int install_iommu_arch(const struct iommu_functions *ops) |
| 63 | { |
| 64 | if (arch_iommu) |
| 65 | return -EBUSY; |
| 66 | |
| 67 | arch_iommu = ops; |
| 68 | return 0; |
| 69 | } |
| 70 | EXPORT_SYMBOL_GPL(install_iommu_arch); |
| 71 | |
| 72 | /** |
| 73 | * uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
| 74 | * @ops: a pointer to architecture specific iommu functions |
| 75 | * |
| 76 | * This interface uninstalls the iommu algorighm installed previously. |
| 77 | **/ |
| 78 | void uninstall_iommu_arch(const struct iommu_functions *ops) |
| 79 | { |
| 80 | if (arch_iommu != ops) |
| 81 | pr_err("%s: not your arch\n", __func__); |
| 82 | |
| 83 | arch_iommu = NULL; |
| 84 | } |
| 85 | EXPORT_SYMBOL_GPL(uninstall_iommu_arch); |
| 86 | |
| 87 | /** |
| 88 | * iommu_save_ctx - Save registers for pm off-mode support |
| 89 | * @obj: target iommu |
| 90 | **/ |
| 91 | void iommu_save_ctx(struct iommu *obj) |
| 92 | { |
| 93 | arch_iommu->save_ctx(obj); |
| 94 | } |
| 95 | EXPORT_SYMBOL_GPL(iommu_save_ctx); |
| 96 | |
| 97 | /** |
| 98 | * iommu_restore_ctx - Restore registers for pm off-mode support |
| 99 | * @obj: target iommu |
| 100 | **/ |
| 101 | void iommu_restore_ctx(struct iommu *obj) |
| 102 | { |
| 103 | arch_iommu->restore_ctx(obj); |
| 104 | } |
| 105 | EXPORT_SYMBOL_GPL(iommu_restore_ctx); |
| 106 | |
| 107 | /** |
| 108 | * iommu_arch_version - Return running iommu arch version |
| 109 | **/ |
| 110 | u32 iommu_arch_version(void) |
| 111 | { |
| 112 | return arch_iommu->version; |
| 113 | } |
| 114 | EXPORT_SYMBOL_GPL(iommu_arch_version); |
| 115 | |
| 116 | static int iommu_enable(struct iommu *obj) |
| 117 | { |
| 118 | int err; |
| 119 | |
| 120 | if (!obj) |
| 121 | return -EINVAL; |
| 122 | |
Martin Hostettler | ef4815a | 2011-02-24 12:51:31 -0800 | [diff] [blame] | 123 | if (!arch_iommu) |
| 124 | return -ENODEV; |
| 125 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 126 | clk_enable(obj->clk); |
| 127 | |
| 128 | err = arch_iommu->enable(obj); |
| 129 | |
| 130 | clk_disable(obj->clk); |
| 131 | return err; |
| 132 | } |
| 133 | |
| 134 | static void iommu_disable(struct iommu *obj) |
| 135 | { |
| 136 | if (!obj) |
| 137 | return; |
| 138 | |
| 139 | clk_enable(obj->clk); |
| 140 | |
| 141 | arch_iommu->disable(obj); |
| 142 | |
| 143 | clk_disable(obj->clk); |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * TLB operations |
| 148 | */ |
| 149 | void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
| 150 | { |
| 151 | BUG_ON(!cr || !e); |
| 152 | |
| 153 | arch_iommu->cr_to_e(cr, e); |
| 154 | } |
| 155 | EXPORT_SYMBOL_GPL(iotlb_cr_to_e); |
| 156 | |
| 157 | static inline int iotlb_cr_valid(struct cr_regs *cr) |
| 158 | { |
| 159 | if (!cr) |
| 160 | return -EINVAL; |
| 161 | |
| 162 | return arch_iommu->cr_valid(cr); |
| 163 | } |
| 164 | |
| 165 | static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, |
| 166 | struct iotlb_entry *e) |
| 167 | { |
| 168 | if (!e) |
| 169 | return NULL; |
| 170 | |
| 171 | return arch_iommu->alloc_cr(obj, e); |
| 172 | } |
| 173 | |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 174 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 175 | { |
| 176 | return arch_iommu->cr_to_virt(cr); |
| 177 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 178 | |
| 179 | static u32 get_iopte_attr(struct iotlb_entry *e) |
| 180 | { |
| 181 | return arch_iommu->get_pte_attr(e); |
| 182 | } |
| 183 | |
| 184 | static u32 iommu_report_fault(struct iommu *obj, u32 *da) |
| 185 | { |
| 186 | return arch_iommu->fault_isr(obj, da); |
| 187 | } |
| 188 | |
| 189 | static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) |
| 190 | { |
| 191 | u32 val; |
| 192 | |
| 193 | val = iommu_read_reg(obj, MMU_LOCK); |
| 194 | |
| 195 | l->base = MMU_LOCK_BASE(val); |
| 196 | l->vict = MMU_LOCK_VICT(val); |
| 197 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) |
| 201 | { |
| 202 | u32 val; |
| 203 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 204 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
| 205 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); |
| 206 | |
| 207 | iommu_write_reg(obj, val, MMU_LOCK); |
| 208 | } |
| 209 | |
| 210 | static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) |
| 211 | { |
| 212 | arch_iommu->tlb_read_cr(obj, cr); |
| 213 | } |
| 214 | |
| 215 | static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) |
| 216 | { |
| 217 | arch_iommu->tlb_load_cr(obj, cr); |
| 218 | |
| 219 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
| 220 | iommu_write_reg(obj, 1, MMU_LD_TLB); |
| 221 | } |
| 222 | |
| 223 | /** |
| 224 | * iotlb_dump_cr - Dump an iommu tlb entry into buf |
| 225 | * @obj: target iommu |
| 226 | * @cr: contents of cam and ram register |
| 227 | * @buf: output buffer |
| 228 | **/ |
| 229 | static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, |
| 230 | char *buf) |
| 231 | { |
| 232 | BUG_ON(!cr || !buf); |
| 233 | |
| 234 | return arch_iommu->dump_cr(obj, cr, buf); |
| 235 | } |
| 236 | |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 237 | /* only used in iotlb iteration for-loop */ |
| 238 | static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n) |
| 239 | { |
| 240 | struct cr_regs cr; |
| 241 | struct iotlb_lock l; |
| 242 | |
| 243 | iotlb_lock_get(obj, &l); |
| 244 | l.vict = n; |
| 245 | iotlb_lock_set(obj, &l); |
| 246 | iotlb_read_cr(obj, &cr); |
| 247 | |
| 248 | return cr; |
| 249 | } |
| 250 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 251 | /** |
| 252 | * load_iotlb_entry - Set an iommu tlb entry |
| 253 | * @obj: target iommu |
| 254 | * @e: an iommu tlb entry info |
| 255 | **/ |
Ohad Ben-Cohen | 5da14a4 | 2011-08-16 15:19:10 +0300 | [diff] [blame^] | 256 | #ifdef PREFETCH_IOTLB |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 257 | static int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 258 | { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 259 | int err = 0; |
| 260 | struct iotlb_lock l; |
| 261 | struct cr_regs *cr; |
| 262 | |
| 263 | if (!obj || !obj->nr_tlb_entries || !e) |
| 264 | return -EINVAL; |
| 265 | |
| 266 | clk_enable(obj->clk); |
| 267 | |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 268 | iotlb_lock_get(obj, &l); |
| 269 | if (l.base == obj->nr_tlb_entries) { |
| 270 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 271 | err = -EBUSY; |
| 272 | goto out; |
| 273 | } |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 274 | if (!e->prsvd) { |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 275 | int i; |
| 276 | struct cr_regs tmp; |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 277 | |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 278 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 279 | if (!iotlb_cr_valid(&tmp)) |
| 280 | break; |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 281 | |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 282 | if (i == obj->nr_tlb_entries) { |
| 283 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); |
| 284 | err = -EBUSY; |
| 285 | goto out; |
| 286 | } |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 287 | |
| 288 | iotlb_lock_get(obj, &l); |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 289 | } else { |
| 290 | l.vict = l.base; |
| 291 | iotlb_lock_set(obj, &l); |
| 292 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 293 | |
| 294 | cr = iotlb_alloc_cr(obj, e); |
| 295 | if (IS_ERR(cr)) { |
| 296 | clk_disable(obj->clk); |
| 297 | return PTR_ERR(cr); |
| 298 | } |
| 299 | |
| 300 | iotlb_load_cr(obj, cr); |
| 301 | kfree(cr); |
| 302 | |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 303 | if (e->prsvd) |
| 304 | l.base++; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 305 | /* increment victim for next tlb load */ |
| 306 | if (++l.vict == obj->nr_tlb_entries) |
Kanigeri, Hari | be6d802 | 2010-04-22 23:26:11 +0000 | [diff] [blame] | 307 | l.vict = l.base; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 308 | iotlb_lock_set(obj, &l); |
| 309 | out: |
| 310 | clk_disable(obj->clk); |
| 311 | return err; |
| 312 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 313 | |
Ohad Ben-Cohen | 5da14a4 | 2011-08-16 15:19:10 +0300 | [diff] [blame^] | 314 | #else /* !PREFETCH_IOTLB */ |
| 315 | |
| 316 | static int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) |
| 317 | { |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | #endif /* !PREFETCH_IOTLB */ |
| 322 | |
| 323 | static int prefetch_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) |
| 324 | { |
| 325 | return load_iotlb_entry(obj, e); |
| 326 | } |
| 327 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 328 | /** |
| 329 | * flush_iotlb_page - Clear an iommu tlb entry |
| 330 | * @obj: target iommu |
| 331 | * @da: iommu device virtual address |
| 332 | * |
| 333 | * Clear an iommu tlb entry which includes 'da' address. |
| 334 | **/ |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 335 | static void flush_iotlb_page(struct iommu *obj, u32 da) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 336 | { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 337 | int i; |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 338 | struct cr_regs cr; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 339 | |
| 340 | clk_enable(obj->clk); |
| 341 | |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 342 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 343 | u32 start; |
| 344 | size_t bytes; |
| 345 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 346 | if (!iotlb_cr_valid(&cr)) |
| 347 | continue; |
| 348 | |
| 349 | start = iotlb_cr_to_virt(&cr); |
| 350 | bytes = iopgsz_to_bytes(cr.cam & 3); |
| 351 | |
| 352 | if ((start <= da) && (da < start + bytes)) { |
| 353 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", |
| 354 | __func__, start, da, bytes); |
Hari Kanigeri | 0fa035e | 2010-08-20 13:50:18 +0000 | [diff] [blame] | 355 | iotlb_load_cr(obj, &cr); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 356 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
| 357 | } |
| 358 | } |
| 359 | clk_disable(obj->clk); |
| 360 | |
| 361 | if (i == obj->nr_tlb_entries) |
| 362 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); |
| 363 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 364 | |
| 365 | /** |
| 366 | * flush_iotlb_range - Clear an iommu tlb entries |
| 367 | * @obj: target iommu |
| 368 | * @start: iommu device virtual address(start) |
| 369 | * @end: iommu device virtual address(end) |
| 370 | * |
| 371 | * Clear an iommu tlb entry which includes 'da' address. |
| 372 | **/ |
| 373 | void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) |
| 374 | { |
| 375 | u32 da = start; |
| 376 | |
| 377 | while (da < end) { |
| 378 | flush_iotlb_page(obj, da); |
| 379 | /* FIXME: Optimize for multiple page size */ |
| 380 | da += IOPTE_SIZE; |
| 381 | } |
| 382 | } |
| 383 | EXPORT_SYMBOL_GPL(flush_iotlb_range); |
| 384 | |
| 385 | /** |
| 386 | * flush_iotlb_all - Clear all iommu tlb entries |
| 387 | * @obj: target iommu |
| 388 | **/ |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 389 | static void flush_iotlb_all(struct iommu *obj) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 390 | { |
| 391 | struct iotlb_lock l; |
| 392 | |
| 393 | clk_enable(obj->clk); |
| 394 | |
| 395 | l.base = 0; |
| 396 | l.vict = 0; |
| 397 | iotlb_lock_set(obj, &l); |
| 398 | |
| 399 | iommu_write_reg(obj, 1, MMU_GFLUSH); |
| 400 | |
| 401 | clk_disable(obj->clk); |
| 402 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 403 | |
Kanigeri, Hari | ddfa975 | 2010-05-24 02:01:51 +0000 | [diff] [blame] | 404 | /** |
| 405 | * iommu_set_twl - enable/disable table walking logic |
| 406 | * @obj: target iommu |
| 407 | * @on: enable/disable |
| 408 | * |
| 409 | * Function used to enable/disable TWL. If one wants to work |
| 410 | * exclusively with locked TLB entries and receive notifications |
| 411 | * for TLB miss then call this function to disable TWL. |
| 412 | */ |
| 413 | void iommu_set_twl(struct iommu *obj, bool on) |
| 414 | { |
| 415 | clk_enable(obj->clk); |
| 416 | arch_iommu->set_twl(obj, on); |
| 417 | clk_disable(obj->clk); |
| 418 | } |
| 419 | EXPORT_SYMBOL_GPL(iommu_set_twl); |
| 420 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 421 | #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
| 422 | |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 423 | ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 424 | { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 425 | if (!obj || !buf) |
| 426 | return -EINVAL; |
| 427 | |
| 428 | clk_enable(obj->clk); |
| 429 | |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 430 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 431 | |
| 432 | clk_disable(obj->clk); |
| 433 | |
| 434 | return bytes; |
| 435 | } |
| 436 | EXPORT_SYMBOL_GPL(iommu_dump_ctx); |
| 437 | |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 438 | static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 439 | { |
| 440 | int i; |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 441 | struct iotlb_lock saved; |
| 442 | struct cr_regs tmp; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 443 | struct cr_regs *p = crs; |
| 444 | |
| 445 | clk_enable(obj->clk); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 446 | iotlb_lock_get(obj, &saved); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 447 | |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 448 | for_each_iotlb_cr(obj, num, i, tmp) { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 449 | if (!iotlb_cr_valid(&tmp)) |
| 450 | continue; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 451 | *p++ = tmp; |
| 452 | } |
Hiroshi DOYU | 37c2836 | 2010-04-27 05:37:12 +0000 | [diff] [blame] | 453 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 454 | iotlb_lock_set(obj, &saved); |
| 455 | clk_disable(obj->clk); |
| 456 | |
| 457 | return p - crs; |
| 458 | } |
| 459 | |
| 460 | /** |
| 461 | * dump_tlb_entries - dump cr arrays to given buffer |
| 462 | * @obj: target iommu |
| 463 | * @buf: output buffer |
| 464 | **/ |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 465 | size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 466 | { |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 467 | int i, num; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 468 | struct cr_regs *cr; |
| 469 | char *p = buf; |
| 470 | |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 471 | num = bytes / sizeof(*cr); |
| 472 | num = min(obj->nr_tlb_entries, num); |
| 473 | |
| 474 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 475 | if (!cr) |
| 476 | return 0; |
| 477 | |
Hiroshi DOYU | 14e0e67 | 2009-08-28 10:54:41 -0700 | [diff] [blame] | 478 | num = __dump_tlb_entries(obj, cr, num); |
| 479 | for (i = 0; i < num; i++) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 480 | p += iotlb_dump_cr(obj, cr + i, p); |
| 481 | kfree(cr); |
| 482 | |
| 483 | return p - buf; |
| 484 | } |
| 485 | EXPORT_SYMBOL_GPL(dump_tlb_entries); |
| 486 | |
| 487 | int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
| 488 | { |
| 489 | return driver_for_each_device(&omap_iommu_driver.driver, |
| 490 | NULL, data, fn); |
| 491 | } |
| 492 | EXPORT_SYMBOL_GPL(foreach_iommu_device); |
| 493 | |
| 494 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ |
| 495 | |
| 496 | /* |
| 497 | * H/W pagetable operations |
| 498 | */ |
| 499 | static void flush_iopgd_range(u32 *first, u32 *last) |
| 500 | { |
| 501 | /* FIXME: L2 cache should be taken care of if it exists */ |
| 502 | do { |
| 503 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" |
| 504 | : : "r" (first)); |
| 505 | first += L1_CACHE_BYTES / sizeof(*first); |
| 506 | } while (first <= last); |
| 507 | } |
| 508 | |
| 509 | static void flush_iopte_range(u32 *first, u32 *last) |
| 510 | { |
| 511 | /* FIXME: L2 cache should be taken care of if it exists */ |
| 512 | do { |
| 513 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" |
| 514 | : : "r" (first)); |
| 515 | first += L1_CACHE_BYTES / sizeof(*first); |
| 516 | } while (first <= last); |
| 517 | } |
| 518 | |
| 519 | static void iopte_free(u32 *iopte) |
| 520 | { |
| 521 | /* Note: freed iopte's must be clean ready for re-use */ |
| 522 | kmem_cache_free(iopte_cachep, iopte); |
| 523 | } |
| 524 | |
| 525 | static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) |
| 526 | { |
| 527 | u32 *iopte; |
| 528 | |
| 529 | /* a table has already existed */ |
| 530 | if (*iopgd) |
| 531 | goto pte_ready; |
| 532 | |
| 533 | /* |
| 534 | * do the allocation outside the page table lock |
| 535 | */ |
| 536 | spin_unlock(&obj->page_table_lock); |
| 537 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); |
| 538 | spin_lock(&obj->page_table_lock); |
| 539 | |
| 540 | if (!*iopgd) { |
| 541 | if (!iopte) |
| 542 | return ERR_PTR(-ENOMEM); |
| 543 | |
| 544 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; |
| 545 | flush_iopgd_range(iopgd, iopgd); |
| 546 | |
| 547 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); |
| 548 | } else { |
| 549 | /* We raced, free the reduniovant table */ |
| 550 | iopte_free(iopte); |
| 551 | } |
| 552 | |
| 553 | pte_ready: |
| 554 | iopte = iopte_offset(iopgd, da); |
| 555 | |
| 556 | dev_vdbg(obj->dev, |
| 557 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", |
| 558 | __func__, da, iopgd, *iopgd, iopte, *iopte); |
| 559 | |
| 560 | return iopte; |
| 561 | } |
| 562 | |
| 563 | static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) |
| 564 | { |
| 565 | u32 *iopgd = iopgd_offset(obj, da); |
| 566 | |
Hiroshi DOYU | 4abb761 | 2010-05-06 18:24:04 +0300 | [diff] [blame] | 567 | if ((da | pa) & ~IOSECTION_MASK) { |
| 568 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", |
| 569 | __func__, da, pa, IOSECTION_SIZE); |
| 570 | return -EINVAL; |
| 571 | } |
| 572 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 573 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
| 574 | flush_iopgd_range(iopgd, iopgd); |
| 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) |
| 579 | { |
| 580 | u32 *iopgd = iopgd_offset(obj, da); |
| 581 | int i; |
| 582 | |
Hiroshi DOYU | 4abb761 | 2010-05-06 18:24:04 +0300 | [diff] [blame] | 583 | if ((da | pa) & ~IOSUPER_MASK) { |
| 584 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", |
| 585 | __func__, da, pa, IOSUPER_SIZE); |
| 586 | return -EINVAL; |
| 587 | } |
| 588 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 589 | for (i = 0; i < 16; i++) |
| 590 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; |
| 591 | flush_iopgd_range(iopgd, iopgd + 15); |
| 592 | return 0; |
| 593 | } |
| 594 | |
| 595 | static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) |
| 596 | { |
| 597 | u32 *iopgd = iopgd_offset(obj, da); |
| 598 | u32 *iopte = iopte_alloc(obj, iopgd, da); |
| 599 | |
| 600 | if (IS_ERR(iopte)) |
| 601 | return PTR_ERR(iopte); |
| 602 | |
| 603 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; |
| 604 | flush_iopte_range(iopte, iopte); |
| 605 | |
| 606 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", |
| 607 | __func__, da, pa, iopte, *iopte); |
| 608 | |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) |
| 613 | { |
| 614 | u32 *iopgd = iopgd_offset(obj, da); |
| 615 | u32 *iopte = iopte_alloc(obj, iopgd, da); |
| 616 | int i; |
| 617 | |
Hiroshi DOYU | 4abb761 | 2010-05-06 18:24:04 +0300 | [diff] [blame] | 618 | if ((da | pa) & ~IOLARGE_MASK) { |
| 619 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", |
| 620 | __func__, da, pa, IOLARGE_SIZE); |
| 621 | return -EINVAL; |
| 622 | } |
| 623 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 624 | if (IS_ERR(iopte)) |
| 625 | return PTR_ERR(iopte); |
| 626 | |
| 627 | for (i = 0; i < 16; i++) |
| 628 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; |
| 629 | flush_iopte_range(iopte, iopte + 15); |
| 630 | return 0; |
| 631 | } |
| 632 | |
| 633 | static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) |
| 634 | { |
| 635 | int (*fn)(struct iommu *, u32, u32, u32); |
| 636 | u32 prot; |
| 637 | int err; |
| 638 | |
| 639 | if (!obj || !e) |
| 640 | return -EINVAL; |
| 641 | |
| 642 | switch (e->pgsz) { |
| 643 | case MMU_CAM_PGSZ_16M: |
| 644 | fn = iopgd_alloc_super; |
| 645 | break; |
| 646 | case MMU_CAM_PGSZ_1M: |
| 647 | fn = iopgd_alloc_section; |
| 648 | break; |
| 649 | case MMU_CAM_PGSZ_64K: |
| 650 | fn = iopte_alloc_large; |
| 651 | break; |
| 652 | case MMU_CAM_PGSZ_4K: |
| 653 | fn = iopte_alloc_page; |
| 654 | break; |
| 655 | default: |
| 656 | fn = NULL; |
| 657 | BUG(); |
| 658 | break; |
| 659 | } |
| 660 | |
| 661 | prot = get_iopte_attr(e); |
| 662 | |
| 663 | spin_lock(&obj->page_table_lock); |
| 664 | err = fn(obj, e->da, e->pa, prot); |
| 665 | spin_unlock(&obj->page_table_lock); |
| 666 | |
| 667 | return err; |
| 668 | } |
| 669 | |
| 670 | /** |
| 671 | * iopgtable_store_entry - Make an iommu pte entry |
| 672 | * @obj: target iommu |
| 673 | * @e: an iommu tlb entry info |
| 674 | **/ |
| 675 | int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) |
| 676 | { |
| 677 | int err; |
| 678 | |
| 679 | flush_iotlb_page(obj, e->da); |
| 680 | err = iopgtable_store_entry_core(obj, e); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 681 | if (!err) |
Ohad Ben-Cohen | 5da14a4 | 2011-08-16 15:19:10 +0300 | [diff] [blame^] | 682 | prefetch_iotlb_entry(obj, e); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 683 | return err; |
| 684 | } |
| 685 | EXPORT_SYMBOL_GPL(iopgtable_store_entry); |
| 686 | |
| 687 | /** |
| 688 | * iopgtable_lookup_entry - Lookup an iommu pte entry |
| 689 | * @obj: target iommu |
| 690 | * @da: iommu device virtual address |
| 691 | * @ppgd: iommu pgd entry pointer to be returned |
| 692 | * @ppte: iommu pte entry pointer to be returned |
| 693 | **/ |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 694 | static void |
| 695 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 696 | { |
| 697 | u32 *iopgd, *iopte = NULL; |
| 698 | |
| 699 | iopgd = iopgd_offset(obj, da); |
| 700 | if (!*iopgd) |
| 701 | goto out; |
| 702 | |
Hiroshi DOYU | a1a5445 | 2010-05-13 09:45:35 +0300 | [diff] [blame] | 703 | if (iopgd_is_table(*iopgd)) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 704 | iopte = iopte_offset(iopgd, da); |
| 705 | out: |
| 706 | *ppgd = iopgd; |
| 707 | *ppte = iopte; |
| 708 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 709 | |
| 710 | static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) |
| 711 | { |
| 712 | size_t bytes; |
| 713 | u32 *iopgd = iopgd_offset(obj, da); |
| 714 | int nent = 1; |
| 715 | |
| 716 | if (!*iopgd) |
| 717 | return 0; |
| 718 | |
Hiroshi DOYU | a1a5445 | 2010-05-13 09:45:35 +0300 | [diff] [blame] | 719 | if (iopgd_is_table(*iopgd)) { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 720 | int i; |
| 721 | u32 *iopte = iopte_offset(iopgd, da); |
| 722 | |
| 723 | bytes = IOPTE_SIZE; |
| 724 | if (*iopte & IOPTE_LARGE) { |
| 725 | nent *= 16; |
| 726 | /* rewind to the 1st entry */ |
Hiroshi DOYU | c127c7d | 2010-02-15 10:03:32 -0800 | [diff] [blame] | 727 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 728 | } |
| 729 | bytes *= nent; |
| 730 | memset(iopte, 0, nent * sizeof(*iopte)); |
| 731 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); |
| 732 | |
| 733 | /* |
| 734 | * do table walk to check if this table is necessary or not |
| 735 | */ |
| 736 | iopte = iopte_offset(iopgd, 0); |
| 737 | for (i = 0; i < PTRS_PER_IOPTE; i++) |
| 738 | if (iopte[i]) |
| 739 | goto out; |
| 740 | |
| 741 | iopte_free(iopte); |
| 742 | nent = 1; /* for the next L1 entry */ |
| 743 | } else { |
| 744 | bytes = IOPGD_SIZE; |
Hiroshi DOYU | dcc730d | 2009-10-22 14:46:32 -0700 | [diff] [blame] | 745 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 746 | nent *= 16; |
| 747 | /* rewind to the 1st entry */ |
Hiroshi DOYU | 8d33ea5 | 2010-02-15 10:03:32 -0800 | [diff] [blame] | 748 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 749 | } |
| 750 | bytes *= nent; |
| 751 | } |
| 752 | memset(iopgd, 0, nent * sizeof(*iopgd)); |
| 753 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); |
| 754 | out: |
| 755 | return bytes; |
| 756 | } |
| 757 | |
| 758 | /** |
| 759 | * iopgtable_clear_entry - Remove an iommu pte entry |
| 760 | * @obj: target iommu |
| 761 | * @da: iommu device virtual address |
| 762 | **/ |
Ohad Ben-Cohen | e1f2381 | 2011-08-16 14:58:14 +0300 | [diff] [blame] | 763 | static size_t iopgtable_clear_entry(struct iommu *obj, u32 da) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 764 | { |
| 765 | size_t bytes; |
| 766 | |
| 767 | spin_lock(&obj->page_table_lock); |
| 768 | |
| 769 | bytes = iopgtable_clear_entry_core(obj, da); |
| 770 | flush_iotlb_page(obj, da); |
| 771 | |
| 772 | spin_unlock(&obj->page_table_lock); |
| 773 | |
| 774 | return bytes; |
| 775 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 776 | |
| 777 | static void iopgtable_clear_entry_all(struct iommu *obj) |
| 778 | { |
| 779 | int i; |
| 780 | |
| 781 | spin_lock(&obj->page_table_lock); |
| 782 | |
| 783 | for (i = 0; i < PTRS_PER_IOPGD; i++) { |
| 784 | u32 da; |
| 785 | u32 *iopgd; |
| 786 | |
| 787 | da = i << IOPGD_SHIFT; |
| 788 | iopgd = iopgd_offset(obj, da); |
| 789 | |
| 790 | if (!*iopgd) |
| 791 | continue; |
| 792 | |
Hiroshi DOYU | a1a5445 | 2010-05-13 09:45:35 +0300 | [diff] [blame] | 793 | if (iopgd_is_table(*iopgd)) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 794 | iopte_free(iopte_offset(iopgd, 0)); |
| 795 | |
| 796 | *iopgd = 0; |
| 797 | flush_iopgd_range(iopgd, iopgd); |
| 798 | } |
| 799 | |
| 800 | flush_iotlb_all(obj); |
| 801 | |
| 802 | spin_unlock(&obj->page_table_lock); |
| 803 | } |
| 804 | |
| 805 | /* |
| 806 | * Device IOMMU generic operations |
| 807 | */ |
| 808 | static irqreturn_t iommu_fault_handler(int irq, void *data) |
| 809 | { |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 810 | u32 da, errs; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 811 | u32 *iopgd, *iopte; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 812 | struct iommu *obj = data; |
| 813 | |
| 814 | if (!obj->refcount) |
| 815 | return IRQ_NONE; |
| 816 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 817 | clk_enable(obj->clk); |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 818 | errs = iommu_report_fault(obj, &da); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 819 | clk_disable(obj->clk); |
Laurent Pinchart | c56b2dd | 2011-05-10 16:56:46 +0200 | [diff] [blame] | 820 | if (errs == 0) |
| 821 | return IRQ_HANDLED; |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 822 | |
| 823 | /* Fault callback or TLB/PTE Dynamic loading */ |
| 824 | if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 825 | return IRQ_HANDLED; |
| 826 | |
Hiroshi DOYU | 37b2981 | 2010-05-24 02:01:52 +0000 | [diff] [blame] | 827 | iommu_disable(obj); |
| 828 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 829 | iopgd = iopgd_offset(obj, da); |
| 830 | |
Hiroshi DOYU | a1a5445 | 2010-05-13 09:45:35 +0300 | [diff] [blame] | 831 | if (!iopgd_is_table(*iopgd)) { |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 832 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
| 833 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 834 | return IRQ_NONE; |
| 835 | } |
| 836 | |
| 837 | iopte = iopte_offset(iopgd, da); |
| 838 | |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 839 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
| 840 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, |
| 841 | iopte, *iopte); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 842 | |
| 843 | return IRQ_NONE; |
| 844 | } |
| 845 | |
| 846 | static int device_match_by_alias(struct device *dev, void *data) |
| 847 | { |
| 848 | struct iommu *obj = to_iommu(dev); |
| 849 | const char *name = data; |
| 850 | |
| 851 | pr_debug("%s: %s %s\n", __func__, obj->name, name); |
| 852 | |
| 853 | return strcmp(obj->name, name) == 0; |
| 854 | } |
| 855 | |
| 856 | /** |
Guzman Lugo, Fernando | c7f4ab2 | 2010-12-15 00:54:03 +0000 | [diff] [blame] | 857 | * iommu_set_da_range - Set a valid device address range |
| 858 | * @obj: target iommu |
| 859 | * @start Start of valid range |
| 860 | * @end End of valid range |
| 861 | **/ |
| 862 | int iommu_set_da_range(struct iommu *obj, u32 start, u32 end) |
| 863 | { |
| 864 | |
| 865 | if (!obj) |
| 866 | return -EFAULT; |
| 867 | |
| 868 | if (end < start || !PAGE_ALIGN(start | end)) |
| 869 | return -EINVAL; |
| 870 | |
| 871 | obj->da_start = start; |
| 872 | obj->da_end = end; |
| 873 | |
| 874 | return 0; |
| 875 | } |
| 876 | EXPORT_SYMBOL_GPL(iommu_set_da_range); |
| 877 | |
| 878 | /** |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 879 | * omap_find_iommu_device() - find an omap iommu device by name |
| 880 | * @name: name of the iommu device |
| 881 | * |
| 882 | * The generic iommu API requires the caller to provide the device |
| 883 | * he wishes to attach to a certain iommu domain. |
| 884 | * |
| 885 | * Drivers generally should not bother with this as it should just |
| 886 | * be taken care of by the DMA-API using dev_archdata. |
| 887 | * |
| 888 | * This function is provided as an interim solution until the latter |
| 889 | * materializes, and omap3isp is fully migrated to the DMA-API. |
| 890 | */ |
| 891 | struct device *omap_find_iommu_device(const char *name) |
| 892 | { |
| 893 | return driver_find_device(&omap_iommu_driver.driver, NULL, |
| 894 | (void *)name, |
| 895 | device_match_by_alias); |
| 896 | } |
| 897 | EXPORT_SYMBOL_GPL(omap_find_iommu_device); |
| 898 | |
| 899 | /** |
| 900 | * omap_iommu_attach() - attach iommu device to an iommu domain |
| 901 | * @dev: target omap iommu device |
| 902 | * @iopgd: page table |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 903 | **/ |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 904 | static struct iommu *omap_iommu_attach(struct device *dev, u32 *iopgd) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 905 | { |
| 906 | int err = -ENOMEM; |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 907 | struct iommu *obj = to_iommu(dev); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 908 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 909 | spin_lock(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 910 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 911 | /* an iommu device can only be attached once */ |
| 912 | if (++obj->refcount > 1) { |
| 913 | dev_err(dev, "%s: already attached!\n", obj->name); |
| 914 | err = -EBUSY; |
| 915 | goto err_enable; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 916 | } |
| 917 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 918 | obj->iopgd = iopgd; |
| 919 | err = iommu_enable(obj); |
| 920 | if (err) |
| 921 | goto err_enable; |
| 922 | flush_iotlb_all(obj); |
| 923 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 924 | if (!try_module_get(obj->owner)) |
| 925 | goto err_module; |
| 926 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 927 | spin_unlock(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 928 | |
| 929 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
| 930 | return obj; |
| 931 | |
| 932 | err_module: |
| 933 | if (obj->refcount == 1) |
| 934 | iommu_disable(obj); |
| 935 | err_enable: |
| 936 | obj->refcount--; |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 937 | spin_unlock(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 938 | return ERR_PTR(err); |
| 939 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 940 | |
| 941 | /** |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 942 | * omap_iommu_detach - release iommu device |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 943 | * @obj: target iommu |
| 944 | **/ |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 945 | static void omap_iommu_detach(struct iommu *obj) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 946 | { |
Roel Kluin | acf9d46 | 2010-01-08 10:29:05 -0800 | [diff] [blame] | 947 | if (!obj || IS_ERR(obj)) |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 948 | return; |
| 949 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 950 | spin_lock(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 951 | |
| 952 | if (--obj->refcount == 0) |
| 953 | iommu_disable(obj); |
| 954 | |
| 955 | module_put(obj->owner); |
| 956 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 957 | obj->iopgd = NULL; |
| 958 | |
| 959 | spin_unlock(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 960 | |
| 961 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
| 962 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 963 | |
David Cohen | d594f1f | 2011-02-16 19:35:51 +0000 | [diff] [blame] | 964 | int iommu_set_isr(const char *name, |
| 965 | int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, |
| 966 | void *priv), |
| 967 | void *isr_priv) |
| 968 | { |
| 969 | struct device *dev; |
| 970 | struct iommu *obj; |
| 971 | |
| 972 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, |
| 973 | device_match_by_alias); |
| 974 | if (!dev) |
| 975 | return -ENODEV; |
| 976 | |
| 977 | obj = to_iommu(dev); |
| 978 | mutex_lock(&obj->iommu_lock); |
| 979 | if (obj->refcount != 0) { |
| 980 | mutex_unlock(&obj->iommu_lock); |
| 981 | return -EBUSY; |
| 982 | } |
| 983 | obj->isr = isr; |
| 984 | obj->isr_priv = isr_priv; |
| 985 | mutex_unlock(&obj->iommu_lock); |
| 986 | |
| 987 | return 0; |
| 988 | } |
| 989 | EXPORT_SYMBOL_GPL(iommu_set_isr); |
| 990 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 991 | /* |
| 992 | * OMAP Device MMU(IOMMU) detection |
| 993 | */ |
| 994 | static int __devinit omap_iommu_probe(struct platform_device *pdev) |
| 995 | { |
| 996 | int err = -ENODEV; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 997 | int irq; |
| 998 | struct iommu *obj; |
| 999 | struct resource *res; |
| 1000 | struct iommu_platform_data *pdata = pdev->dev.platform_data; |
| 1001 | |
| 1002 | if (pdev->num_resources != 2) |
| 1003 | return -EINVAL; |
| 1004 | |
| 1005 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
| 1006 | if (!obj) |
| 1007 | return -ENOMEM; |
| 1008 | |
| 1009 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); |
| 1010 | if (IS_ERR(obj->clk)) |
| 1011 | goto err_clk; |
| 1012 | |
| 1013 | obj->nr_tlb_entries = pdata->nr_tlb_entries; |
| 1014 | obj->name = pdata->name; |
| 1015 | obj->dev = &pdev->dev; |
| 1016 | obj->ctx = (void *)obj + sizeof(*obj); |
Guzman Lugo, Fernando | c7f4ab2 | 2010-12-15 00:54:03 +0000 | [diff] [blame] | 1017 | obj->da_start = pdata->da_start; |
| 1018 | obj->da_end = pdata->da_end; |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1019 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 1020 | spin_lock_init(&obj->iommu_lock); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1021 | mutex_init(&obj->mmap_lock); |
| 1022 | spin_lock_init(&obj->page_table_lock); |
| 1023 | INIT_LIST_HEAD(&obj->mmap); |
| 1024 | |
| 1025 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1026 | if (!res) { |
| 1027 | err = -ENODEV; |
| 1028 | goto err_mem; |
| 1029 | } |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1030 | |
| 1031 | res = request_mem_region(res->start, resource_size(res), |
| 1032 | dev_name(&pdev->dev)); |
| 1033 | if (!res) { |
| 1034 | err = -EIO; |
| 1035 | goto err_mem; |
| 1036 | } |
| 1037 | |
Aaro Koskinen | da4a0f7 | 2011-03-14 12:28:32 +0000 | [diff] [blame] | 1038 | obj->regbase = ioremap(res->start, resource_size(res)); |
| 1039 | if (!obj->regbase) { |
| 1040 | err = -ENOMEM; |
| 1041 | goto err_ioremap; |
| 1042 | } |
| 1043 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1044 | irq = platform_get_irq(pdev, 0); |
| 1045 | if (irq < 0) { |
| 1046 | err = -ENODEV; |
| 1047 | goto err_irq; |
| 1048 | } |
| 1049 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, |
| 1050 | dev_name(&pdev->dev), obj); |
| 1051 | if (err < 0) |
| 1052 | goto err_irq; |
| 1053 | platform_set_drvdata(pdev, obj); |
| 1054 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1055 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
| 1056 | return 0; |
| 1057 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1058 | err_irq: |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1059 | iounmap(obj->regbase); |
Aaro Koskinen | da4a0f7 | 2011-03-14 12:28:32 +0000 | [diff] [blame] | 1060 | err_ioremap: |
| 1061 | release_mem_region(res->start, resource_size(res)); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1062 | err_mem: |
| 1063 | clk_put(obj->clk); |
| 1064 | err_clk: |
| 1065 | kfree(obj); |
| 1066 | return err; |
| 1067 | } |
| 1068 | |
| 1069 | static int __devexit omap_iommu_remove(struct platform_device *pdev) |
| 1070 | { |
| 1071 | int irq; |
| 1072 | struct resource *res; |
| 1073 | struct iommu *obj = platform_get_drvdata(pdev); |
| 1074 | |
| 1075 | platform_set_drvdata(pdev, NULL); |
| 1076 | |
| 1077 | iopgtable_clear_entry_all(obj); |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1078 | |
| 1079 | irq = platform_get_irq(pdev, 0); |
| 1080 | free_irq(irq, obj); |
| 1081 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1082 | release_mem_region(res->start, resource_size(res)); |
| 1083 | iounmap(obj->regbase); |
| 1084 | |
| 1085 | clk_put(obj->clk); |
| 1086 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
| 1087 | kfree(obj); |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
| 1091 | static struct platform_driver omap_iommu_driver = { |
| 1092 | .probe = omap_iommu_probe, |
| 1093 | .remove = __devexit_p(omap_iommu_remove), |
| 1094 | .driver = { |
| 1095 | .name = "omap-iommu", |
| 1096 | }, |
| 1097 | }; |
| 1098 | |
| 1099 | static void iopte_cachep_ctor(void *iopte) |
| 1100 | { |
| 1101 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); |
| 1102 | } |
| 1103 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 1104 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
| 1105 | phys_addr_t pa, int order, int prot) |
| 1106 | { |
| 1107 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1108 | struct iommu *oiommu = omap_domain->iommu_dev; |
| 1109 | struct device *dev = oiommu->dev; |
| 1110 | size_t bytes = PAGE_SIZE << order; |
| 1111 | struct iotlb_entry e; |
| 1112 | int omap_pgsz; |
| 1113 | u32 ret, flags; |
| 1114 | |
| 1115 | /* we only support mapping a single iommu page for now */ |
| 1116 | omap_pgsz = bytes_to_iopgsz(bytes); |
| 1117 | if (omap_pgsz < 0) { |
| 1118 | dev_err(dev, "invalid size to map: %d\n", bytes); |
| 1119 | return -EINVAL; |
| 1120 | } |
| 1121 | |
| 1122 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); |
| 1123 | |
| 1124 | flags = omap_pgsz | prot; |
| 1125 | |
| 1126 | iotlb_init_entry(&e, da, pa, flags); |
| 1127 | |
| 1128 | ret = iopgtable_store_entry(oiommu, &e); |
| 1129 | if (ret) { |
| 1130 | dev_err(dev, "iopgtable_store_entry failed: %d\n", ret); |
| 1131 | return ret; |
| 1132 | } |
| 1133 | |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
| 1137 | static int omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
| 1138 | int order) |
| 1139 | { |
| 1140 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1141 | struct iommu *oiommu = omap_domain->iommu_dev; |
| 1142 | struct device *dev = oiommu->dev; |
| 1143 | size_t bytes = PAGE_SIZE << order; |
| 1144 | size_t ret; |
| 1145 | |
| 1146 | dev_dbg(dev, "unmapping da 0x%lx size 0x%x\n", da, bytes); |
| 1147 | |
| 1148 | ret = iopgtable_clear_entry(oiommu, da); |
| 1149 | if (ret != bytes) { |
| 1150 | dev_err(dev, "entry @ 0x%lx was %d; not %d\n", da, ret, bytes); |
| 1151 | return -EINVAL; |
| 1152 | } |
| 1153 | |
| 1154 | return 0; |
| 1155 | } |
| 1156 | |
| 1157 | static int |
| 1158 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) |
| 1159 | { |
| 1160 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1161 | struct iommu *oiommu; |
| 1162 | int ret = 0; |
| 1163 | |
| 1164 | spin_lock(&omap_domain->lock); |
| 1165 | |
| 1166 | /* only a single device is supported per domain for now */ |
| 1167 | if (omap_domain->iommu_dev) { |
| 1168 | dev_err(dev, "iommu domain is already attached\n"); |
| 1169 | ret = -EBUSY; |
| 1170 | goto out; |
| 1171 | } |
| 1172 | |
| 1173 | /* get a handle to and enable the omap iommu */ |
| 1174 | oiommu = omap_iommu_attach(dev, omap_domain->pgtable); |
| 1175 | if (IS_ERR(oiommu)) { |
| 1176 | ret = PTR_ERR(oiommu); |
| 1177 | dev_err(dev, "can't get omap iommu: %d\n", ret); |
| 1178 | goto out; |
| 1179 | } |
| 1180 | |
| 1181 | omap_domain->iommu_dev = oiommu; |
| 1182 | |
| 1183 | out: |
| 1184 | spin_unlock(&omap_domain->lock); |
| 1185 | return ret; |
| 1186 | } |
| 1187 | |
| 1188 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
| 1189 | struct device *dev) |
| 1190 | { |
| 1191 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1192 | struct iommu *oiommu = to_iommu(dev); |
| 1193 | |
| 1194 | spin_lock(&omap_domain->lock); |
| 1195 | |
| 1196 | /* only a single device is supported per domain for now */ |
| 1197 | if (omap_domain->iommu_dev != oiommu) { |
| 1198 | dev_err(dev, "invalid iommu device\n"); |
| 1199 | goto out; |
| 1200 | } |
| 1201 | |
| 1202 | iopgtable_clear_entry_all(oiommu); |
| 1203 | |
| 1204 | omap_iommu_detach(oiommu); |
| 1205 | |
| 1206 | omap_domain->iommu_dev = NULL; |
| 1207 | |
| 1208 | out: |
| 1209 | spin_unlock(&omap_domain->lock); |
| 1210 | } |
| 1211 | |
| 1212 | static int omap_iommu_domain_init(struct iommu_domain *domain) |
| 1213 | { |
| 1214 | struct omap_iommu_domain *omap_domain; |
| 1215 | |
| 1216 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); |
| 1217 | if (!omap_domain) { |
| 1218 | pr_err("kzalloc failed\n"); |
| 1219 | goto out; |
| 1220 | } |
| 1221 | |
| 1222 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); |
| 1223 | if (!omap_domain->pgtable) { |
| 1224 | pr_err("kzalloc failed\n"); |
| 1225 | goto fail_nomem; |
| 1226 | } |
| 1227 | |
| 1228 | /* |
| 1229 | * should never fail, but please keep this around to ensure |
| 1230 | * we keep the hardware happy |
| 1231 | */ |
| 1232 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); |
| 1233 | |
| 1234 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); |
| 1235 | spin_lock_init(&omap_domain->lock); |
| 1236 | |
| 1237 | domain->priv = omap_domain; |
| 1238 | |
| 1239 | return 0; |
| 1240 | |
| 1241 | fail_nomem: |
| 1242 | kfree(omap_domain); |
| 1243 | out: |
| 1244 | return -ENOMEM; |
| 1245 | } |
| 1246 | |
| 1247 | /* assume device was already detached */ |
| 1248 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
| 1249 | { |
| 1250 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1251 | |
| 1252 | domain->priv = NULL; |
| 1253 | |
| 1254 | kfree(omap_domain->pgtable); |
| 1255 | kfree(omap_domain); |
| 1256 | } |
| 1257 | |
| 1258 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, |
| 1259 | unsigned long da) |
| 1260 | { |
| 1261 | struct omap_iommu_domain *omap_domain = domain->priv; |
| 1262 | struct iommu *oiommu = omap_domain->iommu_dev; |
| 1263 | struct device *dev = oiommu->dev; |
| 1264 | u32 *pgd, *pte; |
| 1265 | phys_addr_t ret = 0; |
| 1266 | |
| 1267 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); |
| 1268 | |
| 1269 | if (pte) { |
| 1270 | if (iopte_is_small(*pte)) |
| 1271 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); |
| 1272 | else if (iopte_is_large(*pte)) |
| 1273 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); |
| 1274 | else |
| 1275 | dev_err(dev, "bogus pte 0x%x", *pte); |
| 1276 | } else { |
| 1277 | if (iopgd_is_section(*pgd)) |
| 1278 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); |
| 1279 | else if (iopgd_is_super(*pgd)) |
| 1280 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); |
| 1281 | else |
| 1282 | dev_err(dev, "bogus pgd 0x%x", *pgd); |
| 1283 | } |
| 1284 | |
| 1285 | return ret; |
| 1286 | } |
| 1287 | |
| 1288 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, |
| 1289 | unsigned long cap) |
| 1290 | { |
| 1291 | return 0; |
| 1292 | } |
| 1293 | |
| 1294 | static struct iommu_ops omap_iommu_ops = { |
| 1295 | .domain_init = omap_iommu_domain_init, |
| 1296 | .domain_destroy = omap_iommu_domain_destroy, |
| 1297 | .attach_dev = omap_iommu_attach_dev, |
| 1298 | .detach_dev = omap_iommu_detach_dev, |
| 1299 | .map = omap_iommu_map, |
| 1300 | .unmap = omap_iommu_unmap, |
| 1301 | .iova_to_phys = omap_iommu_iova_to_phys, |
| 1302 | .domain_has_cap = omap_iommu_domain_has_cap, |
| 1303 | }; |
| 1304 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1305 | static int __init omap_iommu_init(void) |
| 1306 | { |
| 1307 | struct kmem_cache *p; |
| 1308 | const unsigned long flags = SLAB_HWCACHE_ALIGN; |
| 1309 | size_t align = 1 << 10; /* L2 pagetable alignement */ |
| 1310 | |
| 1311 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, |
| 1312 | iopte_cachep_ctor); |
| 1313 | if (!p) |
| 1314 | return -ENOMEM; |
| 1315 | iopte_cachep = p; |
| 1316 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 1317 | register_iommu(&omap_iommu_ops); |
| 1318 | |
Hiroshi DOYU | a9dcad5 | 2009-01-26 15:13:40 +0200 | [diff] [blame] | 1319 | return platform_driver_register(&omap_iommu_driver); |
| 1320 | } |
| 1321 | module_init(omap_iommu_init); |
| 1322 | |
| 1323 | static void __exit omap_iommu_exit(void) |
| 1324 | { |
| 1325 | kmem_cache_destroy(iopte_cachep); |
| 1326 | |
| 1327 | platform_driver_unregister(&omap_iommu_driver); |
| 1328 | } |
| 1329 | module_exit(omap_iommu_exit); |
| 1330 | |
| 1331 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); |
| 1332 | MODULE_ALIAS("platform:omap-iommu"); |
| 1333 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); |
| 1334 | MODULE_LICENSE("GPL v2"); |