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Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000021#include <linux/irqchip/chained_irq.h>
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080022#include <linux/io.h>
23#include <linux/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080024#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28/* Since we request GPIOs from ourself */
29#include <linux/pinctrl/consumer.h>
30
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080031#include <mach/hardware.h>
32#include <mach/at91_pio.h>
33
34#include "core.h"
35
Linus Walleij94daf852013-11-05 10:30:14 +010036#define MAX_GPIO_BANKS 5
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080037#define MAX_NB_GPIO_PER_BANK 32
38
39struct at91_pinctrl_mux_ops;
40
41struct at91_gpio_chip {
42 struct gpio_chip chip;
43 struct pinctrl_gpio_range range;
44 struct at91_gpio_chip *next; /* Bank sharing same clock */
45 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
46 int pioc_virq; /* PIO bank Linux virtual interrupt */
47 int pioc_idx; /* PIO bank index */
48 void __iomem *regbase; /* PIO bank virtual address */
49 struct clk *clock; /* associated clock */
50 struct irq_domain *domain; /* associated irq domain */
51 struct at91_pinctrl_mux_ops *ops; /* ops */
52};
53
54#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
55
56static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
57
58static int gpio_banks;
59
Jean-Christophe PLAGNIOL-VILLARD525fae22012-10-23 18:28:00 +020060#define PULL_UP (1 << 0)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080061#define MULTI_DRIVE (1 << 1)
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +080062#define DEGLITCH (1 << 2)
63#define PULL_DOWN (1 << 3)
64#define DIS_SCHMIT (1 << 4)
65#define DEBOUNCE (1 << 16)
66#define DEBOUNCE_VAL_SHIFT 17
67#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +080068
69/**
70 * struct at91_pmx_func - describes AT91 pinmux functions
71 * @name: the name of this specific function
72 * @groups: corresponding pin groups
73 * @ngroups: the number of groups
74 */
75struct at91_pmx_func {
76 const char *name;
77 const char **groups;
78 unsigned ngroups;
79};
80
81enum at91_mux {
82 AT91_MUX_GPIO = 0,
83 AT91_MUX_PERIPH_A = 1,
84 AT91_MUX_PERIPH_B = 2,
85 AT91_MUX_PERIPH_C = 3,
86 AT91_MUX_PERIPH_D = 4,
87};
88
89/**
90 * struct at91_pmx_pin - describes an At91 pin mux
91 * @bank: the bank of the pin
92 * @pin: the pin number in the @bank
93 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
94 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
95 */
96struct at91_pmx_pin {
97 uint32_t bank;
98 uint32_t pin;
99 enum at91_mux mux;
100 unsigned long conf;
101};
102
103/**
104 * struct at91_pin_group - describes an At91 pin group
105 * @name: the name of this specific pin group
106 * @pins_conf: the mux mode for each pin in this group. The size of this
107 * array is the same as pins.
108 * @pins: an array of discrete physical pins used in this group, taken
109 * from the driver-local pin enumeration space
110 * @npins: the number of pins in this group array, i.e. the number of
111 * elements in .pins so we can iterate over that array
112 */
113struct at91_pin_group {
114 const char *name;
115 struct at91_pmx_pin *pins_conf;
116 unsigned int *pins;
117 unsigned npins;
118};
119
120/**
Alexandre Bellonic2eb9e72013-12-07 14:08:52 +0100121 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800122 * on new IP with support for periph C and D the way to mux in
123 * periph A and B has changed
124 * So provide the right call back
125 * if not present means the IP does not support it
126 * @get_periph: return the periph mode configured
127 * @mux_A_periph: mux as periph A
128 * @mux_B_periph: mux as periph B
129 * @mux_C_periph: mux as periph C
130 * @mux_D_periph: mux as periph D
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800131 * @get_deglitch: get deglitch status
132 * @set_deglitch: enable/disable deglitch
133 * @get_debounce: get debounce status
134 * @set_debounce: enable/disable debounce
135 * @get_pulldown: get pulldown status
136 * @set_pulldown: enable/disable pulldown
137 * @get_schmitt_trig: get schmitt trigger status
138 * @disable_schmitt_trig: disable schmitt trigger
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800139 * @irq_type: return irq type
140 */
141struct at91_pinctrl_mux_ops {
142 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
146 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800147 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200148 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800149 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200150 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800151 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
Boris BREZILLON77966ad2013-09-13 09:45:33 +0200152 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800153 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
154 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800155 /* irq */
156 int (*irq_type)(struct irq_data *d, unsigned type);
157};
158
159static int gpio_irq_type(struct irq_data *d, unsigned type);
160static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
161
162struct at91_pinctrl {
163 struct device *dev;
164 struct pinctrl_dev *pctl;
165
166 int nbanks;
167
168 uint32_t *mux_mask;
169 int nmux;
170
171 struct at91_pmx_func *functions;
172 int nfunctions;
173
174 struct at91_pin_group *groups;
175 int ngroups;
176
177 struct at91_pinctrl_mux_ops *ops;
178};
179
180static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
181 const struct at91_pinctrl *info,
182 const char *name)
183{
184 const struct at91_pin_group *grp = NULL;
185 int i;
186
187 for (i = 0; i < info->ngroups; i++) {
188 if (strcmp(info->groups[i].name, name))
189 continue;
190
191 grp = &info->groups[i];
192 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
193 break;
194 }
195
196 return grp;
197}
198
199static int at91_get_groups_count(struct pinctrl_dev *pctldev)
200{
201 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
202
203 return info->ngroups;
204}
205
206static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
207 unsigned selector)
208{
209 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
210
211 return info->groups[selector].name;
212}
213
214static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
215 const unsigned **pins,
216 unsigned *npins)
217{
218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219
220 if (selector >= info->ngroups)
221 return -EINVAL;
222
223 *pins = info->groups[selector].pins;
224 *npins = info->groups[selector].npins;
225
226 return 0;
227}
228
229static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
230 unsigned offset)
231{
232 seq_printf(s, "%s", dev_name(pctldev->dev));
233}
234
235static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
236 struct device_node *np,
237 struct pinctrl_map **map, unsigned *num_maps)
238{
239 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
240 const struct at91_pin_group *grp;
241 struct pinctrl_map *new_map;
242 struct device_node *parent;
243 int map_num = 1;
244 int i;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800245
246 /*
Alexandre Belloni61e310a2013-10-16 16:12:33 +0200247 * first find the group of this node and check if we need to create
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800248 * config maps for pins
249 */
250 grp = at91_pinctrl_find_group_by_name(info, np->name);
251 if (!grp) {
252 dev_err(info->dev, "unable to find group for node %s\n",
253 np->name);
254 return -EINVAL;
255 }
256
257 map_num += grp->npins;
258 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
259 if (!new_map)
260 return -ENOMEM;
261
262 *map = new_map;
263 *num_maps = map_num;
264
265 /* create mux map */
266 parent = of_get_parent(np);
267 if (!parent) {
Julia Lawallc62b2b32012-12-12 15:22:44 +0100268 devm_kfree(pctldev->dev, new_map);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800269 return -EINVAL;
270 }
271 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
272 new_map[0].data.mux.function = parent->name;
273 new_map[0].data.mux.group = np->name;
274 of_node_put(parent);
275
276 /* create config map */
277 new_map++;
278 for (i = 0; i < grp->npins; i++) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800279 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
280 new_map[i].data.configs.group_or_pin =
281 pin_get_name(pctldev, grp->pins[i]);
282 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
283 new_map[i].data.configs.num_configs = 1;
284 }
285
286 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
287 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
288
289 return 0;
290}
291
292static void at91_dt_free_map(struct pinctrl_dev *pctldev,
293 struct pinctrl_map *map, unsigned num_maps)
294{
295}
296
Laurent Pinchart022ab142013-02-16 10:25:07 +0100297static const struct pinctrl_ops at91_pctrl_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800298 .get_groups_count = at91_get_groups_count,
299 .get_group_name = at91_get_group_name,
300 .get_group_pins = at91_get_group_pins,
301 .pin_dbg_show = at91_pin_dbg_show,
302 .dt_node_to_map = at91_dt_node_to_map,
303 .dt_free_map = at91_dt_free_map,
304};
305
Sachin Kamat3c936002013-03-15 10:07:03 +0530306static void __iomem *pin_to_controller(struct at91_pinctrl *info,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800307 unsigned int bank)
308{
309 return gpio_chips[bank]->regbase;
310}
311
312static inline int pin_to_bank(unsigned pin)
313{
314 return pin /= MAX_NB_GPIO_PER_BANK;
315}
316
317static unsigned pin_to_mask(unsigned int pin)
318{
319 return 1 << pin;
320}
321
322static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
323{
324 writel_relaxed(mask, pio + PIO_IDR);
325}
326
327static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
328{
Boris BREZILLON05d35342013-08-27 15:19:21 +0200329 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800330}
331
332static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
333{
334 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
335}
336
337static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
338{
339 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
340}
341
342static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
343{
344 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
345}
346
347static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
348{
349 writel_relaxed(mask, pio + PIO_ASR);
350}
351
352static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
353{
354 writel_relaxed(mask, pio + PIO_BSR);
355}
356
357static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
358{
359
360 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
361 pio + PIO_ABCDSR1);
362 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
363 pio + PIO_ABCDSR2);
364}
365
366static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
367{
368 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
369 pio + PIO_ABCDSR1);
370 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
371 pio + PIO_ABCDSR2);
372}
373
374static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
375{
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
377 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
378}
379
380static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
381{
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
383 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
384}
385
386static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
387{
388 unsigned select;
389
390 if (readl_relaxed(pio + PIO_PSR) & mask)
391 return AT91_MUX_GPIO;
392
393 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
394 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
395
396 return select + 1;
397}
398
399static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
400{
401 unsigned select;
402
403 if (readl_relaxed(pio + PIO_PSR) & mask)
404 return AT91_MUX_GPIO;
405
406 select = readl_relaxed(pio + PIO_ABSR) & mask;
407
408 return select + 1;
409}
410
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800411static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
412{
413 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
414}
415
416static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
417{
418 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
419}
420
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200421static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
422{
423 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
424 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
425
426 return false;
427}
428
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800429static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
430{
431 if (is_on)
432 __raw_writel(mask, pio + PIO_IFSCDR);
433 at91_mux_set_deglitch(pio, mask, is_on);
434}
435
436static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
437{
438 *div = __raw_readl(pio + PIO_SCDR);
439
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200440 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
441 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800442}
443
444static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
445 bool is_on, u32 div)
446{
447 if (is_on) {
448 __raw_writel(mask, pio + PIO_IFSCER);
449 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
450 __raw_writel(mask, pio + PIO_IFER);
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200451 } else
452 __raw_writel(mask, pio + PIO_IFSCDR);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800453}
454
455static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
456{
Boris BREZILLON05d35342013-08-27 15:19:21 +0200457 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800458}
459
460static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
461{
462 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
463}
464
465static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
466{
467 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
468}
469
470static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
471{
472 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
473}
474
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800475static struct at91_pinctrl_mux_ops at91rm9200_ops = {
476 .get_periph = at91_mux_get_periph,
477 .mux_A_periph = at91_mux_set_A_periph,
478 .mux_B_periph = at91_mux_set_B_periph,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800479 .get_deglitch = at91_mux_get_deglitch,
480 .set_deglitch = at91_mux_set_deglitch,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800481 .irq_type = gpio_irq_type,
482};
483
484static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
485 .get_periph = at91_mux_pio3_get_periph,
486 .mux_A_periph = at91_mux_pio3_set_A_periph,
487 .mux_B_periph = at91_mux_pio3_set_B_periph,
488 .mux_C_periph = at91_mux_pio3_set_C_periph,
489 .mux_D_periph = at91_mux_pio3_set_D_periph,
Boris BREZILLONc8dba022013-09-13 09:47:22 +0200490 .get_deglitch = at91_mux_pio3_get_deglitch,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800491 .set_deglitch = at91_mux_pio3_set_deglitch,
492 .get_debounce = at91_mux_pio3_get_debounce,
493 .set_debounce = at91_mux_pio3_set_debounce,
494 .get_pulldown = at91_mux_pio3_get_pulldown,
495 .set_pulldown = at91_mux_pio3_set_pulldown,
496 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
497 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800498 .irq_type = alt_gpio_irq_type,
499};
500
501static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
502{
503 if (pin->mux) {
504 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
505 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
506 } else {
507 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
508 pin->bank + 'A', pin->pin, pin->conf);
509 }
510}
511
Sachin Kamat3c936002013-03-15 10:07:03 +0530512static int pin_check_config(struct at91_pinctrl *info, const char *name,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800513 int index, const struct at91_pmx_pin *pin)
514{
515 int mux;
516
517 /* check if it's a valid config */
518 if (pin->bank >= info->nbanks) {
519 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
520 name, index, pin->bank, info->nbanks);
521 return -EINVAL;
522 }
523
524 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
525 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
526 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
527 return -EINVAL;
528 }
529
530 if (!pin->mux)
531 return 0;
532
533 mux = pin->mux - 1;
534
535 if (mux >= info->nmux) {
536 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
537 name, index, mux, info->nmux);
538 return -EINVAL;
539 }
540
541 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
542 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
543 name, index, mux, pin->bank + 'A', pin->pin);
544 return -EINVAL;
545 }
546
547 return 0;
548}
549
550static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
551{
552 writel_relaxed(mask, pio + PIO_PDR);
553}
554
555static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
556{
557 writel_relaxed(mask, pio + PIO_PER);
558 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
559}
560
561static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
562 unsigned group)
563{
564 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
565 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
566 const struct at91_pmx_pin *pin;
567 uint32_t npins = info->groups[group].npins;
568 int i, ret;
569 unsigned mask;
570 void __iomem *pio;
571
572 dev_dbg(info->dev, "enable function %s group %s\n",
573 info->functions[selector].name, info->groups[group].name);
574
575 /* first check that all the pins of the group are valid with a valid
Alexandre Belloni61e310a2013-10-16 16:12:33 +0200576 * parameter */
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800577 for (i = 0; i < npins; i++) {
578 pin = &pins_conf[i];
579 ret = pin_check_config(info, info->groups[group].name, i, pin);
580 if (ret)
581 return ret;
582 }
583
584 for (i = 0; i < npins; i++) {
585 pin = &pins_conf[i];
586 at91_pin_dbg(info->dev, pin);
587 pio = pin_to_controller(info, pin->bank);
588 mask = pin_to_mask(pin->pin);
589 at91_mux_disable_interrupt(pio, mask);
Sachin Kamat3c936002013-03-15 10:07:03 +0530590 switch (pin->mux) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800591 case AT91_MUX_GPIO:
592 at91_mux_gpio_enable(pio, mask, 1);
593 break;
594 case AT91_MUX_PERIPH_A:
595 info->ops->mux_A_periph(pio, mask);
596 break;
597 case AT91_MUX_PERIPH_B:
598 info->ops->mux_B_periph(pio, mask);
599 break;
600 case AT91_MUX_PERIPH_C:
601 if (!info->ops->mux_C_periph)
602 return -EINVAL;
603 info->ops->mux_C_periph(pio, mask);
604 break;
605 case AT91_MUX_PERIPH_D:
606 if (!info->ops->mux_D_periph)
607 return -EINVAL;
608 info->ops->mux_D_periph(pio, mask);
609 break;
610 }
611 if (pin->mux)
612 at91_mux_gpio_disable(pio, mask);
613 }
614
615 return 0;
616}
617
618static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
619 unsigned group)
620{
621 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
622 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
623 const struct at91_pmx_pin *pin;
624 uint32_t npins = info->groups[group].npins;
625 int i;
626 unsigned mask;
627 void __iomem *pio;
628
629 for (i = 0; i < npins; i++) {
630 pin = &pins_conf[i];
631 at91_pin_dbg(info->dev, pin);
632 pio = pin_to_controller(info, pin->bank);
633 mask = pin_to_mask(pin->pin);
634 at91_mux_gpio_enable(pio, mask, 1);
635 }
636}
637
638static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
639{
640 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
641
642 return info->nfunctions;
643}
644
645static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
646 unsigned selector)
647{
648 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
649
650 return info->functions[selector].name;
651}
652
653static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
654 const char * const **groups,
655 unsigned * const num_groups)
656{
657 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
658
659 *groups = info->functions[selector].groups;
660 *num_groups = info->functions[selector].ngroups;
661
662 return 0;
663}
664
Axel Linf6f94f62012-11-05 21:23:50 +0800665static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
666 struct pinctrl_gpio_range *range,
667 unsigned offset)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800668{
669 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
670 struct at91_gpio_chip *at91_chip;
671 struct gpio_chip *chip;
672 unsigned mask;
673
674 if (!range) {
675 dev_err(npct->dev, "invalid range\n");
676 return -EINVAL;
677 }
678 if (!range->gc) {
679 dev_err(npct->dev, "missing GPIO chip in range\n");
680 return -EINVAL;
681 }
682 chip = range->gc;
683 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
684
685 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
686
687 mask = 1 << (offset - chip->base);
688
689 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
690 offset, 'A' + range->id, offset - chip->base, mask);
691
692 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
693
694 return 0;
695}
696
Axel Linf6f94f62012-11-05 21:23:50 +0800697static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
698 struct pinctrl_gpio_range *range,
699 unsigned offset)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800700{
701 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
702
703 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
704 /* Set the pin to some default state, GPIO is usually default */
705}
706
Laurent Pinchart022ab142013-02-16 10:25:07 +0100707static const struct pinmux_ops at91_pmx_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800708 .get_functions_count = at91_pmx_get_funcs_count,
709 .get_function_name = at91_pmx_get_func_name,
710 .get_function_groups = at91_pmx_get_groups,
711 .enable = at91_pmx_enable,
712 .disable = at91_pmx_disable,
713 .gpio_request_enable = at91_gpio_request_enable,
714 .gpio_disable_free = at91_gpio_disable_free,
715};
716
717static int at91_pinconf_get(struct pinctrl_dev *pctldev,
718 unsigned pin_id, unsigned long *config)
719{
720 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
721 void __iomem *pio;
722 unsigned pin;
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800723 int div;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800724
Alexandre Belloni1292e692013-12-07 14:08:53 +0100725 *config = 0;
726 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800727 pio = pin_to_controller(info, pin_to_bank(pin_id));
728 pin = pin_id % MAX_NB_GPIO_PER_BANK;
729
730 if (at91_mux_get_multidrive(pio, pin))
731 *config |= MULTI_DRIVE;
732
733 if (at91_mux_get_pullup(pio, pin))
734 *config |= PULL_UP;
735
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800736 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
737 *config |= DEGLITCH;
738 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
739 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
740 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
741 *config |= PULL_DOWN;
742 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
743 *config |= DIS_SCHMIT;
744
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800745 return 0;
746}
747
748static int at91_pinconf_set(struct pinctrl_dev *pctldev,
Sherman Yin03b054e2013-08-27 11:32:12 -0700749 unsigned pin_id, unsigned long *configs,
750 unsigned num_configs)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800751{
752 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
753 unsigned mask;
754 void __iomem *pio;
Sherman Yin03b054e2013-08-27 11:32:12 -0700755 int i;
756 unsigned long config;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800757
Sherman Yin03b054e2013-08-27 11:32:12 -0700758 for (i = 0; i < num_configs; i++) {
759 config = configs[i];
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800760
Sherman Yin03b054e2013-08-27 11:32:12 -0700761 dev_dbg(info->dev,
762 "%s:%d, pin_id=%d, config=0x%lx",
763 __func__, __LINE__, pin_id, config);
764 pio = pin_to_controller(info, pin_to_bank(pin_id));
765 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800766
Sherman Yin03b054e2013-08-27 11:32:12 -0700767 if (config & PULL_UP && config & PULL_DOWN)
768 return -EINVAL;
769
770 at91_mux_set_pullup(pio, mask, config & PULL_UP);
771 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
772 if (info->ops->set_deglitch)
773 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
774 if (info->ops->set_debounce)
775 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800776 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
Sherman Yin03b054e2013-08-27 11:32:12 -0700777 if (info->ops->set_pulldown)
778 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
779 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
780 info->ops->disable_schmitt_trig(pio, mask);
781
782 } /* for each config */
Jean-Christophe PLAGNIOL-VILLARD7ebd7a32012-09-26 14:57:45 +0800783
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800784 return 0;
785}
786
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100787#define DBG_SHOW_FLAG(flag) do { \
788 if (config & flag) { \
789 if (num_conf) \
790 seq_puts(s, "|"); \
791 seq_puts(s, #flag); \
792 num_conf++; \
793 } \
794} while (0)
795
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800796static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
797 struct seq_file *s, unsigned pin_id)
798{
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100799 unsigned long config;
800 int ret, val, num_conf = 0;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800801
Alexandre Belloni4d9b8a82013-12-07 14:08:54 +0100802 ret = at91_pinconf_get(pctldev, pin_id, &config);
803
804 DBG_SHOW_FLAG(MULTI_DRIVE);
805 DBG_SHOW_FLAG(PULL_UP);
806 DBG_SHOW_FLAG(PULL_DOWN);
807 DBG_SHOW_FLAG(DIS_SCHMIT);
808 DBG_SHOW_FLAG(DEGLITCH);
809 DBG_SHOW_FLAG(DEBOUNCE);
810 if (config & DEBOUNCE) {
811 val = config >> DEBOUNCE_VAL_SHIFT;
812 seq_printf(s, "(%d)", val);
813 }
814
815 return;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800816}
817
818static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
819 struct seq_file *s, unsigned group)
820{
821}
822
Laurent Pinchart022ab142013-02-16 10:25:07 +0100823static const struct pinconf_ops at91_pinconf_ops = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800824 .pin_config_get = at91_pinconf_get,
825 .pin_config_set = at91_pinconf_set,
826 .pin_config_dbg_show = at91_pinconf_dbg_show,
827 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
828};
829
830static struct pinctrl_desc at91_pinctrl_desc = {
831 .pctlops = &at91_pctrl_ops,
832 .pmxops = &at91_pmx_ops,
833 .confops = &at91_pinconf_ops,
834 .owner = THIS_MODULE,
835};
836
837static const char *gpio_compat = "atmel,at91rm9200-gpio";
838
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800839static void at91_pinctrl_child_count(struct at91_pinctrl *info,
840 struct device_node *np)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800841{
842 struct device_node *child;
843
844 for_each_child_of_node(np, child) {
845 if (of_device_is_compatible(child, gpio_compat)) {
846 info->nbanks++;
847 } else {
848 info->nfunctions++;
849 info->ngroups += of_get_child_count(child);
850 }
851 }
852}
853
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800854static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
855 struct device_node *np)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800856{
857 int ret = 0;
858 int size;
Sachin Kamat1164d732013-03-15 10:07:02 +0530859 const __be32 *list;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800860
861 list = of_get_property(np, "atmel,mux-mask", &size);
862 if (!list) {
863 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
864 return -EINVAL;
865 }
866
867 size /= sizeof(*list);
868 if (!size || size % info->nbanks) {
869 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
870 return -EINVAL;
871 }
872 info->nmux = size / info->nbanks;
873
874 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
875 if (!info->mux_mask) {
876 dev_err(info->dev, "could not alloc mux_mask\n");
877 return -ENOMEM;
878 }
879
880 ret = of_property_read_u32_array(np, "atmel,mux-mask",
881 info->mux_mask, size);
882 if (ret)
883 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
884 return ret;
885}
886
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800887static int at91_pinctrl_parse_groups(struct device_node *np,
888 struct at91_pin_group *grp,
889 struct at91_pinctrl *info, u32 index)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800890{
891 struct at91_pmx_pin *pin;
892 int size;
Sachin Kamat1164d732013-03-15 10:07:02 +0530893 const __be32 *list;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800894 int i, j;
895
896 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
897
898 /* Initialise group */
899 grp->name = np->name;
900
901 /*
902 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
903 * do sanity check and calculate pins number
904 */
905 list = of_get_property(np, "atmel,pins", &size);
906 /* we do not check return since it's safe node passed down */
907 size /= sizeof(*list);
908 if (!size || size % 4) {
909 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
910 return -EINVAL;
911 }
912
913 grp->npins = size / 4;
914 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
915 GFP_KERNEL);
916 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
917 GFP_KERNEL);
918 if (!grp->pins_conf || !grp->pins)
919 return -ENOMEM;
920
921 for (i = 0, j = 0; i < size; i += 4, j++) {
922 pin->bank = be32_to_cpu(*list++);
923 pin->pin = be32_to_cpu(*list++);
924 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
925 pin->mux = be32_to_cpu(*list++);
926 pin->conf = be32_to_cpu(*list++);
927
928 at91_pin_dbg(info->dev, pin);
929 pin++;
930 }
931
932 return 0;
933}
934
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800935static int at91_pinctrl_parse_functions(struct device_node *np,
936 struct at91_pinctrl *info, u32 index)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800937{
938 struct device_node *child;
939 struct at91_pmx_func *func;
940 struct at91_pin_group *grp;
941 int ret;
942 static u32 grp_index;
943 u32 i = 0;
944
945 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
946
947 func = &info->functions[index];
948
949 /* Initialise function */
950 func->name = np->name;
951 func->ngroups = of_get_child_count(np);
952 if (func->ngroups <= 0) {
953 dev_err(info->dev, "no groups defined\n");
954 return -EINVAL;
955 }
956 func->groups = devm_kzalloc(info->dev,
957 func->ngroups * sizeof(char *), GFP_KERNEL);
958 if (!func->groups)
959 return -ENOMEM;
960
961 for_each_child_of_node(np, child) {
962 func->groups[i] = child->name;
963 grp = &info->groups[grp_index++];
964 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
965 if (ret)
966 return ret;
967 }
968
969 return 0;
970}
971
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800972static struct of_device_id at91_pinctrl_of_match[] = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800973 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
974 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
975 { /* sentinel */ }
976};
977
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800978static int at91_pinctrl_probe_dt(struct platform_device *pdev,
979 struct at91_pinctrl *info)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800980{
981 int ret = 0;
982 int i, j;
983 uint32_t *tmp;
984 struct device_node *np = pdev->dev.of_node;
985 struct device_node *child;
986
987 if (!np)
988 return -ENODEV;
989
990 info->dev = &pdev->dev;
Sachin Kamat3c936002013-03-15 10:07:03 +0530991 info->ops = (struct at91_pinctrl_mux_ops *)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800992 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
993 at91_pinctrl_child_count(info, np);
994
995 if (info->nbanks < 1) {
Alexandre Belloni61e310a2013-10-16 16:12:33 +0200996 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +0800997 return -EINVAL;
998 }
999
1000 ret = at91_pinctrl_mux_mask(info, np);
1001 if (ret)
1002 return ret;
1003
1004 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1005
1006 dev_dbg(&pdev->dev, "mux-mask\n");
1007 tmp = info->mux_mask;
1008 for (i = 0; i < info->nbanks; i++) {
1009 for (j = 0; j < info->nmux; j++, tmp++) {
1010 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1011 }
1012 }
1013
1014 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1015 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1016 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1017 GFP_KERNEL);
1018 if (!info->functions)
1019 return -ENOMEM;
1020
1021 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1022 GFP_KERNEL);
1023 if (!info->groups)
1024 return -ENOMEM;
1025
1026 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
1027 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1028 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1029
1030 i = 0;
1031
1032 for_each_child_of_node(np, child) {
1033 if (of_device_is_compatible(child, gpio_compat))
1034 continue;
1035 ret = at91_pinctrl_parse_functions(child, info, i++);
1036 if (ret) {
1037 dev_err(&pdev->dev, "failed to parse function\n");
1038 return ret;
1039 }
1040 }
1041
1042 return 0;
1043}
1044
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001045static int at91_pinctrl_probe(struct platform_device *pdev)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001046{
1047 struct at91_pinctrl *info;
1048 struct pinctrl_pin_desc *pdesc;
Sachin Kamat3c936002013-03-15 10:07:03 +05301049 int ret, i, j, k;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001050
1051 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1052 if (!info)
1053 return -ENOMEM;
1054
1055 ret = at91_pinctrl_probe_dt(pdev, info);
1056 if (ret)
1057 return ret;
1058
1059 /*
1060 * We need all the GPIO drivers to probe FIRST, or we will not be able
1061 * to obtain references to the struct gpio_chip * for them, and we
1062 * need this to proceed.
1063 */
1064 for (i = 0; i < info->nbanks; i++) {
1065 if (!gpio_chips[i]) {
1066 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1067 devm_kfree(&pdev->dev, info);
1068 return -EPROBE_DEFER;
1069 }
1070 }
1071
1072 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1073 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1074 at91_pinctrl_desc.pins = pdesc =
1075 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1076
1077 if (!at91_pinctrl_desc.pins)
1078 return -ENOMEM;
1079
1080 for (i = 0 , k = 0; i < info->nbanks; i++) {
1081 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1082 pdesc->number = k;
1083 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1084 pdesc++;
1085 }
1086 }
1087
1088 platform_set_drvdata(pdev, info);
1089 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1090
1091 if (!info->pctl) {
1092 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1093 ret = -EINVAL;
1094 goto err;
1095 }
1096
1097 /* We will handle a range of GPIO pins */
1098 for (i = 0; i < info->nbanks; i++)
1099 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1100
1101 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1102
1103 return 0;
1104
1105err:
1106 return ret;
1107}
1108
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001109static int at91_pinctrl_remove(struct platform_device *pdev)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001110{
1111 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1112
1113 pinctrl_unregister(info->pctl);
1114
1115 return 0;
1116}
1117
1118static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1119{
1120 /*
1121 * Map back to global GPIO space and request muxing, the direction
1122 * parameter does not matter for this controller.
1123 */
1124 int gpio = chip->base + offset;
1125 int bank = chip->base / chip->ngpio;
1126
1127 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1128 'A' + bank, offset, gpio);
1129
1130 return pinctrl_request_gpio(gpio);
1131}
1132
1133static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1134{
1135 int gpio = chip->base + offset;
1136
1137 pinctrl_free_gpio(gpio);
1138}
1139
1140static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1141{
1142 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1143 void __iomem *pio = at91_gpio->regbase;
1144 unsigned mask = 1 << offset;
1145
1146 writel_relaxed(mask, pio + PIO_ODR);
1147 return 0;
1148}
1149
1150static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1151{
1152 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1153 void __iomem *pio = at91_gpio->regbase;
1154 unsigned mask = 1 << offset;
1155 u32 pdsr;
1156
1157 pdsr = readl_relaxed(pio + PIO_PDSR);
1158 return (pdsr & mask) != 0;
1159}
1160
1161static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1162 int val)
1163{
1164 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1165 void __iomem *pio = at91_gpio->regbase;
1166 unsigned mask = 1 << offset;
1167
1168 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1169}
1170
1171static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1172 int val)
1173{
1174 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1175 void __iomem *pio = at91_gpio->regbase;
1176 unsigned mask = 1 << offset;
1177
1178 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1179 writel_relaxed(mask, pio + PIO_OER);
1180
1181 return 0;
1182}
1183
1184static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1185{
1186 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1187 int virq;
1188
1189 if (offset < chip->ngpio)
1190 virq = irq_create_mapping(at91_gpio->domain, offset);
1191 else
1192 virq = -ENXIO;
1193
1194 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1195 chip->label, offset + chip->base, virq);
1196 return virq;
1197}
1198
1199#ifdef CONFIG_DEBUG_FS
1200static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1201{
1202 enum at91_mux mode;
1203 int i;
1204 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1205 void __iomem *pio = at91_gpio->regbase;
1206
1207 for (i = 0; i < chip->ngpio; i++) {
1208 unsigned pin = chip->base + i;
1209 unsigned mask = pin_to_mask(pin);
1210 const char *gpio_label;
1211 u32 pdsr;
1212
1213 gpio_label = gpiochip_is_requested(chip, i);
1214 if (!gpio_label)
1215 continue;
1216 mode = at91_gpio->ops->get_periph(pio, mask);
1217 seq_printf(s, "[%s] GPIO%s%d: ",
1218 gpio_label, chip->label, i);
1219 if (mode == AT91_MUX_GPIO) {
1220 pdsr = readl_relaxed(pio + PIO_PDSR);
1221
1222 seq_printf(s, "[gpio] %s\n",
1223 pdsr & mask ?
1224 "set" : "clear");
1225 } else {
1226 seq_printf(s, "[periph %c]\n",
1227 mode + 'A' - 1);
1228 }
1229 }
1230}
1231#else
1232#define at91_gpio_dbg_show NULL
1233#endif
1234
1235/* Several AIC controller irqs are dispatched through this GPIO handler.
1236 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1237 * at91_set_gpio_input() then maybe enable its glitch filter.
1238 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1239 * handler.
1240 * First implementation always triggers on rising and falling edges
1241 * whereas the newer PIO3 can be additionally configured to trigger on
1242 * level, edge with any polarity.
1243 *
1244 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1245 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1246 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1247 */
1248
1249static void gpio_irq_mask(struct irq_data *d)
1250{
1251 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1252 void __iomem *pio = at91_gpio->regbase;
1253 unsigned mask = 1 << d->hwirq;
1254
1255 if (pio)
1256 writel_relaxed(mask, pio + PIO_IDR);
1257}
1258
1259static void gpio_irq_unmask(struct irq_data *d)
1260{
1261 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1262 void __iomem *pio = at91_gpio->regbase;
1263 unsigned mask = 1 << d->hwirq;
1264
1265 if (pio)
1266 writel_relaxed(mask, pio + PIO_IER);
1267}
1268
1269static int gpio_irq_type(struct irq_data *d, unsigned type)
1270{
1271 switch (type) {
1272 case IRQ_TYPE_NONE:
1273 case IRQ_TYPE_EDGE_BOTH:
1274 return 0;
1275 default:
1276 return -EINVAL;
1277 }
1278}
1279
1280/* Alternate irq type for PIO3 support */
1281static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1282{
1283 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1284 void __iomem *pio = at91_gpio->regbase;
1285 unsigned mask = 1 << d->hwirq;
1286
1287 switch (type) {
1288 case IRQ_TYPE_EDGE_RISING:
Nicolas Ferreb0dcfd82014-01-21 16:55:18 +01001289 __irq_set_handler_locked(d->irq, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001290 writel_relaxed(mask, pio + PIO_ESR);
1291 writel_relaxed(mask, pio + PIO_REHLSR);
1292 break;
1293 case IRQ_TYPE_EDGE_FALLING:
Nicolas Ferreb0dcfd82014-01-21 16:55:18 +01001294 __irq_set_handler_locked(d->irq, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001295 writel_relaxed(mask, pio + PIO_ESR);
1296 writel_relaxed(mask, pio + PIO_FELLSR);
1297 break;
1298 case IRQ_TYPE_LEVEL_LOW:
Nicolas Ferreb0dcfd82014-01-21 16:55:18 +01001299 __irq_set_handler_locked(d->irq, handle_level_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001300 writel_relaxed(mask, pio + PIO_LSR);
1301 writel_relaxed(mask, pio + PIO_FELLSR);
1302 break;
1303 case IRQ_TYPE_LEVEL_HIGH:
Nicolas Ferreb0dcfd82014-01-21 16:55:18 +01001304 __irq_set_handler_locked(d->irq, handle_level_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001305 writel_relaxed(mask, pio + PIO_LSR);
1306 writel_relaxed(mask, pio + PIO_REHLSR);
1307 break;
1308 case IRQ_TYPE_EDGE_BOTH:
1309 /*
1310 * disable additional interrupt modes:
1311 * fall back to default behavior
1312 */
Nicolas Ferreb0dcfd82014-01-21 16:55:18 +01001313 __irq_set_handler_locked(d->irq, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001314 writel_relaxed(mask, pio + PIO_AIMDR);
1315 return 0;
1316 case IRQ_TYPE_NONE:
1317 default:
1318 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1319 return -EINVAL;
1320 }
1321
1322 /* enable additional interrupt modes */
1323 writel_relaxed(mask, pio + PIO_AIMER);
1324
1325 return 0;
1326}
1327
Jean-Jacques Hiblot94e69202014-01-23 11:37:58 +01001328static unsigned int gpio_irq_startup(struct irq_data *d)
1329{
1330 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1331 unsigned pin = d->hwirq;
1332 int ret;
1333
1334 ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
1335 if (ret) {
1336 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1337 d->hwirq);
1338 return ret;
1339 }
1340 gpio_irq_unmask(d);
1341 return 0;
1342}
1343
1344static void gpio_irq_shutdown(struct irq_data *d)
1345{
1346 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1347 unsigned pin = d->hwirq;
1348
1349 gpio_irq_mask(d);
1350 gpio_unlock_as_irq(&at91_gpio->chip, pin);
1351}
1352
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001353#ifdef CONFIG_PM
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001354
1355static u32 wakeups[MAX_GPIO_BANKS];
1356static u32 backups[MAX_GPIO_BANKS];
1357
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001358static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1359{
1360 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1361 unsigned bank = at91_gpio->pioc_idx;
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001362 unsigned mask = 1 << d->hwirq;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001363
1364 if (unlikely(bank >= MAX_GPIO_BANKS))
1365 return -EINVAL;
1366
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001367 if (state)
1368 wakeups[bank] |= mask;
1369 else
1370 wakeups[bank] &= ~mask;
1371
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001372 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1373
1374 return 0;
1375}
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001376
1377void at91_pinctrl_gpio_suspend(void)
1378{
1379 int i;
1380
1381 for (i = 0; i < gpio_banks; i++) {
1382 void __iomem *pio;
1383
1384 if (!gpio_chips[i])
1385 continue;
1386
1387 pio = gpio_chips[i]->regbase;
1388
1389 backups[i] = __raw_readl(pio + PIO_IMR);
1390 __raw_writel(backups[i], pio + PIO_IDR);
1391 __raw_writel(wakeups[i], pio + PIO_IER);
1392
Boris BREZILLON795f9952013-12-15 19:30:51 +01001393 if (!wakeups[i])
1394 clk_disable_unprepare(gpio_chips[i]->clock);
1395 else
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001396 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1397 'A'+i, wakeups[i]);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001398 }
1399}
1400
1401void at91_pinctrl_gpio_resume(void)
1402{
1403 int i;
1404
1405 for (i = 0; i < gpio_banks; i++) {
1406 void __iomem *pio;
1407
1408 if (!gpio_chips[i])
1409 continue;
1410
1411 pio = gpio_chips[i]->regbase;
1412
Boris BREZILLON37ef1d92013-12-15 19:30:52 +01001413 if (!wakeups[i])
1414 clk_prepare_enable(gpio_chips[i]->clock);
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001415
1416 __raw_writel(wakeups[i], pio + PIO_IDR);
1417 __raw_writel(backups[i], pio + PIO_IER);
1418 }
1419}
1420
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001421#else
1422#define gpio_irq_set_wake NULL
Ludovic Desroches647f8d92013-03-08 16:18:21 +01001423#endif /* CONFIG_PM */
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001424
1425static struct irq_chip gpio_irqchip = {
1426 .name = "GPIO",
Jean-Jacques Hiblot94e69202014-01-23 11:37:58 +01001427 .irq_startup = gpio_irq_startup,
1428 .irq_shutdown = gpio_irq_shutdown,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001429 .irq_disable = gpio_irq_mask,
1430 .irq_mask = gpio_irq_mask,
1431 .irq_unmask = gpio_irq_unmask,
1432 /* .irq_set_type is set dynamically */
1433 .irq_set_wake = gpio_irq_set_wake,
1434};
1435
1436static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1437{
1438 struct irq_chip *chip = irq_desc_get_chip(desc);
1439 struct irq_data *idata = irq_desc_get_irq_data(desc);
1440 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1441 void __iomem *pio = at91_gpio->regbase;
1442 unsigned long isr;
1443 int n;
1444
1445 chained_irq_enter(chip, desc);
1446 for (;;) {
1447 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
Alexandre Bellonic2eb9e72013-12-07 14:08:52 +01001448 * When there are none pending, we're finished unless we need
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001449 * to process multiple banks (like ID_PIOCDE on sam9263).
1450 */
1451 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1452 if (!isr) {
1453 if (!at91_gpio->next)
1454 break;
1455 at91_gpio = at91_gpio->next;
1456 pio = at91_gpio->regbase;
1457 continue;
1458 }
1459
Wei Yongjun05daa162012-10-26 22:50:54 +08001460 for_each_set_bit(n, &isr, BITS_PER_LONG) {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001461 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001462 }
1463 }
1464 chained_irq_exit(chip, desc);
1465 /* now it may re-trigger */
1466}
1467
1468/*
1469 * This lock class tells lockdep that GPIO irqs are in a different
1470 * category than their parents, so it won't report false recursion.
1471 */
1472static struct lock_class_key gpio_lock_class;
1473
1474static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1475 irq_hw_number_t hw)
1476{
1477 struct at91_gpio_chip *at91_gpio = h->host_data;
Boris BREZILLON99fce022013-07-20 16:51:33 +02001478 void __iomem *pio = at91_gpio->regbase;
1479 u32 mask = 1 << hw;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001480
1481 irq_set_lockdep_class(virq, &gpio_lock_class);
1482
1483 /*
1484 * Can use the "simple" and not "edge" handler since it's
1485 * shorter, and the AIC handles interrupts sanely.
1486 */
Boris BREZILLON99fce022013-07-20 16:51:33 +02001487 irq_set_chip(virq, &gpio_irqchip);
1488 if ((at91_gpio->ops == &at91sam9x5_ops) &&
1489 (readl_relaxed(pio + PIO_AIMMR) & mask) &&
1490 (readl_relaxed(pio + PIO_ELSR) & mask))
1491 irq_set_handler(virq, handle_level_irq);
1492 else
1493 irq_set_handler(virq, handle_simple_irq);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001494 set_irq_flags(virq, IRQF_VALID);
1495 irq_set_chip_data(virq, at91_gpio);
1496
1497 return 0;
1498}
1499
Axel Linf6f94f62012-11-05 21:23:50 +08001500static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1501 struct device_node *ctrlr,
1502 const u32 *intspec, unsigned int intsize,
1503 irq_hw_number_t *out_hwirq,
1504 unsigned int *out_type)
Jean-Christophe PLAGNIOL-VILLARDa728c7c2012-10-23 15:56:41 +02001505{
1506 struct at91_gpio_chip *at91_gpio = d->host_data;
1507 int ret;
1508 int pin = at91_gpio->chip.base + intspec[0];
1509
1510 if (WARN_ON(intsize < 2))
1511 return -EINVAL;
1512 *out_hwirq = intspec[0];
1513 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1514
1515 ret = gpio_request(pin, ctrlr->full_name);
1516 if (ret)
1517 return ret;
1518
1519 ret = gpio_direction_input(pin);
1520 if (ret)
1521 return ret;
1522
1523 return 0;
1524}
1525
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001526static struct irq_domain_ops at91_gpio_ops = {
1527 .map = at91_gpio_irq_map,
Jean-Christophe PLAGNIOL-VILLARDa728c7c2012-10-23 15:56:41 +02001528 .xlate = at91_gpio_irq_domain_xlate,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001529};
1530
1531static int at91_gpio_of_irq_setup(struct device_node *node,
1532 struct at91_gpio_chip *at91_gpio)
1533{
1534 struct at91_gpio_chip *prev = NULL;
1535 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1536
1537 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1538
1539 /* Setup proper .irq_set_type function */
1540 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1541
1542 /* Disable irqs of this PIO controller */
1543 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1544
1545 /* Setup irq domain */
1546 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1547 &at91_gpio_ops, at91_gpio);
1548 if (!at91_gpio->domain)
1549 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1550 at91_gpio->pioc_idx);
1551
1552 /* Setup chained handler */
1553 if (at91_gpio->pioc_idx)
1554 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1555
Alexandre Belloni61e310a2013-10-16 16:12:33 +02001556 /* The top level handler handles one bank of GPIOs, except
Alexandre Bellonic2eb9e72013-12-07 14:08:52 +01001557 * on some SoC it can handle up to three...
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001558 * We only set up the handler for the first of the list.
1559 */
1560 if (prev && prev->next == at91_gpio)
1561 return 0;
1562
1563 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1564 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1565
1566 return 0;
1567}
1568
1569/* This structure is replicated for each GPIO block allocated at probe time */
1570static struct gpio_chip at91_gpio_template = {
1571 .request = at91_gpio_request,
1572 .free = at91_gpio_free,
1573 .direction_input = at91_gpio_direction_input,
1574 .get = at91_gpio_get,
1575 .direction_output = at91_gpio_direction_output,
1576 .set = at91_gpio_set,
1577 .to_irq = at91_gpio_to_irq,
1578 .dbg_show = at91_gpio_dbg_show,
Linus Walleij9fb1f392013-12-04 14:42:46 +01001579 .can_sleep = false,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001580 .ngpio = MAX_NB_GPIO_PER_BANK,
1581};
1582
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001583static void at91_gpio_probe_fixup(void)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001584{
1585 unsigned i;
1586 struct at91_gpio_chip *at91_gpio, *last = NULL;
1587
1588 for (i = 0; i < gpio_banks; i++) {
1589 at91_gpio = gpio_chips[i];
1590
1591 /*
1592 * GPIO controller are grouped on some SoC:
1593 * PIOC, PIOD and PIOE can share the same IRQ line
1594 */
1595 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1596 last->next = at91_gpio;
1597 last = at91_gpio;
1598 }
1599}
1600
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001601static struct of_device_id at91_gpio_of_match[] = {
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001602 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1603 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1604 { /* sentinel */ }
1605};
1606
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001607static int at91_gpio_probe(struct platform_device *pdev)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001608{
1609 struct device_node *np = pdev->dev.of_node;
1610 struct resource *res;
1611 struct at91_gpio_chip *at91_chip = NULL;
1612 struct gpio_chip *chip;
1613 struct pinctrl_gpio_range *range;
1614 int ret = 0;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001615 int irq, i;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001616 int alias_idx = of_alias_get_id(np, "gpio");
1617 uint32_t ngpio;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001618 char **names;
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001619
1620 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1621 if (gpio_chips[alias_idx]) {
1622 ret = -EBUSY;
1623 goto err;
1624 }
1625
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001626 irq = platform_get_irq(pdev, 0);
1627 if (irq < 0) {
1628 ret = irq;
1629 goto err;
1630 }
1631
1632 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1633 if (!at91_chip) {
1634 ret = -ENOMEM;
1635 goto err;
1636 }
1637
Wolfram Sangf50b9e12013-05-10 10:17:03 +02001638 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding9e0c1fb2013-01-21 11:09:14 +01001639 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1640 if (IS_ERR(at91_chip->regbase)) {
1641 ret = PTR_ERR(at91_chip->regbase);
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001642 goto err;
1643 }
1644
Sachin Kamat3c936002013-03-15 10:07:03 +05301645 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001646 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1647 at91_chip->pioc_virq = irq;
1648 at91_chip->pioc_idx = alias_idx;
1649
1650 at91_chip->clock = clk_get(&pdev->dev, NULL);
1651 if (IS_ERR(at91_chip->clock)) {
1652 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1653 goto err;
1654 }
1655
1656 if (clk_prepare(at91_chip->clock))
1657 goto clk_prep_err;
1658
1659 /* enable PIO controller's clock */
1660 if (clk_enable(at91_chip->clock)) {
1661 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1662 goto clk_err;
1663 }
1664
1665 at91_chip->chip = at91_gpio_template;
1666
1667 chip = &at91_chip->chip;
1668 chip->of_node = np;
1669 chip->label = dev_name(&pdev->dev);
1670 chip->dev = &pdev->dev;
1671 chip->owner = THIS_MODULE;
1672 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1673
1674 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1675 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1676 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1677 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1678 else
1679 chip->ngpio = ngpio;
1680 }
1681
Sachin Kamat3c936002013-03-15 10:07:03 +05301682 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1683 GFP_KERNEL);
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001684
1685 if (!names) {
1686 ret = -ENOMEM;
1687 goto clk_err;
1688 }
1689
1690 for (i = 0; i < chip->ngpio; i++)
1691 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1692
Sachin Kamat3c936002013-03-15 10:07:03 +05301693 chip->names = (const char *const *)names;
Jean-Christophe PLAGNIOL-VILLARD32b01a32012-11-07 00:33:34 +08001694
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001695 range = &at91_chip->range;
1696 range->name = chip->label;
1697 range->id = alias_idx;
1698 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1699
1700 range->npins = chip->ngpio;
1701 range->gc = chip;
1702
1703 ret = gpiochip_add(chip);
1704 if (ret)
1705 goto clk_err;
1706
1707 gpio_chips[alias_idx] = at91_chip;
1708 gpio_banks = max(gpio_banks, alias_idx + 1);
1709
1710 at91_gpio_probe_fixup();
1711
1712 at91_gpio_of_irq_setup(np, at91_chip);
1713
1714 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1715
1716 return 0;
1717
1718clk_err:
1719 clk_unprepare(at91_chip->clock);
1720clk_prep_err:
1721 clk_put(at91_chip->clock);
1722err:
1723 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1724
1725 return ret;
1726}
1727
1728static struct platform_driver at91_gpio_driver = {
1729 .driver = {
1730 .name = "gpio-at91",
1731 .owner = THIS_MODULE,
Sachin Kamat606fca92013-09-28 17:38:48 +05301732 .of_match_table = at91_gpio_of_match,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001733 },
1734 .probe = at91_gpio_probe,
1735};
1736
1737static struct platform_driver at91_pinctrl_driver = {
1738 .driver = {
1739 .name = "pinctrl-at91",
1740 .owner = THIS_MODULE,
Sachin Kamat606fca92013-09-28 17:38:48 +05301741 .of_match_table = at91_pinctrl_of_match,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001742 },
1743 .probe = at91_pinctrl_probe,
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -08001744 .remove = at91_pinctrl_remove,
Jean-Christophe PLAGNIOL-VILLARD6732ae52012-07-12 23:35:02 +08001745};
1746
1747static int __init at91_pinctrl_init(void)
1748{
1749 int ret;
1750
1751 ret = platform_driver_register(&at91_gpio_driver);
1752 if (ret)
1753 return ret;
1754 return platform_driver_register(&at91_pinctrl_driver);
1755}
1756arch_initcall(at91_pinctrl_init);
1757
1758static void __exit at91_pinctrl_exit(void)
1759{
1760 platform_driver_unregister(&at91_pinctrl_driver);
1761}
1762
1763module_exit(at91_pinctrl_exit);
1764MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1765MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1766MODULE_LICENSE("GPL v2");