Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * IOMMU API for ARM architected SMMU implementations. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 16 | * |
| 17 | * Copyright (C) 2013 ARM Limited |
| 18 | * |
| 19 | * Author: Will Deacon <will.deacon@arm.com> |
| 20 | * |
| 21 | * This driver currently supports: |
| 22 | * - SMMUv1 and v2 implementations |
| 23 | * - Stream-matching and stream-indexing |
| 24 | * - v7/v8 long-descriptor format |
| 25 | * - Non-secure access to the SMMU |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 26 | * - Context fault reporting |
| 27 | */ |
| 28 | |
| 29 | #define pr_fmt(fmt) "arm-smmu: " fmt |
| 30 | |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/err.h> |
| 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/io.h> |
| 36 | #include <linux/iommu.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 37 | #include <linux/module.h> |
| 38 | #include <linux/of.h> |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 39 | #include <linux/pci.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 40 | #include <linux/platform_device.h> |
| 41 | #include <linux/slab.h> |
| 42 | #include <linux/spinlock.h> |
| 43 | |
| 44 | #include <linux/amba/bus.h> |
| 45 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 46 | #include "io-pgtable.h" |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 47 | |
| 48 | /* Maximum number of stream IDs assigned to a single device */ |
Andreas Herrmann | 636e97b | 2014-01-30 18:18:08 +0000 | [diff] [blame] | 49 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 50 | |
| 51 | /* Maximum number of context banks per SMMU */ |
| 52 | #define ARM_SMMU_MAX_CBS 128 |
| 53 | |
| 54 | /* Maximum number of mapping groups per SMMU */ |
| 55 | #define ARM_SMMU_MAX_SMRS 128 |
| 56 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 57 | /* SMMU global address space */ |
| 58 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 59 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 60 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 61 | /* |
| 62 | * SMMU global address space with conditional offset to access secure |
| 63 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, |
| 64 | * nsGFSYNR0: 0x450) |
| 65 | */ |
| 66 | #define ARM_SMMU_GR0_NS(smmu) \ |
| 67 | ((smmu)->base + \ |
| 68 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ |
| 69 | ? 0x400 : 0)) |
| 70 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 71 | /* Configuration registers */ |
| 72 | #define ARM_SMMU_GR0_sCR0 0x0 |
| 73 | #define sCR0_CLIENTPD (1 << 0) |
| 74 | #define sCR0_GFRE (1 << 1) |
| 75 | #define sCR0_GFIE (1 << 2) |
| 76 | #define sCR0_GCFGFRE (1 << 4) |
| 77 | #define sCR0_GCFGFIE (1 << 5) |
| 78 | #define sCR0_USFCFG (1 << 10) |
| 79 | #define sCR0_VMIDPNE (1 << 11) |
| 80 | #define sCR0_PTM (1 << 12) |
| 81 | #define sCR0_FB (1 << 13) |
| 82 | #define sCR0_BSU_SHIFT 14 |
| 83 | #define sCR0_BSU_MASK 0x3 |
| 84 | |
| 85 | /* Identification registers */ |
| 86 | #define ARM_SMMU_GR0_ID0 0x20 |
| 87 | #define ARM_SMMU_GR0_ID1 0x24 |
| 88 | #define ARM_SMMU_GR0_ID2 0x28 |
| 89 | #define ARM_SMMU_GR0_ID3 0x2c |
| 90 | #define ARM_SMMU_GR0_ID4 0x30 |
| 91 | #define ARM_SMMU_GR0_ID5 0x34 |
| 92 | #define ARM_SMMU_GR0_ID6 0x38 |
| 93 | #define ARM_SMMU_GR0_ID7 0x3c |
| 94 | #define ARM_SMMU_GR0_sGFSR 0x48 |
| 95 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 |
| 96 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 |
| 97 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 98 | |
| 99 | #define ID0_S1TS (1 << 30) |
| 100 | #define ID0_S2TS (1 << 29) |
| 101 | #define ID0_NTS (1 << 28) |
| 102 | #define ID0_SMS (1 << 27) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 103 | #define ID0_CTTW (1 << 14) |
| 104 | #define ID0_NUMIRPT_SHIFT 16 |
| 105 | #define ID0_NUMIRPT_MASK 0xff |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 106 | #define ID0_NUMSIDB_SHIFT 9 |
| 107 | #define ID0_NUMSIDB_MASK 0xf |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 108 | #define ID0_NUMSMRG_SHIFT 0 |
| 109 | #define ID0_NUMSMRG_MASK 0xff |
| 110 | |
| 111 | #define ID1_PAGESIZE (1 << 31) |
| 112 | #define ID1_NUMPAGENDXB_SHIFT 28 |
| 113 | #define ID1_NUMPAGENDXB_MASK 7 |
| 114 | #define ID1_NUMS2CB_SHIFT 16 |
| 115 | #define ID1_NUMS2CB_MASK 0xff |
| 116 | #define ID1_NUMCB_SHIFT 0 |
| 117 | #define ID1_NUMCB_MASK 0xff |
| 118 | |
| 119 | #define ID2_OAS_SHIFT 4 |
| 120 | #define ID2_OAS_MASK 0xf |
| 121 | #define ID2_IAS_SHIFT 0 |
| 122 | #define ID2_IAS_MASK 0xf |
| 123 | #define ID2_UBS_SHIFT 8 |
| 124 | #define ID2_UBS_MASK 0xf |
| 125 | #define ID2_PTFS_4K (1 << 12) |
| 126 | #define ID2_PTFS_16K (1 << 13) |
| 127 | #define ID2_PTFS_64K (1 << 14) |
| 128 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 129 | /* Global TLB invalidation */ |
| 130 | #define ARM_SMMU_GR0_STLBIALL 0x60 |
| 131 | #define ARM_SMMU_GR0_TLBIVMID 0x64 |
| 132 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 |
| 133 | #define ARM_SMMU_GR0_TLBIALLH 0x6c |
| 134 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 |
| 135 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 |
| 136 | #define sTLBGSTATUS_GSACTIVE (1 << 0) |
| 137 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ |
| 138 | |
| 139 | /* Stream mapping registers */ |
| 140 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) |
| 141 | #define SMR_VALID (1 << 31) |
| 142 | #define SMR_MASK_SHIFT 16 |
| 143 | #define SMR_MASK_MASK 0x7fff |
| 144 | #define SMR_ID_SHIFT 0 |
| 145 | #define SMR_ID_MASK 0x7fff |
| 146 | |
| 147 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) |
| 148 | #define S2CR_CBNDX_SHIFT 0 |
| 149 | #define S2CR_CBNDX_MASK 0xff |
| 150 | #define S2CR_TYPE_SHIFT 16 |
| 151 | #define S2CR_TYPE_MASK 0x3 |
| 152 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) |
| 153 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) |
| 154 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) |
| 155 | |
| 156 | /* Context bank attribute registers */ |
| 157 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) |
| 158 | #define CBAR_VMID_SHIFT 0 |
| 159 | #define CBAR_VMID_MASK 0xff |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 160 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
| 161 | #define CBAR_S1_BPSHCFG_MASK 3 |
| 162 | #define CBAR_S1_BPSHCFG_NSH 3 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 163 | #define CBAR_S1_MEMATTR_SHIFT 12 |
| 164 | #define CBAR_S1_MEMATTR_MASK 0xf |
| 165 | #define CBAR_S1_MEMATTR_WB 0xf |
| 166 | #define CBAR_TYPE_SHIFT 16 |
| 167 | #define CBAR_TYPE_MASK 0x3 |
| 168 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) |
| 169 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) |
| 170 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) |
| 171 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) |
| 172 | #define CBAR_IRPTNDX_SHIFT 24 |
| 173 | #define CBAR_IRPTNDX_MASK 0xff |
| 174 | |
| 175 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) |
| 176 | #define CBA2R_RW64_32BIT (0 << 0) |
| 177 | #define CBA2R_RW64_64BIT (1 << 0) |
| 178 | |
| 179 | /* Translation context bank */ |
| 180 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 181 | #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 182 | |
| 183 | #define ARM_SMMU_CB_SCTLR 0x0 |
| 184 | #define ARM_SMMU_CB_RESUME 0x8 |
| 185 | #define ARM_SMMU_CB_TTBCR2 0x10 |
| 186 | #define ARM_SMMU_CB_TTBR0_LO 0x20 |
| 187 | #define ARM_SMMU_CB_TTBR0_HI 0x24 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 188 | #define ARM_SMMU_CB_TTBR1_LO 0x28 |
| 189 | #define ARM_SMMU_CB_TTBR1_HI 0x2c |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 190 | #define ARM_SMMU_CB_TTBCR 0x30 |
| 191 | #define ARM_SMMU_CB_S1_MAIR0 0x38 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 192 | #define ARM_SMMU_CB_S1_MAIR1 0x3c |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 193 | #define ARM_SMMU_CB_FSR 0x58 |
| 194 | #define ARM_SMMU_CB_FAR_LO 0x60 |
| 195 | #define ARM_SMMU_CB_FAR_HI 0x64 |
| 196 | #define ARM_SMMU_CB_FSYNR0 0x68 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 197 | #define ARM_SMMU_CB_S1_TLBIVA 0x600 |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 198 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 199 | #define ARM_SMMU_CB_S1_TLBIVAL 0x620 |
| 200 | #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 |
| 201 | #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 202 | |
| 203 | #define SCTLR_S1_ASIDPNE (1 << 12) |
| 204 | #define SCTLR_CFCFG (1 << 7) |
| 205 | #define SCTLR_CFIE (1 << 6) |
| 206 | #define SCTLR_CFRE (1 << 5) |
| 207 | #define SCTLR_E (1 << 4) |
| 208 | #define SCTLR_AFE (1 << 2) |
| 209 | #define SCTLR_TRE (1 << 1) |
| 210 | #define SCTLR_M (1 << 0) |
| 211 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) |
| 212 | |
| 213 | #define RESUME_RETRY (0 << 0) |
| 214 | #define RESUME_TERMINATE (1 << 0) |
| 215 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 216 | #define TTBCR2_SEP_SHIFT 15 |
| 217 | #define TTBCR2_SEP_MASK 0x7 |
| 218 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 219 | #define TTBCR2_ADDR_32 0 |
| 220 | #define TTBCR2_ADDR_36 1 |
| 221 | #define TTBCR2_ADDR_40 2 |
| 222 | #define TTBCR2_ADDR_42 3 |
| 223 | #define TTBCR2_ADDR_44 4 |
| 224 | #define TTBCR2_ADDR_48 5 |
| 225 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 226 | #define TTBRn_HI_ASID_SHIFT 16 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 227 | |
| 228 | #define FSR_MULTI (1 << 31) |
| 229 | #define FSR_SS (1 << 30) |
| 230 | #define FSR_UUT (1 << 8) |
| 231 | #define FSR_ASF (1 << 7) |
| 232 | #define FSR_TLBLKF (1 << 6) |
| 233 | #define FSR_TLBMCF (1 << 5) |
| 234 | #define FSR_EF (1 << 4) |
| 235 | #define FSR_PF (1 << 3) |
| 236 | #define FSR_AFF (1 << 2) |
| 237 | #define FSR_TF (1 << 1) |
| 238 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 239 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
| 240 | FSR_TLBMCF | FSR_TLBLKF) |
| 241 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 242 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 243 | |
| 244 | #define FSYNR0_WNR (1 << 4) |
| 245 | |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 246 | static int force_stage; |
| 247 | module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); |
| 248 | MODULE_PARM_DESC(force_stage, |
| 249 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); |
| 250 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 251 | enum arm_smmu_arch_version { |
| 252 | ARM_SMMU_V1 = 1, |
| 253 | ARM_SMMU_V2, |
| 254 | }; |
| 255 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 256 | struct arm_smmu_smr { |
| 257 | u8 idx; |
| 258 | u16 mask; |
| 259 | u16 id; |
| 260 | }; |
| 261 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 262 | struct arm_smmu_master_cfg { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 263 | int num_streamids; |
| 264 | u16 streamids[MAX_MASTER_STREAMIDS]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 265 | struct arm_smmu_smr *smrs; |
| 266 | }; |
| 267 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 268 | struct arm_smmu_master { |
| 269 | struct device_node *of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 270 | struct rb_node node; |
| 271 | struct arm_smmu_master_cfg cfg; |
| 272 | }; |
| 273 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 274 | struct arm_smmu_device { |
| 275 | struct device *dev; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 276 | |
| 277 | void __iomem *base; |
| 278 | unsigned long size; |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 279 | unsigned long pgshift; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 280 | |
| 281 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) |
| 282 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) |
| 283 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) |
| 284 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) |
| 285 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) |
| 286 | u32 features; |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 287 | |
| 288 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) |
| 289 | u32 options; |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 290 | enum arm_smmu_arch_version version; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 291 | |
| 292 | u32 num_context_banks; |
| 293 | u32 num_s2_context_banks; |
| 294 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); |
| 295 | atomic_t irptndx; |
| 296 | |
| 297 | u32 num_mapping_groups; |
| 298 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); |
| 299 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 300 | unsigned long va_size; |
| 301 | unsigned long ipa_size; |
| 302 | unsigned long pa_size; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 303 | |
| 304 | u32 num_global_irqs; |
| 305 | u32 num_context_irqs; |
| 306 | unsigned int *irqs; |
| 307 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 308 | struct list_head list; |
| 309 | struct rb_root masters; |
| 310 | }; |
| 311 | |
| 312 | struct arm_smmu_cfg { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 313 | u8 cbndx; |
| 314 | u8 irptndx; |
| 315 | u32 cbar; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 316 | }; |
Dan Carpenter | faea13b7 | 2013-08-21 09:33:30 +0100 | [diff] [blame] | 317 | #define INVALID_IRPTNDX 0xff |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 318 | |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 319 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
| 320 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) |
| 321 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 322 | enum arm_smmu_domain_stage { |
| 323 | ARM_SMMU_DOMAIN_S1 = 0, |
| 324 | ARM_SMMU_DOMAIN_S2, |
| 325 | ARM_SMMU_DOMAIN_NESTED, |
| 326 | }; |
| 327 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 328 | struct arm_smmu_domain { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 329 | struct arm_smmu_device *smmu; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 330 | struct io_pgtable_ops *pgtbl_ops; |
| 331 | spinlock_t pgtbl_lock; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 332 | struct arm_smmu_cfg cfg; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 333 | enum arm_smmu_domain_stage stage; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 334 | struct mutex init_mutex; /* Protects smmu pointer */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 335 | }; |
| 336 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 337 | static struct iommu_ops arm_smmu_ops; |
| 338 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 339 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); |
| 340 | static LIST_HEAD(arm_smmu_devices); |
| 341 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 342 | struct arm_smmu_option_prop { |
| 343 | u32 opt; |
| 344 | const char *prop; |
| 345 | }; |
| 346 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 347 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 348 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
| 349 | { 0, NULL}, |
| 350 | }; |
| 351 | |
| 352 | static void parse_driver_options(struct arm_smmu_device *smmu) |
| 353 | { |
| 354 | int i = 0; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 355 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 356 | do { |
| 357 | if (of_property_read_bool(smmu->dev->of_node, |
| 358 | arm_smmu_options[i].prop)) { |
| 359 | smmu->options |= arm_smmu_options[i].opt; |
| 360 | dev_notice(smmu->dev, "option %s\n", |
| 361 | arm_smmu_options[i].prop); |
| 362 | } |
| 363 | } while (arm_smmu_options[++i].opt); |
| 364 | } |
| 365 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 366 | static struct device_node *dev_get_dev_node(struct device *dev) |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 367 | { |
| 368 | if (dev_is_pci(dev)) { |
| 369 | struct pci_bus *bus = to_pci_dev(dev)->bus; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 370 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 371 | while (!pci_is_root_bus(bus)) |
| 372 | bus = bus->parent; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 373 | return bus->bridge->parent->of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 374 | } |
| 375 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 376 | return dev->of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 377 | } |
| 378 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 379 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
| 380 | struct device_node *dev_node) |
| 381 | { |
| 382 | struct rb_node *node = smmu->masters.rb_node; |
| 383 | |
| 384 | while (node) { |
| 385 | struct arm_smmu_master *master; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 386 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 387 | master = container_of(node, struct arm_smmu_master, node); |
| 388 | |
| 389 | if (dev_node < master->of_node) |
| 390 | node = node->rb_left; |
| 391 | else if (dev_node > master->of_node) |
| 392 | node = node->rb_right; |
| 393 | else |
| 394 | return master; |
| 395 | } |
| 396 | |
| 397 | return NULL; |
| 398 | } |
| 399 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 400 | static struct arm_smmu_master_cfg * |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 401 | find_smmu_master_cfg(struct device *dev) |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 402 | { |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 403 | struct arm_smmu_master_cfg *cfg = NULL; |
| 404 | struct iommu_group *group = iommu_group_get(dev); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 405 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 406 | if (group) { |
| 407 | cfg = iommu_group_get_iommudata(group); |
| 408 | iommu_group_put(group); |
| 409 | } |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 410 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 411 | return cfg; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 412 | } |
| 413 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 414 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
| 415 | struct arm_smmu_master *master) |
| 416 | { |
| 417 | struct rb_node **new, *parent; |
| 418 | |
| 419 | new = &smmu->masters.rb_node; |
| 420 | parent = NULL; |
| 421 | while (*new) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 422 | struct arm_smmu_master *this |
| 423 | = container_of(*new, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 424 | |
| 425 | parent = *new; |
| 426 | if (master->of_node < this->of_node) |
| 427 | new = &((*new)->rb_left); |
| 428 | else if (master->of_node > this->of_node) |
| 429 | new = &((*new)->rb_right); |
| 430 | else |
| 431 | return -EEXIST; |
| 432 | } |
| 433 | |
| 434 | rb_link_node(&master->node, parent, new); |
| 435 | rb_insert_color(&master->node, &smmu->masters); |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | static int register_smmu_master(struct arm_smmu_device *smmu, |
| 440 | struct device *dev, |
| 441 | struct of_phandle_args *masterspec) |
| 442 | { |
| 443 | int i; |
| 444 | struct arm_smmu_master *master; |
| 445 | |
| 446 | master = find_smmu_master(smmu, masterspec->np); |
| 447 | if (master) { |
| 448 | dev_err(dev, |
| 449 | "rejecting multiple registrations for master device %s\n", |
| 450 | masterspec->np->name); |
| 451 | return -EBUSY; |
| 452 | } |
| 453 | |
| 454 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { |
| 455 | dev_err(dev, |
| 456 | "reached maximum number (%d) of stream IDs for master device %s\n", |
| 457 | MAX_MASTER_STREAMIDS, masterspec->np->name); |
| 458 | return -ENOSPC; |
| 459 | } |
| 460 | |
| 461 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); |
| 462 | if (!master) |
| 463 | return -ENOMEM; |
| 464 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 465 | master->of_node = masterspec->np; |
| 466 | master->cfg.num_streamids = masterspec->args_count; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 467 | |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 468 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
| 469 | u16 streamid = masterspec->args[i]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 470 | |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 471 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
| 472 | (streamid >= smmu->num_mapping_groups)) { |
| 473 | dev_err(dev, |
| 474 | "stream ID for master device %s greater than maximum allowed (%d)\n", |
| 475 | masterspec->np->name, smmu->num_mapping_groups); |
| 476 | return -ERANGE; |
| 477 | } |
| 478 | master->cfg.streamids[i] = streamid; |
| 479 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 480 | return insert_smmu_master(smmu, master); |
| 481 | } |
| 482 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 483 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 484 | { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 485 | struct arm_smmu_device *smmu; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 486 | struct arm_smmu_master *master = NULL; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 487 | struct device_node *dev_node = dev_get_dev_node(dev); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 488 | |
| 489 | spin_lock(&arm_smmu_devices_lock); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 490 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 491 | master = find_smmu_master(smmu, dev_node); |
| 492 | if (master) |
| 493 | break; |
| 494 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 495 | spin_unlock(&arm_smmu_devices_lock); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 496 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 497 | return master ? smmu : NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) |
| 501 | { |
| 502 | int idx; |
| 503 | |
| 504 | do { |
| 505 | idx = find_next_zero_bit(map, end, start); |
| 506 | if (idx == end) |
| 507 | return -ENOSPC; |
| 508 | } while (test_and_set_bit(idx, map)); |
| 509 | |
| 510 | return idx; |
| 511 | } |
| 512 | |
| 513 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) |
| 514 | { |
| 515 | clear_bit(idx, map); |
| 516 | } |
| 517 | |
| 518 | /* Wait for any pending TLB invalidations to complete */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 519 | static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 520 | { |
| 521 | int count = 0; |
| 522 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 523 | |
| 524 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); |
| 525 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) |
| 526 | & sTLBGSTATUS_GSACTIVE) { |
| 527 | cpu_relax(); |
| 528 | if (++count == TLB_LOOP_TIMEOUT) { |
| 529 | dev_err_ratelimited(smmu->dev, |
| 530 | "TLB sync timed out -- SMMU may be deadlocked\n"); |
| 531 | return; |
| 532 | } |
| 533 | udelay(1); |
| 534 | } |
| 535 | } |
| 536 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 537 | static void arm_smmu_tlb_sync(void *cookie) |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 538 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 539 | struct arm_smmu_domain *smmu_domain = cookie; |
| 540 | __arm_smmu_tlb_sync(smmu_domain->smmu); |
| 541 | } |
| 542 | |
| 543 | static void arm_smmu_tlb_inv_context(void *cookie) |
| 544 | { |
| 545 | struct arm_smmu_domain *smmu_domain = cookie; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 546 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 547 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 548 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 549 | void __iomem *base; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 550 | |
| 551 | if (stage1) { |
| 552 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 553 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
| 554 | base + ARM_SMMU_CB_S1_TLBIASID); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 555 | } else { |
| 556 | base = ARM_SMMU_GR0(smmu); |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 557 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
| 558 | base + ARM_SMMU_GR0_TLBIVMID); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 559 | } |
| 560 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 561 | __arm_smmu_tlb_sync(smmu); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 562 | } |
| 563 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 564 | static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, |
| 565 | bool leaf, void *cookie) |
| 566 | { |
| 567 | struct arm_smmu_domain *smmu_domain = cookie; |
| 568 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 569 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 570 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 571 | void __iomem *reg; |
| 572 | |
| 573 | if (stage1) { |
| 574 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 575 | reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; |
| 576 | |
| 577 | if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { |
| 578 | iova &= ~12UL; |
| 579 | iova |= ARM_SMMU_CB_ASID(cfg); |
| 580 | writel_relaxed(iova, reg); |
| 581 | #ifdef CONFIG_64BIT |
| 582 | } else { |
| 583 | iova >>= 12; |
| 584 | iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; |
| 585 | writeq_relaxed(iova, reg); |
| 586 | #endif |
| 587 | } |
| 588 | #ifdef CONFIG_64BIT |
| 589 | } else if (smmu->version == ARM_SMMU_V2) { |
| 590 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 591 | reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L : |
| 592 | ARM_SMMU_CB_S2_TLBIIPAS2; |
| 593 | writeq_relaxed(iova >> 12, reg); |
| 594 | #endif |
| 595 | } else { |
| 596 | reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; |
| 597 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie) |
| 602 | { |
| 603 | struct arm_smmu_domain *smmu_domain = cookie; |
| 604 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 605 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; |
| 606 | |
| 607 | |
| 608 | /* Ensure new page tables are visible to the hardware walker */ |
| 609 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { |
| 610 | dsb(ishst); |
| 611 | } else { |
| 612 | /* |
| 613 | * If the SMMU can't walk tables in the CPU caches, treat them |
| 614 | * like non-coherent DMA since we need to flush the new entries |
| 615 | * all the way out to memory. There's no possibility of |
| 616 | * recursion here as the SMMU table walker will not be wired |
| 617 | * through another SMMU. |
| 618 | */ |
| 619 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, |
| 620 | DMA_TO_DEVICE); |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | static struct iommu_gather_ops arm_smmu_gather_ops = { |
| 625 | .tlb_flush_all = arm_smmu_tlb_inv_context, |
| 626 | .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, |
| 627 | .tlb_sync = arm_smmu_tlb_sync, |
| 628 | .flush_pgtable = arm_smmu_flush_pgtable, |
| 629 | }; |
| 630 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 631 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
| 632 | { |
| 633 | int flags, ret; |
| 634 | u32 fsr, far, fsynr, resume; |
| 635 | unsigned long iova; |
| 636 | struct iommu_domain *domain = dev; |
| 637 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 638 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 639 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 640 | void __iomem *cb_base; |
| 641 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 642 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 643 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
| 644 | |
| 645 | if (!(fsr & FSR_FAULT)) |
| 646 | return IRQ_NONE; |
| 647 | |
| 648 | if (fsr & FSR_IGN) |
| 649 | dev_err_ratelimited(smmu->dev, |
Hans Wennborg | 70c9a7d | 2014-08-06 05:42:01 +0100 | [diff] [blame] | 650 | "Unexpected context fault (fsr 0x%x)\n", |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 651 | fsr); |
| 652 | |
| 653 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); |
| 654 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; |
| 655 | |
| 656 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); |
| 657 | iova = far; |
| 658 | #ifdef CONFIG_64BIT |
| 659 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); |
| 660 | iova |= ((unsigned long)far << 32); |
| 661 | #endif |
| 662 | |
| 663 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { |
| 664 | ret = IRQ_HANDLED; |
| 665 | resume = RESUME_RETRY; |
| 666 | } else { |
Andreas Herrmann | 2ef0f03 | 2013-10-01 13:39:08 +0100 | [diff] [blame] | 667 | dev_err_ratelimited(smmu->dev, |
| 668 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 669 | iova, fsynr, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 670 | ret = IRQ_NONE; |
| 671 | resume = RESUME_TERMINATE; |
| 672 | } |
| 673 | |
| 674 | /* Clear the faulting FSR */ |
| 675 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); |
| 676 | |
| 677 | /* Retry or terminate any stalled transactions */ |
| 678 | if (fsr & FSR_SS) |
| 679 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); |
| 680 | |
| 681 | return ret; |
| 682 | } |
| 683 | |
| 684 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) |
| 685 | { |
| 686 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; |
| 687 | struct arm_smmu_device *smmu = dev; |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 688 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 689 | |
| 690 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); |
| 691 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); |
| 692 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); |
| 693 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); |
| 694 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 695 | if (!gfsr) |
| 696 | return IRQ_NONE; |
| 697 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 698 | dev_err_ratelimited(smmu->dev, |
| 699 | "Unexpected global fault, this could be serious\n"); |
| 700 | dev_err_ratelimited(smmu->dev, |
| 701 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", |
| 702 | gfsr, gfsynr0, gfsynr1, gfsynr2); |
| 703 | |
| 704 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 705 | return IRQ_HANDLED; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 706 | } |
| 707 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 708 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, |
| 709 | struct io_pgtable_cfg *pgtbl_cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 710 | { |
| 711 | u32 reg; |
| 712 | bool stage1; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 713 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 714 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 715 | void __iomem *cb_base, *gr0_base, *gr1_base; |
| 716 | |
| 717 | gr0_base = ARM_SMMU_GR0(smmu); |
| 718 | gr1_base = ARM_SMMU_GR1(smmu); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 719 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 720 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 721 | |
| 722 | /* CBAR */ |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 723 | reg = cfg->cbar; |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 724 | if (smmu->version == ARM_SMMU_V1) |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 725 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 726 | |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 727 | /* |
| 728 | * Use the weakest shareability/memory types, so they are |
| 729 | * overridden by the ttbcr/pte. |
| 730 | */ |
| 731 | if (stage1) { |
| 732 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | |
| 733 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); |
| 734 | } else { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 735 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 736 | } |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 737 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 738 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 739 | if (smmu->version > ARM_SMMU_V1) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 740 | /* CBA2R */ |
| 741 | #ifdef CONFIG_64BIT |
| 742 | reg = CBA2R_RW64_64BIT; |
| 743 | #else |
| 744 | reg = CBA2R_RW64_32BIT; |
| 745 | #endif |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 746 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 747 | } |
| 748 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 749 | /* TTBRs */ |
| 750 | if (stage1) { |
| 751 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; |
| 752 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
| 753 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 754 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 755 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 756 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 757 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; |
| 758 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO); |
| 759 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32; |
| 760 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
| 761 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI); |
| 762 | } else { |
| 763 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; |
| 764 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
| 765 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32; |
| 766 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
| 767 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 768 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 769 | /* TTBCR */ |
| 770 | if (stage1) { |
| 771 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; |
| 772 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
| 773 | if (smmu->version > ARM_SMMU_V1) { |
| 774 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; |
| 775 | switch (smmu->va_size) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 776 | case 32: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 777 | reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 778 | break; |
| 779 | case 36: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 780 | reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 781 | break; |
| 782 | case 40: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 783 | reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 784 | break; |
| 785 | case 42: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 786 | reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 787 | break; |
| 788 | case 44: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 789 | reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 790 | break; |
| 791 | case 48: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 792 | reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 793 | break; |
| 794 | } |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 795 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 796 | } |
| 797 | } else { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 798 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; |
| 799 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 800 | } |
| 801 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 802 | /* MAIRs (stage-1 only) */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 803 | if (stage1) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 804 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 805 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 806 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; |
| 807 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 808 | } |
| 809 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 810 | /* SCTLR */ |
| 811 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; |
| 812 | if (stage1) |
| 813 | reg |= SCTLR_S1_ASIDPNE; |
| 814 | #ifdef __BIG_ENDIAN |
| 815 | reg |= SCTLR_E; |
| 816 | #endif |
Will Deacon | 2572484 | 2013-08-21 13:49:53 +0100 | [diff] [blame] | 817 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 821 | struct arm_smmu_device *smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 822 | { |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 823 | int irq, start, ret = 0; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 824 | unsigned long ias, oas; |
| 825 | struct io_pgtable_ops *pgtbl_ops; |
| 826 | struct io_pgtable_cfg pgtbl_cfg; |
| 827 | enum io_pgtable_fmt fmt; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 828 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 829 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 830 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 831 | mutex_lock(&smmu_domain->init_mutex); |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 832 | if (smmu_domain->smmu) |
| 833 | goto out_unlock; |
| 834 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 835 | /* |
| 836 | * Mapping the requested stage onto what we support is surprisingly |
| 837 | * complicated, mainly because the spec allows S1+S2 SMMUs without |
| 838 | * support for nested translation. That means we end up with the |
| 839 | * following table: |
| 840 | * |
| 841 | * Requested Supported Actual |
| 842 | * S1 N S1 |
| 843 | * S1 S1+S2 S1 |
| 844 | * S1 S2 S2 |
| 845 | * S1 S1 S1 |
| 846 | * N N N |
| 847 | * N S1+S2 S2 |
| 848 | * N S2 S2 |
| 849 | * N S1 S1 |
| 850 | * |
| 851 | * Note that you can't actually request stage-2 mappings. |
| 852 | */ |
| 853 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) |
| 854 | smmu_domain->stage = ARM_SMMU_DOMAIN_S2; |
| 855 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) |
| 856 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; |
| 857 | |
| 858 | switch (smmu_domain->stage) { |
| 859 | case ARM_SMMU_DOMAIN_S1: |
| 860 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
| 861 | start = smmu->num_s2_context_banks; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 862 | ias = smmu->va_size; |
| 863 | oas = smmu->ipa_size; |
| 864 | if (IS_ENABLED(CONFIG_64BIT)) |
| 865 | fmt = ARM_64_LPAE_S1; |
| 866 | else |
| 867 | fmt = ARM_32_LPAE_S1; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 868 | break; |
| 869 | case ARM_SMMU_DOMAIN_NESTED: |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 870 | /* |
| 871 | * We will likely want to change this if/when KVM gets |
| 872 | * involved. |
| 873 | */ |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 874 | case ARM_SMMU_DOMAIN_S2: |
Will Deacon | 9c5c92e | 2014-06-25 12:12:41 +0100 | [diff] [blame] | 875 | cfg->cbar = CBAR_TYPE_S2_TRANS; |
| 876 | start = 0; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 877 | ias = smmu->ipa_size; |
| 878 | oas = smmu->pa_size; |
| 879 | if (IS_ENABLED(CONFIG_64BIT)) |
| 880 | fmt = ARM_64_LPAE_S2; |
| 881 | else |
| 882 | fmt = ARM_32_LPAE_S2; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 883 | break; |
| 884 | default: |
| 885 | ret = -EINVAL; |
| 886 | goto out_unlock; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 887 | } |
| 888 | |
| 889 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, |
| 890 | smmu->num_context_banks); |
| 891 | if (IS_ERR_VALUE(ret)) |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 892 | goto out_unlock; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 893 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 894 | cfg->cbndx = ret; |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 895 | if (smmu->version == ARM_SMMU_V1) { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 896 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
| 897 | cfg->irptndx %= smmu->num_context_irqs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 898 | } else { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 899 | cfg->irptndx = cfg->cbndx; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 900 | } |
| 901 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 902 | pgtbl_cfg = (struct io_pgtable_cfg) { |
| 903 | .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, |
| 904 | .ias = ias, |
| 905 | .oas = oas, |
| 906 | .tlb = &arm_smmu_gather_ops, |
| 907 | }; |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 908 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 909 | smmu_domain->smmu = smmu; |
| 910 | pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); |
| 911 | if (!pgtbl_ops) { |
| 912 | ret = -ENOMEM; |
| 913 | goto out_clear_smmu; |
| 914 | } |
| 915 | |
| 916 | /* Update our support page sizes to reflect the page table format */ |
| 917 | arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; |
| 918 | |
| 919 | /* Initialise the context bank with our page table cfg */ |
| 920 | arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); |
| 921 | |
| 922 | /* |
| 923 | * Request context fault interrupt. Do this last to avoid the |
| 924 | * handler seeing a half-initialised domain state. |
| 925 | */ |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 926 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 927 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
| 928 | "arm-smmu-context-fault", domain); |
| 929 | if (IS_ERR_VALUE(ret)) { |
| 930 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 931 | cfg->irptndx, irq); |
| 932 | cfg->irptndx = INVALID_IRPTNDX; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 933 | } |
| 934 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 935 | mutex_unlock(&smmu_domain->init_mutex); |
| 936 | |
| 937 | /* Publish page table ops for map/unmap */ |
| 938 | smmu_domain->pgtbl_ops = pgtbl_ops; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 939 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 940 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 941 | out_clear_smmu: |
| 942 | smmu_domain->smmu = NULL; |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 943 | out_unlock: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 944 | mutex_unlock(&smmu_domain->init_mutex); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 945 | return ret; |
| 946 | } |
| 947 | |
| 948 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) |
| 949 | { |
| 950 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 951 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 952 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 953 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 954 | int irq; |
| 955 | |
| 956 | if (!smmu) |
| 957 | return; |
| 958 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 959 | /* |
| 960 | * Disable the context bank and free the page tables before freeing |
| 961 | * it. |
| 962 | */ |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 963 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 964 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 965 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 966 | if (cfg->irptndx != INVALID_IRPTNDX) { |
| 967 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 968 | free_irq(irq, domain); |
| 969 | } |
| 970 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 971 | if (smmu_domain->pgtbl_ops) |
| 972 | free_io_pgtable_ops(smmu_domain->pgtbl_ops); |
| 973 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 974 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 975 | } |
| 976 | |
| 977 | static int arm_smmu_domain_init(struct iommu_domain *domain) |
| 978 | { |
| 979 | struct arm_smmu_domain *smmu_domain; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 980 | |
| 981 | /* |
| 982 | * Allocate the domain and initialise some of its data structures. |
| 983 | * We can't really do anything meaningful until we've added a |
| 984 | * master. |
| 985 | */ |
| 986 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); |
| 987 | if (!smmu_domain) |
| 988 | return -ENOMEM; |
| 989 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 990 | mutex_init(&smmu_domain->init_mutex); |
| 991 | spin_lock_init(&smmu_domain->pgtbl_lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 992 | domain->priv = smmu_domain; |
| 993 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 994 | } |
| 995 | |
| 996 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) |
| 997 | { |
| 998 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 999 | |
| 1000 | /* |
| 1001 | * Free the domain resources. We assume that all devices have |
| 1002 | * already been detached. |
| 1003 | */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1004 | arm_smmu_destroy_domain_context(domain); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1005 | kfree(smmu_domain); |
| 1006 | } |
| 1007 | |
| 1008 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1009 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1010 | { |
| 1011 | int i; |
| 1012 | struct arm_smmu_smr *smrs; |
| 1013 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1014 | |
| 1015 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) |
| 1016 | return 0; |
| 1017 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1018 | if (cfg->smrs) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1019 | return -EEXIST; |
| 1020 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1021 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1022 | if (!smrs) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1023 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
| 1024 | cfg->num_streamids); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1025 | return -ENOMEM; |
| 1026 | } |
| 1027 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1028 | /* Allocate the SMRs on the SMMU */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1029 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1030 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
| 1031 | smmu->num_mapping_groups); |
| 1032 | if (IS_ERR_VALUE(idx)) { |
| 1033 | dev_err(smmu->dev, "failed to allocate free SMR\n"); |
| 1034 | goto err_free_smrs; |
| 1035 | } |
| 1036 | |
| 1037 | smrs[i] = (struct arm_smmu_smr) { |
| 1038 | .idx = idx, |
| 1039 | .mask = 0, /* We don't currently share SMRs */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1040 | .id = cfg->streamids[i], |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1041 | }; |
| 1042 | } |
| 1043 | |
| 1044 | /* It worked! Now, poke the actual hardware */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1045 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1046 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
| 1047 | smrs[i].mask << SMR_MASK_SHIFT; |
| 1048 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); |
| 1049 | } |
| 1050 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1051 | cfg->smrs = smrs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1052 | return 0; |
| 1053 | |
| 1054 | err_free_smrs: |
| 1055 | while (--i >= 0) |
| 1056 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); |
| 1057 | kfree(smrs); |
| 1058 | return -ENOSPC; |
| 1059 | } |
| 1060 | |
| 1061 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1062 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1063 | { |
| 1064 | int i; |
| 1065 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1066 | struct arm_smmu_smr *smrs = cfg->smrs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1067 | |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1068 | if (!smrs) |
| 1069 | return; |
| 1070 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1071 | /* Invalidate the SMRs before freeing back to the allocator */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1072 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1073 | u8 idx = smrs[i].idx; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1074 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1075 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
| 1076 | __arm_smmu_free_bitmap(smmu->smr_map, idx); |
| 1077 | } |
| 1078 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1079 | cfg->smrs = NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1080 | kfree(smrs); |
| 1081 | } |
| 1082 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1083 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1084 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1085 | { |
| 1086 | int i, ret; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1087 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1088 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1089 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1090 | /* Devices in an IOMMU group may already be configured */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1091 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1092 | if (ret) |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1093 | return ret == -EEXIST ? 0 : ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1094 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1095 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1096 | u32 idx, s2cr; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1097 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1098 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
Kefeng Wang | 6069d23 | 2014-04-18 10:20:48 +0800 | [diff] [blame] | 1099 | s2cr = S2CR_TYPE_TRANS | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1100 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1101 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
| 1102 | } |
| 1103 | |
| 1104 | return 0; |
| 1105 | } |
| 1106 | |
| 1107 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1108 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1109 | { |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1110 | int i; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1111 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1112 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1113 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1114 | /* An IOMMU group is torn down by the first device to be removed */ |
| 1115 | if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) |
| 1116 | return; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1117 | |
| 1118 | /* |
| 1119 | * We *must* clear the S2CR first, because freeing the SMR means |
| 1120 | * that it can be re-allocated immediately. |
| 1121 | */ |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1122 | for (i = 0; i < cfg->num_streamids; ++i) { |
| 1123 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
| 1124 | |
| 1125 | writel_relaxed(S2CR_TYPE_BYPASS, |
| 1126 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
| 1127 | } |
| 1128 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1129 | arm_smmu_master_free_smrs(smmu, cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1130 | } |
| 1131 | |
| 1132 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) |
| 1133 | { |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1134 | int ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1135 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1136 | struct arm_smmu_device *smmu; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1137 | struct arm_smmu_master_cfg *cfg; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1138 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1139 | smmu = find_smmu_for_device(dev); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1140 | if (!smmu) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1141 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
| 1142 | return -ENXIO; |
| 1143 | } |
| 1144 | |
Will Deacon | 844e35b | 2014-07-17 11:23:51 +0100 | [diff] [blame] | 1145 | if (dev->archdata.iommu) { |
| 1146 | dev_err(dev, "already attached to IOMMU domain\n"); |
| 1147 | return -EEXIST; |
| 1148 | } |
| 1149 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1150 | /* Ensure that the domain is finalised */ |
| 1151 | ret = arm_smmu_init_domain_context(domain, smmu); |
| 1152 | if (IS_ERR_VALUE(ret)) |
| 1153 | return ret; |
| 1154 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1155 | /* |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1156 | * Sanity check the domain. We don't support domains across |
| 1157 | * different SMMUs. |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1158 | */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1159 | if (smmu_domain->smmu != smmu) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1160 | dev_err(dev, |
| 1161 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1162 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
| 1163 | return -EINVAL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1164 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1165 | |
| 1166 | /* Looks ok, so add the device to the domain */ |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1167 | cfg = find_smmu_master_cfg(dev); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1168 | if (!cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1169 | return -ENODEV; |
| 1170 | |
Will Deacon | 844e35b | 2014-07-17 11:23:51 +0100 | [diff] [blame] | 1171 | ret = arm_smmu_domain_add_master(smmu_domain, cfg); |
| 1172 | if (!ret) |
| 1173 | dev->archdata.iommu = domain; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1174 | return ret; |
| 1175 | } |
| 1176 | |
| 1177 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
| 1178 | { |
| 1179 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1180 | struct arm_smmu_master_cfg *cfg; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1181 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1182 | cfg = find_smmu_master_cfg(dev); |
Will Deacon | 844e35b | 2014-07-17 11:23:51 +0100 | [diff] [blame] | 1183 | if (!cfg) |
| 1184 | return; |
| 1185 | |
| 1186 | dev->archdata.iommu = NULL; |
| 1187 | arm_smmu_domain_remove_master(smmu_domain, cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1188 | } |
| 1189 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1190 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, |
Will Deacon | b410aed | 2014-02-20 16:31:06 +0000 | [diff] [blame] | 1191 | phys_addr_t paddr, size_t size, int prot) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1192 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1193 | int ret; |
| 1194 | unsigned long flags; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1195 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1196 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1197 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1198 | if (!ops) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1199 | return -ENODEV; |
| 1200 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1201 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 1202 | ret = ops->map(ops, iova, paddr, size, prot); |
| 1203 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
| 1204 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1205 | } |
| 1206 | |
| 1207 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 1208 | size_t size) |
| 1209 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1210 | size_t ret; |
| 1211 | unsigned long flags; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1212 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1213 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1214 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1215 | if (!ops) |
| 1216 | return 0; |
| 1217 | |
| 1218 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 1219 | ret = ops->unmap(ops, iova, size); |
| 1220 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
| 1221 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1222 | } |
| 1223 | |
| 1224 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, |
| 1225 | dma_addr_t iova) |
| 1226 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1227 | phys_addr_t ret; |
| 1228 | unsigned long flags; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1229 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1230 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1231 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1232 | if (!ops) |
Will Deacon | a44a9791 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1233 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1234 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1235 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 1236 | ret = ops->iova_to_phys(ops, iova); |
| 1237 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
| 1238 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1239 | } |
| 1240 | |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 1241 | static bool arm_smmu_capable(enum iommu_cap cap) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1242 | { |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 1243 | switch (cap) { |
| 1244 | case IOMMU_CAP_CACHE_COHERENCY: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 1245 | /* |
| 1246 | * Return true here as the SMMU can always send out coherent |
| 1247 | * requests. |
| 1248 | */ |
| 1249 | return true; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 1250 | case IOMMU_CAP_INTR_REMAP: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 1251 | return true; /* MSIs are just memory writes */ |
Antonios Motakis | 0029a8d | 2014-10-13 14:06:18 +0100 | [diff] [blame] | 1252 | case IOMMU_CAP_NOEXEC: |
| 1253 | return true; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 1254 | default: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 1255 | return false; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 1256 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1257 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1258 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1259 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
| 1260 | { |
| 1261 | *((u16 *)data) = alias; |
| 1262 | return 0; /* Continue walking */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1263 | } |
| 1264 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1265 | static void __arm_smmu_release_pci_iommudata(void *data) |
| 1266 | { |
| 1267 | kfree(data); |
| 1268 | } |
| 1269 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1270 | static int arm_smmu_add_device(struct device *dev) |
| 1271 | { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1272 | struct arm_smmu_device *smmu; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1273 | struct arm_smmu_master_cfg *cfg; |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1274 | struct iommu_group *group; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1275 | void (*releasefn)(void *) = NULL; |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1276 | int ret; |
| 1277 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1278 | smmu = find_smmu_for_device(dev); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1279 | if (!smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1280 | return -ENODEV; |
| 1281 | |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1282 | group = iommu_group_alloc(); |
| 1283 | if (IS_ERR(group)) { |
| 1284 | dev_err(dev, "Failed to allocate IOMMU group\n"); |
| 1285 | return PTR_ERR(group); |
| 1286 | } |
| 1287 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1288 | if (dev_is_pci(dev)) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1289 | struct pci_dev *pdev = to_pci_dev(dev); |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1290 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1291 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); |
| 1292 | if (!cfg) { |
| 1293 | ret = -ENOMEM; |
| 1294 | goto out_put_group; |
| 1295 | } |
| 1296 | |
| 1297 | cfg->num_streamids = 1; |
| 1298 | /* |
| 1299 | * Assume Stream ID == Requester ID for now. |
| 1300 | * We need a way to describe the ID mappings in FDT. |
| 1301 | */ |
| 1302 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, |
| 1303 | &cfg->streamids[0]); |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1304 | releasefn = __arm_smmu_release_pci_iommudata; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1305 | } else { |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1306 | struct arm_smmu_master *master; |
| 1307 | |
| 1308 | master = find_smmu_master(smmu, dev->of_node); |
| 1309 | if (!master) { |
| 1310 | ret = -ENODEV; |
| 1311 | goto out_put_group; |
| 1312 | } |
| 1313 | |
| 1314 | cfg = &master->cfg; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1315 | } |
| 1316 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1317 | iommu_group_set_iommudata(group, cfg, releasefn); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1318 | ret = iommu_group_add_device(group, dev); |
| 1319 | |
| 1320 | out_put_group: |
| 1321 | iommu_group_put(group); |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1322 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | static void arm_smmu_remove_device(struct device *dev) |
| 1326 | { |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 1327 | iommu_group_remove_device(dev); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1328 | } |
| 1329 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1330 | static int arm_smmu_domain_get_attr(struct iommu_domain *domain, |
| 1331 | enum iommu_attr attr, void *data) |
| 1332 | { |
| 1333 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1334 | |
| 1335 | switch (attr) { |
| 1336 | case DOMAIN_ATTR_NESTING: |
| 1337 | *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); |
| 1338 | return 0; |
| 1339 | default: |
| 1340 | return -ENODEV; |
| 1341 | } |
| 1342 | } |
| 1343 | |
| 1344 | static int arm_smmu_domain_set_attr(struct iommu_domain *domain, |
| 1345 | enum iommu_attr attr, void *data) |
| 1346 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1347 | int ret = 0; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1348 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1349 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1350 | mutex_lock(&smmu_domain->init_mutex); |
| 1351 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1352 | switch (attr) { |
| 1353 | case DOMAIN_ATTR_NESTING: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1354 | if (smmu_domain->smmu) { |
| 1355 | ret = -EPERM; |
| 1356 | goto out_unlock; |
| 1357 | } |
| 1358 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1359 | if (*(int *)data) |
| 1360 | smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; |
| 1361 | else |
| 1362 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; |
| 1363 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1364 | break; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1365 | default: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1366 | ret = -ENODEV; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1367 | } |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1368 | |
| 1369 | out_unlock: |
| 1370 | mutex_unlock(&smmu_domain->init_mutex); |
| 1371 | return ret; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1372 | } |
| 1373 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1374 | static struct iommu_ops arm_smmu_ops = { |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1375 | .capable = arm_smmu_capable, |
| 1376 | .domain_init = arm_smmu_domain_init, |
| 1377 | .domain_destroy = arm_smmu_domain_destroy, |
| 1378 | .attach_dev = arm_smmu_attach_dev, |
| 1379 | .detach_dev = arm_smmu_detach_dev, |
| 1380 | .map = arm_smmu_map, |
| 1381 | .unmap = arm_smmu_unmap, |
Joerg Roedel | 76771c9 | 2014-12-02 13:07:13 +0100 | [diff] [blame] | 1382 | .map_sg = default_iommu_map_sg, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1383 | .iova_to_phys = arm_smmu_iova_to_phys, |
| 1384 | .add_device = arm_smmu_add_device, |
| 1385 | .remove_device = arm_smmu_remove_device, |
| 1386 | .domain_get_attr = arm_smmu_domain_get_attr, |
| 1387 | .domain_set_attr = arm_smmu_domain_set_attr, |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1388 | .pgsize_bitmap = -1UL, /* Restricted during device attach */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1389 | }; |
| 1390 | |
| 1391 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) |
| 1392 | { |
| 1393 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1394 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1395 | int i = 0; |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1396 | u32 reg; |
| 1397 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1398 | /* clear global FSR */ |
| 1399 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); |
| 1400 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1401 | |
| 1402 | /* Mark all SMRn as invalid and all S2CRn as bypass */ |
| 1403 | for (i = 0; i < smmu->num_mapping_groups; ++i) { |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 1404 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1405 | writel_relaxed(S2CR_TYPE_BYPASS, |
| 1406 | gr0_base + ARM_SMMU_GR0_S2CR(i)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1407 | } |
| 1408 | |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1409 | /* Make sure all context banks are disabled and clear CB_FSR */ |
| 1410 | for (i = 0; i < smmu->num_context_banks; ++i) { |
| 1411 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); |
| 1412 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
| 1413 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); |
| 1414 | } |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1415 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1416 | /* Invalidate the TLB, just in case */ |
| 1417 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); |
| 1418 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); |
| 1419 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); |
| 1420 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1421 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1422 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1423 | /* Enable fault reporting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1424 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1425 | |
| 1426 | /* Disable TLB broadcasting. */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1427 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1428 | |
| 1429 | /* Enable client access, but bypass when no mapping is found */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1430 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1431 | |
| 1432 | /* Disable forced broadcasting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1433 | reg &= ~sCR0_FB; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1434 | |
| 1435 | /* Don't upgrade barriers */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1436 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1437 | |
| 1438 | /* Push the button */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1439 | __arm_smmu_tlb_sync(smmu); |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1440 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1441 | } |
| 1442 | |
| 1443 | static int arm_smmu_id_size_to_bits(int size) |
| 1444 | { |
| 1445 | switch (size) { |
| 1446 | case 0: |
| 1447 | return 32; |
| 1448 | case 1: |
| 1449 | return 36; |
| 1450 | case 2: |
| 1451 | return 40; |
| 1452 | case 3: |
| 1453 | return 42; |
| 1454 | case 4: |
| 1455 | return 44; |
| 1456 | case 5: |
| 1457 | default: |
| 1458 | return 48; |
| 1459 | } |
| 1460 | } |
| 1461 | |
| 1462 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) |
| 1463 | { |
| 1464 | unsigned long size; |
| 1465 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1466 | u32 id; |
| 1467 | |
| 1468 | dev_notice(smmu->dev, "probing hardware configuration...\n"); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1469 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); |
| 1470 | |
| 1471 | /* ID0 */ |
| 1472 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 1473 | |
| 1474 | /* Restrict available stages based on module parameter */ |
| 1475 | if (force_stage == 1) |
| 1476 | id &= ~(ID0_S2TS | ID0_NTS); |
| 1477 | else if (force_stage == 2) |
| 1478 | id &= ~(ID0_S1TS | ID0_NTS); |
| 1479 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1480 | if (id & ID0_S1TS) { |
| 1481 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; |
| 1482 | dev_notice(smmu->dev, "\tstage 1 translation\n"); |
| 1483 | } |
| 1484 | |
| 1485 | if (id & ID0_S2TS) { |
| 1486 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; |
| 1487 | dev_notice(smmu->dev, "\tstage 2 translation\n"); |
| 1488 | } |
| 1489 | |
| 1490 | if (id & ID0_NTS) { |
| 1491 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; |
| 1492 | dev_notice(smmu->dev, "\tnested translation\n"); |
| 1493 | } |
| 1494 | |
| 1495 | if (!(smmu->features & |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 1496 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1497 | dev_err(smmu->dev, "\tno translation support!\n"); |
| 1498 | return -ENODEV; |
| 1499 | } |
| 1500 | |
| 1501 | if (id & ID0_CTTW) { |
| 1502 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; |
| 1503 | dev_notice(smmu->dev, "\tcoherent table walk\n"); |
| 1504 | } |
| 1505 | |
| 1506 | if (id & ID0_SMS) { |
| 1507 | u32 smr, sid, mask; |
| 1508 | |
| 1509 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; |
| 1510 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & |
| 1511 | ID0_NUMSMRG_MASK; |
| 1512 | if (smmu->num_mapping_groups == 0) { |
| 1513 | dev_err(smmu->dev, |
| 1514 | "stream-matching supported, but no SMRs present!\n"); |
| 1515 | return -ENODEV; |
| 1516 | } |
| 1517 | |
| 1518 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; |
| 1519 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); |
| 1520 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); |
| 1521 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); |
| 1522 | |
| 1523 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; |
| 1524 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; |
| 1525 | if ((mask & sid) != sid) { |
| 1526 | dev_err(smmu->dev, |
| 1527 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", |
| 1528 | mask, sid); |
| 1529 | return -ENODEV; |
| 1530 | } |
| 1531 | |
| 1532 | dev_notice(smmu->dev, |
| 1533 | "\tstream matching with %u register groups, mask 0x%x", |
| 1534 | smmu->num_mapping_groups, mask); |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 1535 | } else { |
| 1536 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & |
| 1537 | ID0_NUMSIDB_MASK; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1538 | } |
| 1539 | |
| 1540 | /* ID1 */ |
| 1541 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 1542 | smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1543 | |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 1544 | /* Check for size mismatch of SMMU address space from mapped region */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1545 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 1546 | size *= 2 << smmu->pgshift; |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 1547 | if (smmu->size != size) |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1548 | dev_warn(smmu->dev, |
| 1549 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", |
| 1550 | size, smmu->size); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1551 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1552 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1553 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; |
| 1554 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { |
| 1555 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); |
| 1556 | return -ENODEV; |
| 1557 | } |
| 1558 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", |
| 1559 | smmu->num_context_banks, smmu->num_s2_context_banks); |
| 1560 | |
| 1561 | /* ID2 */ |
| 1562 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); |
| 1563 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1564 | smmu->ipa_size = size; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1565 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1566 | /* The output mask is also applied for bypass */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1567 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1568 | smmu->pa_size = size; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1569 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1570 | if (smmu->version == ARM_SMMU_V1) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1571 | smmu->va_size = smmu->ipa_size; |
| 1572 | size = SZ_4K | SZ_2M | SZ_1G; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1573 | } else { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1574 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1575 | smmu->va_size = arm_smmu_id_size_to_bits(size); |
| 1576 | #ifndef CONFIG_64BIT |
| 1577 | smmu->va_size = min(32UL, smmu->va_size); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1578 | #endif |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1579 | size = 0; |
| 1580 | if (id & ID2_PTFS_4K) |
| 1581 | size |= SZ_4K | SZ_2M | SZ_1G; |
| 1582 | if (id & ID2_PTFS_16K) |
| 1583 | size |= SZ_16K | SZ_32M; |
| 1584 | if (id & ID2_PTFS_64K) |
| 1585 | size |= SZ_64K | SZ_512M; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1586 | } |
| 1587 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1588 | arm_smmu_ops.pgsize_bitmap &= size; |
| 1589 | dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size); |
| 1590 | |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 1591 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) |
| 1592 | dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1593 | smmu->va_size, smmu->ipa_size); |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 1594 | |
| 1595 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) |
| 1596 | dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame^] | 1597 | smmu->ipa_size, smmu->pa_size); |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 1598 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1599 | return 0; |
| 1600 | } |
| 1601 | |
Joerg Roedel | 09b5269 | 2014-10-02 12:24:45 +0200 | [diff] [blame] | 1602 | static const struct of_device_id arm_smmu_of_match[] = { |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1603 | { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 }, |
| 1604 | { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 }, |
| 1605 | { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, |
Robin Murphy | d3aba04 | 2014-08-28 17:52:00 +0100 | [diff] [blame] | 1606 | { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1607 | { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, |
| 1608 | { }, |
| 1609 | }; |
| 1610 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); |
| 1611 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1612 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
| 1613 | { |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1614 | const struct of_device_id *of_id; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1615 | struct resource *res; |
| 1616 | struct arm_smmu_device *smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1617 | struct device *dev = &pdev->dev; |
| 1618 | struct rb_node *node; |
| 1619 | struct of_phandle_args masterspec; |
| 1620 | int num_irqs, i, err; |
| 1621 | |
| 1622 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
| 1623 | if (!smmu) { |
| 1624 | dev_err(dev, "failed to allocate arm_smmu_device\n"); |
| 1625 | return -ENOMEM; |
| 1626 | } |
| 1627 | smmu->dev = dev; |
| 1628 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1629 | of_id = of_match_node(arm_smmu_of_match, dev->of_node); |
| 1630 | smmu->version = (enum arm_smmu_arch_version)of_id->data; |
| 1631 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1632 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Julia Lawall | 8a7f431 | 2013-08-19 12:20:37 +0100 | [diff] [blame] | 1633 | smmu->base = devm_ioremap_resource(dev, res); |
| 1634 | if (IS_ERR(smmu->base)) |
| 1635 | return PTR_ERR(smmu->base); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1636 | smmu->size = resource_size(res); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1637 | |
| 1638 | if (of_property_read_u32(dev->of_node, "#global-interrupts", |
| 1639 | &smmu->num_global_irqs)) { |
| 1640 | dev_err(dev, "missing #global-interrupts property\n"); |
| 1641 | return -ENODEV; |
| 1642 | } |
| 1643 | |
| 1644 | num_irqs = 0; |
| 1645 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { |
| 1646 | num_irqs++; |
| 1647 | if (num_irqs > smmu->num_global_irqs) |
| 1648 | smmu->num_context_irqs++; |
| 1649 | } |
| 1650 | |
Andreas Herrmann | 44a08de | 2013-10-01 13:39:07 +0100 | [diff] [blame] | 1651 | if (!smmu->num_context_irqs) { |
| 1652 | dev_err(dev, "found %d interrupts but expected at least %d\n", |
| 1653 | num_irqs, smmu->num_global_irqs + 1); |
| 1654 | return -ENODEV; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1655 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1656 | |
| 1657 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, |
| 1658 | GFP_KERNEL); |
| 1659 | if (!smmu->irqs) { |
| 1660 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); |
| 1661 | return -ENOMEM; |
| 1662 | } |
| 1663 | |
| 1664 | for (i = 0; i < num_irqs; ++i) { |
| 1665 | int irq = platform_get_irq(pdev, i); |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1666 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1667 | if (irq < 0) { |
| 1668 | dev_err(dev, "failed to get irq index %d\n", i); |
| 1669 | return -ENODEV; |
| 1670 | } |
| 1671 | smmu->irqs[i] = irq; |
| 1672 | } |
| 1673 | |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 1674 | err = arm_smmu_device_cfg_probe(smmu); |
| 1675 | if (err) |
| 1676 | return err; |
| 1677 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1678 | i = 0; |
| 1679 | smmu->masters = RB_ROOT; |
| 1680 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", |
| 1681 | "#stream-id-cells", i, |
| 1682 | &masterspec)) { |
| 1683 | err = register_smmu_master(smmu, dev, &masterspec); |
| 1684 | if (err) { |
| 1685 | dev_err(dev, "failed to add master %s\n", |
| 1686 | masterspec.np->name); |
| 1687 | goto out_put_masters; |
| 1688 | } |
| 1689 | |
| 1690 | i++; |
| 1691 | } |
| 1692 | dev_notice(dev, "registered %d master devices\n", i); |
| 1693 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1694 | parse_driver_options(smmu); |
| 1695 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 1696 | if (smmu->version > ARM_SMMU_V1 && |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1697 | smmu->num_context_banks != smmu->num_context_irqs) { |
| 1698 | dev_err(dev, |
| 1699 | "found only %d context interrupt(s) but %d required\n", |
| 1700 | smmu->num_context_irqs, smmu->num_context_banks); |
Wei Yongjun | 89a23cde | 2013-11-15 09:42:30 +0000 | [diff] [blame] | 1701 | err = -ENODEV; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1702 | goto out_put_masters; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1703 | } |
| 1704 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1705 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
| 1706 | err = request_irq(smmu->irqs[i], |
| 1707 | arm_smmu_global_fault, |
| 1708 | IRQF_SHARED, |
| 1709 | "arm-smmu global fault", |
| 1710 | smmu); |
| 1711 | if (err) { |
| 1712 | dev_err(dev, "failed to request global IRQ %d (%u)\n", |
| 1713 | i, smmu->irqs[i]); |
| 1714 | goto out_free_irqs; |
| 1715 | } |
| 1716 | } |
| 1717 | |
| 1718 | INIT_LIST_HEAD(&smmu->list); |
| 1719 | spin_lock(&arm_smmu_devices_lock); |
| 1720 | list_add(&smmu->list, &arm_smmu_devices); |
| 1721 | spin_unlock(&arm_smmu_devices_lock); |
Will Deacon | fd90cec | 2013-08-21 13:56:34 +0100 | [diff] [blame] | 1722 | |
| 1723 | arm_smmu_device_reset(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1724 | return 0; |
| 1725 | |
| 1726 | out_free_irqs: |
| 1727 | while (i--) |
| 1728 | free_irq(smmu->irqs[i], smmu); |
| 1729 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1730 | out_put_masters: |
| 1731 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1732 | struct arm_smmu_master *master |
| 1733 | = container_of(node, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1734 | of_node_put(master->of_node); |
| 1735 | } |
| 1736 | |
| 1737 | return err; |
| 1738 | } |
| 1739 | |
| 1740 | static int arm_smmu_device_remove(struct platform_device *pdev) |
| 1741 | { |
| 1742 | int i; |
| 1743 | struct device *dev = &pdev->dev; |
| 1744 | struct arm_smmu_device *curr, *smmu = NULL; |
| 1745 | struct rb_node *node; |
| 1746 | |
| 1747 | spin_lock(&arm_smmu_devices_lock); |
| 1748 | list_for_each_entry(curr, &arm_smmu_devices, list) { |
| 1749 | if (curr->dev == dev) { |
| 1750 | smmu = curr; |
| 1751 | list_del(&smmu->list); |
| 1752 | break; |
| 1753 | } |
| 1754 | } |
| 1755 | spin_unlock(&arm_smmu_devices_lock); |
| 1756 | |
| 1757 | if (!smmu) |
| 1758 | return -ENODEV; |
| 1759 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1760 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1761 | struct arm_smmu_master *master |
| 1762 | = container_of(node, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1763 | of_node_put(master->of_node); |
| 1764 | } |
| 1765 | |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 1766 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1767 | dev_err(dev, "removing device with active domains!\n"); |
| 1768 | |
| 1769 | for (i = 0; i < smmu->num_global_irqs; ++i) |
| 1770 | free_irq(smmu->irqs[i], smmu); |
| 1771 | |
| 1772 | /* Turn the thing off */ |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1773 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1774 | return 0; |
| 1775 | } |
| 1776 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1777 | static struct platform_driver arm_smmu_driver = { |
| 1778 | .driver = { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1779 | .name = "arm-smmu", |
| 1780 | .of_match_table = of_match_ptr(arm_smmu_of_match), |
| 1781 | }, |
| 1782 | .probe = arm_smmu_device_dt_probe, |
| 1783 | .remove = arm_smmu_device_remove, |
| 1784 | }; |
| 1785 | |
| 1786 | static int __init arm_smmu_init(void) |
| 1787 | { |
Thierry Reding | 0e7d37a | 2014-11-07 15:26:18 +0000 | [diff] [blame] | 1788 | struct device_node *np; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1789 | int ret; |
| 1790 | |
Thierry Reding | 0e7d37a | 2014-11-07 15:26:18 +0000 | [diff] [blame] | 1791 | /* |
| 1792 | * Play nice with systems that don't have an ARM SMMU by checking that |
| 1793 | * an ARM SMMU exists in the system before proceeding with the driver |
| 1794 | * and IOMMU bus operation registration. |
| 1795 | */ |
| 1796 | np = of_find_matching_node(NULL, arm_smmu_of_match); |
| 1797 | if (!np) |
| 1798 | return 0; |
| 1799 | |
| 1800 | of_node_put(np); |
| 1801 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1802 | ret = platform_driver_register(&arm_smmu_driver); |
| 1803 | if (ret) |
| 1804 | return ret; |
| 1805 | |
| 1806 | /* Oh, for a proper bus abstraction */ |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 1807 | if (!iommu_present(&platform_bus_type)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1808 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
| 1809 | |
Will Deacon | d123cf8 | 2014-02-04 22:17:53 +0000 | [diff] [blame] | 1810 | #ifdef CONFIG_ARM_AMBA |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 1811 | if (!iommu_present(&amba_bustype)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1812 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
Will Deacon | d123cf8 | 2014-02-04 22:17:53 +0000 | [diff] [blame] | 1813 | #endif |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1814 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1815 | #ifdef CONFIG_PCI |
| 1816 | if (!iommu_present(&pci_bus_type)) |
| 1817 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); |
| 1818 | #endif |
| 1819 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1820 | return 0; |
| 1821 | } |
| 1822 | |
| 1823 | static void __exit arm_smmu_exit(void) |
| 1824 | { |
| 1825 | return platform_driver_unregister(&arm_smmu_driver); |
| 1826 | } |
| 1827 | |
Andreas Herrmann | b1950b2 | 2013-10-01 13:39:05 +0100 | [diff] [blame] | 1828 | subsys_initcall(arm_smmu_init); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1829 | module_exit(arm_smmu_exit); |
| 1830 | |
| 1831 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); |
| 1832 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); |
| 1833 | MODULE_LICENSE("GPL v2"); |