bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
| 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 19 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 20 | #include "config.h" |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 21 | #include "exec.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 22 | #include "disas.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 23 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 24 | #if !defined(CONFIG_SOFTMMU) |
| 25 | #undef EAX |
| 26 | #undef ECX |
| 27 | #undef EDX |
| 28 | #undef EBX |
| 29 | #undef ESP |
| 30 | #undef EBP |
| 31 | #undef ESI |
| 32 | #undef EDI |
| 33 | #undef EIP |
| 34 | #include <signal.h> |
| 35 | #include <sys/ucontext.h> |
| 36 | #endif |
| 37 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 38 | int tb_invalidated_flag; |
| 39 | |
bellard | dc99065 | 2003-03-19 00:00:28 +0000 | [diff] [blame] | 40 | //#define DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 41 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 42 | |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 44 | /* XXX: unify with i386 target */ |
| 45 | void cpu_loop_exit(void) |
| 46 | { |
| 47 | longjmp(env->jmp_env, 1); |
| 48 | } |
| 49 | #endif |
| 50 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 51 | /* exit the current TB from a signal handler. The host registers are |
| 52 | restored in a state compatible with the CPU emulator |
| 53 | */ |
| 54 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
| 55 | { |
| 56 | #if !defined(CONFIG_SOFTMMU) |
| 57 | struct ucontext *uc = puc; |
| 58 | #endif |
| 59 | |
| 60 | env = env1; |
| 61 | |
| 62 | /* XXX: restore cpu registers saved in host registers */ |
| 63 | |
| 64 | #if !defined(CONFIG_SOFTMMU) |
| 65 | if (puc) { |
| 66 | /* XXX: use siglongjmp ? */ |
| 67 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 68 | } |
| 69 | #endif |
| 70 | longjmp(env->jmp_env, 1); |
| 71 | } |
| 72 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 73 | /* main execution loop */ |
| 74 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 75 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 76 | { |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 77 | int saved_T0, saved_T1, saved_T2; |
| 78 | CPUState *saved_env; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 79 | #ifdef reg_EAX |
| 80 | int saved_EAX; |
| 81 | #endif |
| 82 | #ifdef reg_ECX |
| 83 | int saved_ECX; |
| 84 | #endif |
| 85 | #ifdef reg_EDX |
| 86 | int saved_EDX; |
| 87 | #endif |
| 88 | #ifdef reg_EBX |
| 89 | int saved_EBX; |
| 90 | #endif |
| 91 | #ifdef reg_ESP |
| 92 | int saved_ESP; |
| 93 | #endif |
| 94 | #ifdef reg_EBP |
| 95 | int saved_EBP; |
| 96 | #endif |
| 97 | #ifdef reg_ESI |
| 98 | int saved_ESI; |
| 99 | #endif |
| 100 | #ifdef reg_EDI |
| 101 | int saved_EDI; |
| 102 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 103 | #ifdef __sparc__ |
| 104 | int saved_i7, tmp_T0; |
| 105 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 106 | int code_gen_size, ret, interrupt_request; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 107 | void (*gen_func)(void); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 108 | TranslationBlock *tb, **ptb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 109 | target_ulong cs_base, pc; |
| 110 | uint8_t *tc_ptr; |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 111 | unsigned int flags; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 112 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 113 | /* first we save global registers */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 114 | saved_env = env; |
| 115 | env = env1; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 116 | saved_T0 = T0; |
| 117 | saved_T1 = T1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 118 | saved_T2 = T2; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 119 | #ifdef __sparc__ |
| 120 | /* we also save i7 because longjmp may not restore it */ |
| 121 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 122 | #endif |
| 123 | |
| 124 | #if defined(TARGET_I386) |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 125 | #ifdef reg_EAX |
| 126 | saved_EAX = EAX; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 127 | #endif |
| 128 | #ifdef reg_ECX |
| 129 | saved_ECX = ECX; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 130 | #endif |
| 131 | #ifdef reg_EDX |
| 132 | saved_EDX = EDX; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 133 | #endif |
| 134 | #ifdef reg_EBX |
| 135 | saved_EBX = EBX; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 136 | #endif |
| 137 | #ifdef reg_ESP |
| 138 | saved_ESP = ESP; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 139 | #endif |
| 140 | #ifdef reg_EBP |
| 141 | saved_EBP = EBP; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 142 | #endif |
| 143 | #ifdef reg_ESI |
| 144 | saved_ESI = ESI; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 145 | #endif |
| 146 | #ifdef reg_EDI |
| 147 | saved_EDI = EDI; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 148 | #endif |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 149 | |
| 150 | env_to_regs(); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 151 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 152 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 153 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 154 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 155 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 156 | #elif defined(TARGET_ARM) |
| 157 | { |
| 158 | unsigned int psr; |
| 159 | psr = env->cpsr; |
| 160 | env->CF = (psr >> 29) & 1; |
| 161 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
| 162 | env->VF = (psr << 3) & 0x80000000; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 163 | env->QF = (psr >> 27) & 1; |
| 164 | env->cpsr = psr & ~CACHED_CPSR_BITS; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 165 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 166 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 167 | #elif defined(TARGET_PPC) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 168 | #else |
| 169 | #error unsupported target CPU |
| 170 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 171 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 172 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 173 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 174 | for(;;) { |
| 175 | if (setjmp(env->jmp_env) == 0) { |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 176 | env->current_tb = NULL; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 177 | /* if an exception is pending, we execute it here */ |
| 178 | if (env->exception_index >= 0) { |
| 179 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 180 | /* exit request from the cpu execution loop */ |
| 181 | ret = env->exception_index; |
| 182 | break; |
| 183 | } else if (env->user_mode_only) { |
| 184 | /* if user mode only, we simulate a fake exception |
| 185 | which will be hanlded outside the cpu execution |
| 186 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 187 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 188 | do_interrupt_user(env->exception_index, |
| 189 | env->exception_is_int, |
| 190 | env->error_code, |
| 191 | env->exception_next_eip); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 192 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 193 | ret = env->exception_index; |
| 194 | break; |
| 195 | } else { |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 196 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 197 | /* simulate a real cpu exception. On i386, it can |
| 198 | trigger new exceptions, but we do not handle |
| 199 | double or triple faults yet. */ |
| 200 | do_interrupt(env->exception_index, |
| 201 | env->exception_is_int, |
| 202 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 203 | env->exception_next_eip, 0); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 204 | #elif defined(TARGET_PPC) |
| 205 | do_interrupt(env); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 206 | #elif defined(TARGET_SPARC) |
bellard | 1a0c329 | 2005-02-13 19:02:07 +0000 | [diff] [blame] | 207 | do_interrupt(env->exception_index); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 208 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 209 | } |
| 210 | env->exception_index = -1; |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 211 | } |
| 212 | #ifdef USE_KQEMU |
| 213 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
| 214 | int ret; |
| 215 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 216 | ret = kqemu_cpu_exec(env); |
| 217 | /* put eflags in CPU temporary format */ |
| 218 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 219 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 220 | CC_OP = CC_OP_EFLAGS; |
| 221 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 222 | if (ret == 1) { |
| 223 | /* exception */ |
| 224 | longjmp(env->jmp_env, 1); |
| 225 | } else if (ret == 2) { |
| 226 | /* softmmu execution needed */ |
| 227 | } else { |
| 228 | if (env->interrupt_request != 0) { |
| 229 | /* hardware interrupt will be executed just after */ |
| 230 | } else { |
| 231 | /* otherwise, we restart */ |
| 232 | longjmp(env->jmp_env, 1); |
| 233 | } |
| 234 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 235 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 236 | #endif |
| 237 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 238 | T0 = 0; /* force lookup of first TB */ |
| 239 | for(;;) { |
| 240 | #ifdef __sparc__ |
| 241 | /* g1 can be modified by some libc? functions */ |
| 242 | tmp_T0 = T0; |
| 243 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 244 | interrupt_request = env->interrupt_request; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 245 | if (__builtin_expect(interrupt_request, 0)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 246 | #if defined(TARGET_I386) |
| 247 | /* if hardware interrupt pending, we execute it */ |
| 248 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 249 | (env->eflags & IF_MASK) && |
| 250 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 251 | int intno; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 252 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 253 | intno = cpu_get_pic_interrupt(env); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 254 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 255 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
| 256 | } |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 257 | do_interrupt(intno, 0, 0, 0, 1); |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 258 | /* ensure that no TB jump will be modified as |
| 259 | the program flow was changed */ |
| 260 | #ifdef __sparc__ |
| 261 | tmp_T0 = 0; |
| 262 | #else |
| 263 | T0 = 0; |
| 264 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 265 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 266 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 267 | #if 0 |
| 268 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
| 269 | cpu_ppc_reset(env); |
| 270 | } |
| 271 | #endif |
| 272 | if (msr_ee != 0) { |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 273 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 274 | /* Raise it */ |
| 275 | env->exception_index = EXCP_EXTERNAL; |
| 276 | env->error_code = 0; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 277 | do_interrupt(env); |
| 278 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 279 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
| 280 | /* Raise it */ |
| 281 | env->exception_index = EXCP_DECR; |
| 282 | env->error_code = 0; |
| 283 | do_interrupt(env); |
| 284 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
| 285 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 286 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 287 | #elif defined(TARGET_SPARC) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 288 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 289 | (env->psret != 0)) { |
| 290 | int pil = env->interrupt_index & 15; |
| 291 | int type = env->interrupt_index & 0xf0; |
| 292 | |
| 293 | if (((type == TT_EXTINT) && |
| 294 | (pil == 15 || pil > env->psrpil)) || |
| 295 | type != TT_EXTINT) { |
| 296 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 297 | do_interrupt(env->interrupt_index); |
| 298 | env->interrupt_index = 0; |
| 299 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 300 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 301 | //do_interrupt(0, 0, 0, 0, 0); |
| 302 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
| 303 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 304 | #endif |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 305 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
| 306 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 307 | /* ensure that no TB jump will be modified as |
| 308 | the program flow was changed */ |
| 309 | #ifdef __sparc__ |
| 310 | tmp_T0 = 0; |
| 311 | #else |
| 312 | T0 = 0; |
| 313 | #endif |
| 314 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 315 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
| 316 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
| 317 | env->exception_index = EXCP_INTERRUPT; |
| 318 | cpu_loop_exit(); |
| 319 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 320 | } |
| 321 | #ifdef DEBUG_EXEC |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 322 | if ((loglevel & CPU_LOG_EXEC)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 323 | #if defined(TARGET_I386) |
| 324 | /* restore flags in standard format */ |
| 325 | env->regs[R_EAX] = EAX; |
| 326 | env->regs[R_EBX] = EBX; |
| 327 | env->regs[R_ECX] = ECX; |
| 328 | env->regs[R_EDX] = EDX; |
| 329 | env->regs[R_ESI] = ESI; |
| 330 | env->regs[R_EDI] = EDI; |
| 331 | env->regs[R_EBP] = EBP; |
| 332 | env->regs[R_ESP] = ESP; |
| 333 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 334 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 335 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 336 | #elif defined(TARGET_ARM) |
bellard | 1b21b62 | 2003-07-09 17:16:27 +0000 | [diff] [blame] | 337 | env->cpsr = compute_cpsr(); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 338 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 339 | env->cpsr &= ~CACHED_CPSR_BITS; |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 340 | #elif defined(TARGET_SPARC) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 341 | cpu_dump_state (env, logfile, fprintf, 0); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 342 | #elif defined(TARGET_PPC) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 343 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 344 | #else |
| 345 | #error unsupported target CPU |
| 346 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 347 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 348 | #endif |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 349 | /* we record a subset of the CPU state. It will |
| 350 | always be the same before a given translated block |
| 351 | is executed. */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 352 | #if defined(TARGET_I386) |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 353 | flags = env->hflags; |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 354 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 355 | cs_base = env->segs[R_CS].base; |
| 356 | pc = cs_base + env->eip; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 357 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 358 | flags = env->thumb | (env->vfp.vec_len << 1) |
| 359 | | (env->vfp.vec_stride << 4); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 360 | cs_base = 0; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 361 | pc = env->regs[15]; |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 362 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 363 | flags = 0; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 364 | cs_base = env->npc; |
| 365 | pc = env->pc; |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 366 | #elif defined(TARGET_PPC) |
bellard | c4decf3 | 2005-02-15 22:59:52 +0000 | [diff] [blame] | 367 | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_se << MSR_SE); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 368 | cs_base = 0; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 369 | pc = env->nip; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 370 | #else |
| 371 | #error unsupported CPU |
| 372 | #endif |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 373 | tb = tb_find(&ptb, pc, cs_base, |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 374 | flags); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 375 | if (!tb) { |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 376 | TranslationBlock **ptb1; |
| 377 | unsigned int h; |
| 378 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
| 379 | |
| 380 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 381 | spin_lock(&tb_lock); |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 382 | |
| 383 | tb_invalidated_flag = 0; |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 384 | |
| 385 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 386 | |
| 387 | /* find translated block using physical mappings */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 388 | phys_pc = get_phys_addr_code(env, pc); |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 389 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 390 | phys_page2 = -1; |
| 391 | h = tb_phys_hash_func(phys_pc); |
| 392 | ptb1 = &tb_phys_hash[h]; |
| 393 | for(;;) { |
| 394 | tb = *ptb1; |
| 395 | if (!tb) |
| 396 | goto not_found; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 397 | if (tb->pc == pc && |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 398 | tb->page_addr[0] == phys_page1 && |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 399 | tb->cs_base == cs_base && |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 400 | tb->flags == flags) { |
| 401 | /* check next page if needed */ |
bellard | b516f85 | 2004-01-18 21:50:04 +0000 | [diff] [blame] | 402 | if (tb->page_addr[1] != -1) { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 403 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
bellard | b516f85 | 2004-01-18 21:50:04 +0000 | [diff] [blame] | 404 | TARGET_PAGE_SIZE; |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 405 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 406 | if (tb->page_addr[1] == phys_page2) |
| 407 | goto found; |
| 408 | } else { |
| 409 | goto found; |
| 410 | } |
| 411 | } |
| 412 | ptb1 = &tb->phys_hash_next; |
| 413 | } |
| 414 | not_found: |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 415 | /* if no translated code available, then translate it now */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 416 | tb = tb_alloc(pc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 417 | if (!tb) { |
| 418 | /* flush must be done */ |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 419 | tb_flush(env); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 420 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 421 | tb = tb_alloc(pc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 422 | /* don't forget to invalidate previous TB info */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 423 | ptb = &tb_hash[tb_hash_func(pc)]; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 424 | T0 = 0; |
| 425 | } |
| 426 | tc_ptr = code_gen_ptr; |
| 427 | tb->tc_ptr = tc_ptr; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 428 | tb->cs_base = cs_base; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 429 | tb->flags = flags; |
bellard | facc68b | 2003-09-17 22:51:18 +0000 | [diff] [blame] | 430 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 431 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
| 432 | |
| 433 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 434 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 435 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 436 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 437 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 438 | } |
| 439 | tb_link_phys(tb, phys_pc, phys_page2); |
| 440 | |
| 441 | found: |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 442 | if (tb_invalidated_flag) { |
| 443 | /* as some TB could have been invalidated because |
| 444 | of memory exceptions while generating the code, we |
| 445 | must recompute the hash index here */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 446 | ptb = &tb_hash[tb_hash_func(pc)]; |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 447 | while (*ptb != NULL) |
| 448 | ptb = &(*ptb)->hash_next; |
| 449 | T0 = 0; |
| 450 | } |
bellard | 1376847 | 2004-01-04 17:43:01 +0000 | [diff] [blame] | 451 | /* we add the TB in the virtual pc hash table */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 452 | *ptb = tb; |
| 453 | tb->hash_next = NULL; |
| 454 | tb_link(tb); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 455 | spin_unlock(&tb_lock); |
| 456 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 457 | #ifdef DEBUG_EXEC |
bellard | c1135f6 | 2005-01-30 22:41:54 +0000 | [diff] [blame] | 458 | if ((loglevel & CPU_LOG_EXEC)) { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 459 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 460 | (long)tb->tc_ptr, tb->pc, |
| 461 | lookup_symbol(tb->pc)); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 462 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 463 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 464 | #ifdef __sparc__ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 465 | T0 = tmp_T0; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 466 | #endif |
bellard | facc68b | 2003-09-17 22:51:18 +0000 | [diff] [blame] | 467 | /* see if we can patch the calling TB. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 468 | { |
| 469 | if (T0 != 0 |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 470 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 471 | && (tb->cflags & CF_CODE_COPY) == |
| 472 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) |
| 473 | #endif |
| 474 | ) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 475 | spin_lock(&tb_lock); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 476 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 477 | #if defined(USE_CODE_COPY) |
| 478 | /* propagates the FP use info */ |
| 479 | ((TranslationBlock *)(T0 & ~3))->cflags |= |
| 480 | (tb->cflags & CF_FP_USED); |
| 481 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 482 | spin_unlock(&tb_lock); |
| 483 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 484 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 485 | tc_ptr = tb->tc_ptr; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 486 | env->current_tb = tb; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 487 | /* execute the generated code */ |
| 488 | gen_func = (void *)tc_ptr; |
| 489 | #if defined(__sparc__) |
| 490 | __asm__ __volatile__("call %0\n\t" |
| 491 | "mov %%o7,%%i0" |
| 492 | : /* no outputs */ |
| 493 | : "r" (gen_func) |
| 494 | : "i0", "i1", "i2", "i3", "i4", "i5"); |
| 495 | #elif defined(__arm__) |
| 496 | asm volatile ("mov pc, %0\n\t" |
| 497 | ".global exec_loop\n\t" |
| 498 | "exec_loop:\n\t" |
| 499 | : /* no outputs */ |
| 500 | : "r" (gen_func) |
| 501 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 502 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 503 | { |
| 504 | if (!(tb->cflags & CF_CODE_COPY)) { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 505 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
| 506 | save_native_fp_state(env); |
| 507 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 508 | gen_func(); |
| 509 | } else { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 510 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
| 511 | restore_native_fp_state(env); |
| 512 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 513 | /* we work with native eflags */ |
| 514 | CC_SRC = cc_table[CC_OP].compute_all(); |
| 515 | CC_OP = CC_OP_EFLAGS; |
| 516 | asm(".globl exec_loop\n" |
| 517 | "\n" |
| 518 | "debug1:\n" |
| 519 | " pushl %%ebp\n" |
| 520 | " fs movl %10, %9\n" |
| 521 | " fs movl %11, %%eax\n" |
| 522 | " andl $0x400, %%eax\n" |
| 523 | " fs orl %8, %%eax\n" |
| 524 | " pushl %%eax\n" |
| 525 | " popf\n" |
| 526 | " fs movl %%esp, %12\n" |
| 527 | " fs movl %0, %%eax\n" |
| 528 | " fs movl %1, %%ecx\n" |
| 529 | " fs movl %2, %%edx\n" |
| 530 | " fs movl %3, %%ebx\n" |
| 531 | " fs movl %4, %%esp\n" |
| 532 | " fs movl %5, %%ebp\n" |
| 533 | " fs movl %6, %%esi\n" |
| 534 | " fs movl %7, %%edi\n" |
| 535 | " fs jmp *%9\n" |
| 536 | "exec_loop:\n" |
| 537 | " fs movl %%esp, %4\n" |
| 538 | " fs movl %12, %%esp\n" |
| 539 | " fs movl %%eax, %0\n" |
| 540 | " fs movl %%ecx, %1\n" |
| 541 | " fs movl %%edx, %2\n" |
| 542 | " fs movl %%ebx, %3\n" |
| 543 | " fs movl %%ebp, %5\n" |
| 544 | " fs movl %%esi, %6\n" |
| 545 | " fs movl %%edi, %7\n" |
| 546 | " pushf\n" |
| 547 | " popl %%eax\n" |
| 548 | " movl %%eax, %%ecx\n" |
| 549 | " andl $0x400, %%ecx\n" |
| 550 | " shrl $9, %%ecx\n" |
| 551 | " andl $0x8d5, %%eax\n" |
| 552 | " fs movl %%eax, %8\n" |
| 553 | " movl $1, %%eax\n" |
| 554 | " subl %%ecx, %%eax\n" |
| 555 | " fs movl %%eax, %11\n" |
| 556 | " fs movl %9, %%ebx\n" /* get T0 value */ |
| 557 | " popl %%ebp\n" |
| 558 | : |
| 559 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
| 560 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
| 561 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
| 562 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
| 563 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
| 564 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
| 565 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
| 566 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
| 567 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), |
| 568 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), |
| 569 | "a" (gen_func), |
| 570 | "m" (*(uint8_t *)offsetof(CPUState, df)), |
| 571 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) |
| 572 | : "%ecx", "%edx" |
| 573 | ); |
| 574 | } |
| 575 | } |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame^] | 576 | #elif defined(__ia64) |
| 577 | struct fptr { |
| 578 | void *ip; |
| 579 | void *gp; |
| 580 | } fp; |
| 581 | |
| 582 | fp.ip = tc_ptr; |
| 583 | fp.gp = code_gen_buffer + 2 * (1 << 20); |
| 584 | (*(void (*)(void)) &fp)(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 585 | #else |
| 586 | gen_func(); |
| 587 | #endif |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 588 | env->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 589 | /* reset soft MMU for next block (it can currently |
| 590 | only be set by a memory fault) */ |
| 591 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 592 | if (env->hflags & HF_SOFTMMU_MASK) { |
| 593 | env->hflags &= ~HF_SOFTMMU_MASK; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 594 | /* do not allow linking to another block */ |
| 595 | T0 = 0; |
| 596 | } |
| 597 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 598 | } |
| 599 | } else { |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 600 | env_to_regs(); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 601 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 602 | } /* for(;;) */ |
| 603 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 604 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 605 | #if defined(TARGET_I386) |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 606 | #if defined(USE_CODE_COPY) |
| 607 | if (env->native_fp_regs) { |
| 608 | save_native_fp_state(env); |
| 609 | } |
| 610 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 611 | /* restore flags in standard format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 612 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 613 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 614 | /* restore global registers */ |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 615 | #ifdef reg_EAX |
| 616 | EAX = saved_EAX; |
| 617 | #endif |
| 618 | #ifdef reg_ECX |
| 619 | ECX = saved_ECX; |
| 620 | #endif |
| 621 | #ifdef reg_EDX |
| 622 | EDX = saved_EDX; |
| 623 | #endif |
| 624 | #ifdef reg_EBX |
| 625 | EBX = saved_EBX; |
| 626 | #endif |
| 627 | #ifdef reg_ESP |
| 628 | ESP = saved_ESP; |
| 629 | #endif |
| 630 | #ifdef reg_EBP |
| 631 | EBP = saved_EBP; |
| 632 | #endif |
| 633 | #ifdef reg_ESI |
| 634 | ESI = saved_ESI; |
| 635 | #endif |
| 636 | #ifdef reg_EDI |
| 637 | EDI = saved_EDI; |
| 638 | #endif |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 639 | #elif defined(TARGET_ARM) |
bellard | 1b21b62 | 2003-07-09 17:16:27 +0000 | [diff] [blame] | 640 | env->cpsr = compute_cpsr(); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 641 | /* XXX: Save/restore host fpu exception state?. */ |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 642 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 643 | #elif defined(TARGET_PPC) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 644 | #else |
| 645 | #error unsupported target CPU |
| 646 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 647 | #ifdef __sparc__ |
| 648 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 649 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 650 | T0 = saved_T0; |
| 651 | T1 = saved_T1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 652 | T2 = saved_T2; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 653 | env = saved_env; |
| 654 | return ret; |
| 655 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 656 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 657 | /* must only be called from the generated code as an exception can be |
| 658 | generated */ |
| 659 | void tb_invalidate_page_range(target_ulong start, target_ulong end) |
| 660 | { |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 661 | /* XXX: cannot enable it yet because it yields to MMU exception |
| 662 | where NIP != read address on PowerPC */ |
| 663 | #if 0 |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 664 | target_ulong phys_addr; |
| 665 | phys_addr = get_phys_addr_code(env, start); |
| 666 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 667 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 668 | } |
| 669 | |
bellard | 1a18c71 | 2003-10-30 01:07:51 +0000 | [diff] [blame] | 670 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 671 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 672 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 673 | { |
| 674 | CPUX86State *saved_env; |
| 675 | |
| 676 | saved_env = env; |
| 677 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 678 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 679 | selector &= 0xffff; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 680 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 681 | (selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 682 | } else { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 683 | load_seg(seg_reg, selector); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 684 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 685 | env = saved_env; |
| 686 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 687 | |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 688 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 689 | { |
| 690 | CPUX86State *saved_env; |
| 691 | |
| 692 | saved_env = env; |
| 693 | env = s; |
| 694 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 695 | helper_fsave((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 696 | |
| 697 | env = saved_env; |
| 698 | } |
| 699 | |
| 700 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 701 | { |
| 702 | CPUX86State *saved_env; |
| 703 | |
| 704 | saved_env = env; |
| 705 | env = s; |
| 706 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 707 | helper_frstor((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 708 | |
| 709 | env = saved_env; |
| 710 | } |
| 711 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 712 | #endif /* TARGET_I386 */ |
| 713 | |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 714 | #if !defined(CONFIG_SOFTMMU) |
| 715 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 716 | #if defined(TARGET_I386) |
| 717 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 718 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 719 | the effective address of the memory exception. 'is_write' is 1 if a |
| 720 | write caused the exception and otherwise 0'. 'old_set' is the |
| 721 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 722 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 723 | int is_write, sigset_t *old_set, |
| 724 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 725 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 726 | TranslationBlock *tb; |
| 727 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 728 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 729 | if (cpu_single_env) |
| 730 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 731 | #if defined(DEBUG_SIGNAL) |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 732 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 733 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 734 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 735 | /* XXX: locking issue */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 736 | if (is_write && page_unprotect(address, pc, puc)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 737 | return 1; |
| 738 | } |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 739 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 740 | /* see if it is an MMU fault */ |
bellard | 93a40ea | 2003-10-27 21:13:06 +0000 | [diff] [blame] | 741 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
| 742 | ((env->hflags & HF_CPL_MASK) == 3), 0); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 743 | if (ret < 0) |
| 744 | return 0; /* not an MMU fault */ |
| 745 | if (ret == 0) |
| 746 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 747 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 748 | tb = tb_find_pc(pc); |
| 749 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 750 | /* the PC is inside the translated code. It means that we have |
| 751 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 752 | cpu_restore_state(tb, env, pc, puc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 753 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 754 | if (ret == 1) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 755 | #if 0 |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 756 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
| 757 | env->eip, env->cr[2], env->error_code); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 758 | #endif |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 759 | /* we restore the process signal mask as the sigreturn should |
| 760 | do it (XXX: use sigsetjmp) */ |
| 761 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 762 | raise_exception_err(EXCP0E_PAGE, env->error_code); |
| 763 | } else { |
| 764 | /* activate soft MMU for this block */ |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 765 | env->hflags |= HF_SOFTMMU_MASK; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 766 | cpu_resume_from_signal(env, puc); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 767 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 768 | /* never comes here */ |
| 769 | return 1; |
| 770 | } |
| 771 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 772 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 773 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 774 | int is_write, sigset_t *old_set, |
| 775 | void *puc) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 776 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 777 | TranslationBlock *tb; |
| 778 | int ret; |
| 779 | |
| 780 | if (cpu_single_env) |
| 781 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 782 | #if defined(DEBUG_SIGNAL) |
| 783 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 784 | pc, address, is_write, *(unsigned long *)old_set); |
| 785 | #endif |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 786 | /* XXX: locking issue */ |
| 787 | if (is_write && page_unprotect(address, pc, puc)) { |
| 788 | return 1; |
| 789 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 790 | /* see if it is an MMU fault */ |
| 791 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
| 792 | if (ret < 0) |
| 793 | return 0; /* not an MMU fault */ |
| 794 | if (ret == 0) |
| 795 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 796 | /* now we have a real cpu fault */ |
| 797 | tb = tb_find_pc(pc); |
| 798 | if (tb) { |
| 799 | /* the PC is inside the translated code. It means that we have |
| 800 | a virtual CPU fault */ |
| 801 | cpu_restore_state(tb, env, pc, puc); |
| 802 | } |
| 803 | /* we restore the process signal mask as the sigreturn should |
| 804 | do it (XXX: use sigsetjmp) */ |
| 805 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 806 | cpu_loop_exit(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 807 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 808 | #elif defined(TARGET_SPARC) |
| 809 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 810 | int is_write, sigset_t *old_set, |
| 811 | void *puc) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 812 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 813 | TranslationBlock *tb; |
| 814 | int ret; |
| 815 | |
| 816 | if (cpu_single_env) |
| 817 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 818 | #if defined(DEBUG_SIGNAL) |
| 819 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 820 | pc, address, is_write, *(unsigned long *)old_set); |
| 821 | #endif |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 822 | /* XXX: locking issue */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 823 | if (is_write && page_unprotect(address, pc, puc)) { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 824 | return 1; |
| 825 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 826 | /* see if it is an MMU fault */ |
| 827 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
| 828 | if (ret < 0) |
| 829 | return 0; /* not an MMU fault */ |
| 830 | if (ret == 0) |
| 831 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 832 | /* now we have a real cpu fault */ |
| 833 | tb = tb_find_pc(pc); |
| 834 | if (tb) { |
| 835 | /* the PC is inside the translated code. It means that we have |
| 836 | a virtual CPU fault */ |
| 837 | cpu_restore_state(tb, env, pc, puc); |
| 838 | } |
| 839 | /* we restore the process signal mask as the sigreturn should |
| 840 | do it (XXX: use sigsetjmp) */ |
| 841 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 842 | cpu_loop_exit(); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 843 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 844 | #elif defined (TARGET_PPC) |
| 845 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 846 | int is_write, sigset_t *old_set, |
| 847 | void *puc) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 848 | { |
| 849 | TranslationBlock *tb; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 850 | int ret; |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 851 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 852 | if (cpu_single_env) |
| 853 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 854 | #if defined(DEBUG_SIGNAL) |
| 855 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 856 | pc, address, is_write, *(unsigned long *)old_set); |
| 857 | #endif |
| 858 | /* XXX: locking issue */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 859 | if (is_write && page_unprotect(address, pc, puc)) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 860 | return 1; |
| 861 | } |
| 862 | |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 863 | /* see if it is an MMU fault */ |
bellard | 7f957d2 | 2004-01-18 23:19:48 +0000 | [diff] [blame] | 864 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 865 | if (ret < 0) |
| 866 | return 0; /* not an MMU fault */ |
| 867 | if (ret == 0) |
| 868 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 869 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 870 | /* now we have a real cpu fault */ |
| 871 | tb = tb_find_pc(pc); |
| 872 | if (tb) { |
| 873 | /* the PC is inside the translated code. It means that we have |
| 874 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 875 | cpu_restore_state(tb, env, pc, puc); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 876 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 877 | if (ret == 1) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 878 | #if 0 |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 879 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
| 880 | env->nip, env->error_code, tb); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 881 | #endif |
| 882 | /* we restore the process signal mask as the sigreturn should |
| 883 | do it (XXX: use sigsetjmp) */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 884 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 885 | do_raise_exception_err(env->exception_index, env->error_code); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 886 | } else { |
| 887 | /* activate soft MMU for this block */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 888 | cpu_resume_from_signal(env, puc); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 889 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 890 | /* never comes here */ |
| 891 | return 1; |
| 892 | } |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 893 | #else |
| 894 | #error unsupported target CPU |
| 895 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 896 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 897 | #if defined(__i386__) |
| 898 | |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 899 | #if defined(USE_CODE_COPY) |
| 900 | static void cpu_send_trap(unsigned long pc, int trap, |
| 901 | struct ucontext *uc) |
| 902 | { |
| 903 | TranslationBlock *tb; |
| 904 | |
| 905 | if (cpu_single_env) |
| 906 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 907 | /* now we have a real cpu fault */ |
| 908 | tb = tb_find_pc(pc); |
| 909 | if (tb) { |
| 910 | /* the PC is inside the translated code. It means that we have |
| 911 | a virtual CPU fault */ |
| 912 | cpu_restore_state(tb, env, pc, uc); |
| 913 | } |
| 914 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 915 | raise_exception_err(trap, env->error_code); |
| 916 | } |
| 917 | #endif |
| 918 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 919 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 920 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 921 | { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 922 | struct ucontext *uc = puc; |
| 923 | unsigned long pc; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 924 | int trapno; |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 925 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 926 | #ifndef REG_EIP |
| 927 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 928 | #define REG_EIP EIP |
| 929 | #define REG_ERR ERR |
| 930 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 931 | #endif |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 932 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 933 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
| 934 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 935 | if (trapno == 0x00 || trapno == 0x05) { |
| 936 | /* send division by zero or bound exception */ |
| 937 | cpu_send_trap(pc, trapno, uc); |
| 938 | return 1; |
| 939 | } else |
| 940 | #endif |
| 941 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 942 | trapno == 0xe ? |
| 943 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 944 | &uc->uc_sigmask, puc); |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 945 | } |
| 946 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 947 | #elif defined(__x86_64__) |
| 948 | |
| 949 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 950 | void *puc) |
| 951 | { |
| 952 | struct ucontext *uc = puc; |
| 953 | unsigned long pc; |
| 954 | |
| 955 | pc = uc->uc_mcontext.gregs[REG_RIP]; |
| 956 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 957 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
| 958 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 959 | &uc->uc_sigmask, puc); |
| 960 | } |
| 961 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 962 | #elif defined(__powerpc__) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 963 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 964 | /*********************************************************************** |
| 965 | * signal context platform-specific definitions |
| 966 | * From Wine |
| 967 | */ |
| 968 | #ifdef linux |
| 969 | /* All Registers access - only for local access */ |
| 970 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) |
| 971 | /* Gpr Registers access */ |
| 972 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
| 973 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 974 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 975 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 976 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 977 | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 978 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 979 | /* Float Registers access */ |
| 980 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 981 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 982 | /* Exception Registers access */ |
| 983 | # define DAR_sig(context) REG_sig(dar, context) |
| 984 | # define DSISR_sig(context) REG_sig(dsisr, context) |
| 985 | # define TRAP_sig(context) REG_sig(trap, context) |
| 986 | #endif /* linux */ |
| 987 | |
| 988 | #ifdef __APPLE__ |
| 989 | # include <sys/ucontext.h> |
| 990 | typedef struct ucontext SIGCONTEXT; |
| 991 | /* All Registers access - only for local access */ |
| 992 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) |
| 993 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) |
| 994 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) |
| 995 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) |
| 996 | /* Gpr Registers access */ |
| 997 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 998 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 999 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 1000 | # define CTR_sig(context) REG_sig(ctr, context) |
| 1001 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 1002 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 1003 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 1004 | /* Float Registers access */ |
| 1005 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) |
| 1006 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 1007 | /* Exception Registers access */ |
| 1008 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 1009 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
| 1010 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 1011 | #endif /* __APPLE__ */ |
| 1012 | |
bellard | d1d9f42 | 2004-07-14 17:20:55 +0000 | [diff] [blame] | 1013 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1014 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1015 | { |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1016 | struct ucontext *uc = puc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1017 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1018 | int is_write; |
| 1019 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1020 | pc = IAR_sig(uc); |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1021 | is_write = 0; |
| 1022 | #if 0 |
| 1023 | /* ppc 4xx case */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1024 | if (DSISR_sig(uc) & 0x00800000) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1025 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1026 | #else |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1027 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1028 | is_write = 1; |
| 1029 | #endif |
| 1030 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1031 | is_write, &uc->uc_sigmask, puc); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1032 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1033 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1034 | #elif defined(__alpha__) |
| 1035 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1036 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1037 | void *puc) |
| 1038 | { |
| 1039 | struct ucontext *uc = puc; |
| 1040 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 1041 | uint32_t insn = *pc; |
| 1042 | int is_write = 0; |
| 1043 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1044 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1045 | switch (insn >> 26) { |
| 1046 | case 0x0d: // stw |
| 1047 | case 0x0e: // stb |
| 1048 | case 0x0f: // stq_u |
| 1049 | case 0x24: // stf |
| 1050 | case 0x25: // stg |
| 1051 | case 0x26: // sts |
| 1052 | case 0x27: // stt |
| 1053 | case 0x2c: // stl |
| 1054 | case 0x2d: // stq |
| 1055 | case 0x2e: // stl_c |
| 1056 | case 0x2f: // stq_c |
| 1057 | is_write = 1; |
| 1058 | } |
| 1059 | |
| 1060 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1061 | is_write, &uc->uc_sigmask, puc); |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1062 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1063 | #elif defined(__sparc__) |
| 1064 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1065 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1066 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1067 | { |
| 1068 | uint32_t *regs = (uint32_t *)(info + 1); |
| 1069 | void *sigmask = (regs + 20); |
| 1070 | unsigned long pc; |
| 1071 | int is_write; |
| 1072 | uint32_t insn; |
| 1073 | |
| 1074 | /* XXX: is there a standard glibc define ? */ |
| 1075 | pc = regs[1]; |
| 1076 | /* XXX: need kernel patch to get write flag faster */ |
| 1077 | is_write = 0; |
| 1078 | insn = *(uint32_t *)pc; |
| 1079 | if ((insn >> 30) == 3) { |
| 1080 | switch((insn >> 19) & 0x3f) { |
| 1081 | case 0x05: // stb |
| 1082 | case 0x06: // sth |
| 1083 | case 0x04: // st |
| 1084 | case 0x07: // std |
| 1085 | case 0x24: // stf |
| 1086 | case 0x27: // stdf |
| 1087 | case 0x25: // stfsr |
| 1088 | is_write = 1; |
| 1089 | break; |
| 1090 | } |
| 1091 | } |
| 1092 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1093 | is_write, sigmask, NULL); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1094 | } |
| 1095 | |
| 1096 | #elif defined(__arm__) |
| 1097 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1098 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1099 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1100 | { |
| 1101 | struct ucontext *uc = puc; |
| 1102 | unsigned long pc; |
| 1103 | int is_write; |
| 1104 | |
| 1105 | pc = uc->uc_mcontext.gregs[R15]; |
| 1106 | /* XXX: compute is_write */ |
| 1107 | is_write = 0; |
| 1108 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1109 | is_write, |
| 1110 | &uc->uc_sigmask); |
| 1111 | } |
| 1112 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1113 | #elif defined(__mc68000) |
| 1114 | |
| 1115 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1116 | void *puc) |
| 1117 | { |
| 1118 | struct ucontext *uc = puc; |
| 1119 | unsigned long pc; |
| 1120 | int is_write; |
| 1121 | |
| 1122 | pc = uc->uc_mcontext.gregs[16]; |
| 1123 | /* XXX: compute is_write */ |
| 1124 | is_write = 0; |
| 1125 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1126 | is_write, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1127 | &uc->uc_sigmask, puc); |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1128 | } |
| 1129 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame^] | 1130 | #elif defined(__ia64) |
| 1131 | |
| 1132 | #ifndef __ISR_VALID |
| 1133 | /* This ought to be in <bits/siginfo.h>... */ |
| 1134 | # define __ISR_VALID 1 |
| 1135 | # define si_flags _sifields._sigfault._si_pad0 |
| 1136 | #endif |
| 1137 | |
| 1138 | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) |
| 1139 | { |
| 1140 | struct ucontext *uc = puc; |
| 1141 | unsigned long ip; |
| 1142 | int is_write = 0; |
| 1143 | |
| 1144 | ip = uc->uc_mcontext.sc_ip; |
| 1145 | switch (host_signum) { |
| 1146 | case SIGILL: |
| 1147 | case SIGFPE: |
| 1148 | case SIGSEGV: |
| 1149 | case SIGBUS: |
| 1150 | case SIGTRAP: |
| 1151 | if (info->si_code && (info->si_flags & __ISR_VALID)) |
| 1152 | /* ISR.W (write-access) is bit 33: */ |
| 1153 | is_write = (info->si_isr >> 33) & 1; |
| 1154 | break; |
| 1155 | |
| 1156 | default: |
| 1157 | break; |
| 1158 | } |
| 1159 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1160 | is_write, |
| 1161 | &uc->uc_sigmask, puc); |
| 1162 | } |
| 1163 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1164 | #else |
| 1165 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 1166 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1167 | |
| 1168 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 1169 | |
| 1170 | #endif /* !defined(CONFIG_SOFTMMU) */ |