bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 19 | */ |
| 20 | #include "exec-i386.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 21 | #include "disas.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 22 | |
bellard | dc99065 | 2003-03-19 00:00:28 +0000 | [diff] [blame] | 23 | //#define DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 24 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 25 | |
| 26 | /* main execution loop */ |
| 27 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 28 | int cpu_x86_exec(CPUX86State *env1) |
| 29 | { |
| 30 | int saved_T0, saved_T1, saved_A0; |
| 31 | CPUX86State *saved_env; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 32 | #ifdef reg_EAX |
| 33 | int saved_EAX; |
| 34 | #endif |
| 35 | #ifdef reg_ECX |
| 36 | int saved_ECX; |
| 37 | #endif |
| 38 | #ifdef reg_EDX |
| 39 | int saved_EDX; |
| 40 | #endif |
| 41 | #ifdef reg_EBX |
| 42 | int saved_EBX; |
| 43 | #endif |
| 44 | #ifdef reg_ESP |
| 45 | int saved_ESP; |
| 46 | #endif |
| 47 | #ifdef reg_EBP |
| 48 | int saved_EBP; |
| 49 | #endif |
| 50 | #ifdef reg_ESI |
| 51 | int saved_ESI; |
| 52 | #endif |
| 53 | #ifdef reg_EDI |
| 54 | int saved_EDI; |
| 55 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 56 | #ifdef __sparc__ |
| 57 | int saved_i7, tmp_T0; |
| 58 | #endif |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 59 | int code_gen_size, ret; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 60 | void (*gen_func)(void); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 61 | TranslationBlock *tb, **ptb; |
bellard | dab2ed9 | 2003-03-22 15:23:14 +0000 | [diff] [blame] | 62 | uint8_t *tc_ptr, *cs_base, *pc; |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 63 | unsigned int flags; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 64 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 65 | /* first we save global registers */ |
| 66 | saved_T0 = T0; |
| 67 | saved_T1 = T1; |
| 68 | saved_A0 = A0; |
| 69 | saved_env = env; |
| 70 | env = env1; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 71 | #ifdef reg_EAX |
| 72 | saved_EAX = EAX; |
| 73 | EAX = env->regs[R_EAX]; |
| 74 | #endif |
| 75 | #ifdef reg_ECX |
| 76 | saved_ECX = ECX; |
| 77 | ECX = env->regs[R_ECX]; |
| 78 | #endif |
| 79 | #ifdef reg_EDX |
| 80 | saved_EDX = EDX; |
| 81 | EDX = env->regs[R_EDX]; |
| 82 | #endif |
| 83 | #ifdef reg_EBX |
| 84 | saved_EBX = EBX; |
| 85 | EBX = env->regs[R_EBX]; |
| 86 | #endif |
| 87 | #ifdef reg_ESP |
| 88 | saved_ESP = ESP; |
| 89 | ESP = env->regs[R_ESP]; |
| 90 | #endif |
| 91 | #ifdef reg_EBP |
| 92 | saved_EBP = EBP; |
| 93 | EBP = env->regs[R_EBP]; |
| 94 | #endif |
| 95 | #ifdef reg_ESI |
| 96 | saved_ESI = ESI; |
| 97 | ESI = env->regs[R_ESI]; |
| 98 | #endif |
| 99 | #ifdef reg_EDI |
| 100 | saved_EDI = EDI; |
| 101 | EDI = env->regs[R_EDI]; |
| 102 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 103 | #ifdef __sparc__ |
| 104 | /* we also save i7 because longjmp may not restore it */ |
| 105 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 106 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 107 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 108 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 109 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 110 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 111 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 112 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 113 | env->interrupt_request = 0; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 114 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 115 | /* prepare setjmp context for exception handling */ |
| 116 | if (setjmp(env->jmp_env) == 0) { |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 117 | T0 = 0; /* force lookup of first TB */ |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 118 | for(;;) { |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 119 | #ifdef __sparc__ |
| 120 | /* g1 can be modified by some libc? functions */ |
| 121 | tmp_T0 = T0; |
| 122 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 123 | if (env->interrupt_request) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 124 | env->exception_index = EXCP_INTERRUPT; |
| 125 | cpu_loop_exit(); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 126 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 127 | #ifdef DEBUG_EXEC |
| 128 | if (loglevel) { |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 129 | /* XXX: save all volatile state in cpu state */ |
| 130 | /* restore flags in standard format */ |
| 131 | env->regs[R_EAX] = EAX; |
| 132 | env->regs[R_EBX] = EBX; |
| 133 | env->regs[R_ECX] = ECX; |
| 134 | env->regs[R_EDX] = EDX; |
| 135 | env->regs[R_ESI] = ESI; |
| 136 | env->regs[R_EDI] = EDI; |
| 137 | env->regs[R_EBP] = EBP; |
| 138 | env->regs[R_ESP] = ESP; |
| 139 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 140 | cpu_x86_dump_state(env, logfile, 0); |
| 141 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 142 | } |
| 143 | #endif |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 144 | /* we compute the CPU state. We assume it will not |
| 145 | change during the whole generated block. */ |
| 146 | flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; |
bellard | dab2ed9 | 2003-03-22 15:23:14 +0000 | [diff] [blame] | 147 | flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 148 | flags |= (((unsigned long)env->seg_cache[R_DS].base | |
| 149 | (unsigned long)env->seg_cache[R_ES].base | |
| 150 | (unsigned long)env->seg_cache[R_SS].base) != 0) << |
| 151 | GEN_FLAG_ADDSEG_SHIFT; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 152 | if (!(env->eflags & VM_MASK)) { |
| 153 | flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT; |
| 154 | } else { |
| 155 | /* NOTE: a dummy CPL is kept */ |
| 156 | flags |= (1 << GEN_FLAG_VM_SHIFT); |
| 157 | flags |= (3 << GEN_FLAG_CPL_SHIFT); |
| 158 | } |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 159 | flags |= (env->eflags & (IOPL_MASK | TF_MASK)); |
bellard | dab2ed9 | 2003-03-22 15:23:14 +0000 | [diff] [blame] | 160 | cs_base = env->seg_cache[R_CS].base; |
| 161 | pc = cs_base + env->eip; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 162 | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
| 163 | flags); |
| 164 | if (!tb) { |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 165 | spin_lock(&tb_lock); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 166 | /* if no translated code available, then translate it now */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 167 | tb = tb_alloc((unsigned long)pc); |
| 168 | if (!tb) { |
| 169 | /* flush must be done */ |
| 170 | tb_flush(); |
| 171 | /* cannot fail at this point */ |
| 172 | tb = tb_alloc((unsigned long)pc); |
| 173 | /* don't forget to invalidate previous TB info */ |
| 174 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
| 175 | T0 = 0; |
| 176 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 177 | tc_ptr = code_gen_ptr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 178 | tb->tc_ptr = tc_ptr; |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 179 | tb->cs_base = (unsigned long)cs_base; |
| 180 | tb->flags = flags; |
| 181 | ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 182 | /* if invalid instruction, signal it */ |
| 183 | if (ret != 0) { |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 184 | /* NOTE: the tb is allocated but not linked, so we |
| 185 | can leave it */ |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 186 | spin_unlock(&tb_lock); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 187 | raise_exception(EXCP06_ILLOP); |
| 188 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 189 | *ptb = tb; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 190 | tb->hash_next = NULL; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 191 | tb_link(tb); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 192 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 193 | spin_unlock(&tb_lock); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 194 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 195 | #ifdef DEBUG_EXEC |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 196 | if (loglevel) { |
| 197 | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", |
| 198 | (long)tb->tc_ptr, (long)tb->pc, |
| 199 | lookup_symbol((void *)tb->pc)); |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 200 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 201 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 202 | #ifdef __sparc__ |
| 203 | T0 = tmp_T0; |
| 204 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 205 | /* see if we can patch the calling TB */ |
| 206 | if (T0 != 0 && !(env->eflags & TF_MASK)) { |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 207 | spin_lock(&tb_lock); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 208 | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 209 | spin_unlock(&tb_lock); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 210 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 211 | tc_ptr = tb->tc_ptr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 212 | |
| 213 | /* execute the generated code */ |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 214 | gen_func = (void *)tc_ptr; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 215 | #if defined(__sparc__) |
bellard | ae22853 | 2003-05-13 18:59:59 +0000 | [diff] [blame] | 216 | __asm__ __volatile__("call %0\n\t" |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 217 | "mov %%o7,%%i0" |
bellard | ae22853 | 2003-05-13 18:59:59 +0000 | [diff] [blame] | 218 | : /* no outputs */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 219 | : "r" (gen_func) |
bellard | ae22853 | 2003-05-13 18:59:59 +0000 | [diff] [blame] | 220 | : "i0", "i1", "i2", "i3", "i4", "i5"); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 221 | #elif defined(__arm__) |
| 222 | asm volatile ("mov pc, %0\n\t" |
| 223 | ".global exec_loop\n\t" |
| 224 | "exec_loop:\n\t" |
| 225 | : /* no outputs */ |
| 226 | : "r" (gen_func) |
| 227 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
bellard | ae22853 | 2003-05-13 18:59:59 +0000 | [diff] [blame] | 228 | #else |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 229 | gen_func(); |
bellard | ae22853 | 2003-05-13 18:59:59 +0000 | [diff] [blame] | 230 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 231 | } |
| 232 | } |
| 233 | ret = env->exception_index; |
| 234 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 235 | /* restore flags in standard format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 236 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 237 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 238 | /* restore global registers */ |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 239 | #ifdef reg_EAX |
| 240 | EAX = saved_EAX; |
| 241 | #endif |
| 242 | #ifdef reg_ECX |
| 243 | ECX = saved_ECX; |
| 244 | #endif |
| 245 | #ifdef reg_EDX |
| 246 | EDX = saved_EDX; |
| 247 | #endif |
| 248 | #ifdef reg_EBX |
| 249 | EBX = saved_EBX; |
| 250 | #endif |
| 251 | #ifdef reg_ESP |
| 252 | ESP = saved_ESP; |
| 253 | #endif |
| 254 | #ifdef reg_EBP |
| 255 | EBP = saved_EBP; |
| 256 | #endif |
| 257 | #ifdef reg_ESI |
| 258 | ESI = saved_ESI; |
| 259 | #endif |
| 260 | #ifdef reg_EDI |
| 261 | EDI = saved_EDI; |
| 262 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 263 | #ifdef __sparc__ |
| 264 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 265 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 266 | T0 = saved_T0; |
| 267 | T1 = saved_T1; |
| 268 | A0 = saved_A0; |
| 269 | env = saved_env; |
| 270 | return ret; |
| 271 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 272 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 273 | void cpu_x86_interrupt(CPUX86State *s) |
| 274 | { |
| 275 | s->interrupt_request = 1; |
| 276 | } |
| 277 | |
| 278 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 279 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 280 | { |
| 281 | CPUX86State *saved_env; |
| 282 | |
| 283 | saved_env = env; |
| 284 | env = s; |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 285 | if (env->eflags & VM_MASK) { |
| 286 | SegmentCache *sc; |
| 287 | selector &= 0xffff; |
| 288 | sc = &env->seg_cache[seg_reg]; |
| 289 | /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded, |
| 290 | so we must load them here */ |
| 291 | sc->base = (void *)(selector << 4); |
| 292 | sc->limit = 0xffff; |
| 293 | sc->seg_32bit = 0; |
| 294 | env->segs[seg_reg] = selector; |
| 295 | } else { |
| 296 | load_seg(seg_reg, selector, 0); |
| 297 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 298 | env = saved_env; |
| 299 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 300 | |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 301 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 302 | { |
| 303 | CPUX86State *saved_env; |
| 304 | |
| 305 | saved_env = env; |
| 306 | env = s; |
| 307 | |
| 308 | helper_fsave(ptr, data32); |
| 309 | |
| 310 | env = saved_env; |
| 311 | } |
| 312 | |
| 313 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 314 | { |
| 315 | CPUX86State *saved_env; |
| 316 | |
| 317 | saved_env = env; |
| 318 | env = s; |
| 319 | |
| 320 | helper_frstor(ptr, data32); |
| 321 | |
| 322 | env = saved_env; |
| 323 | } |
| 324 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 325 | #undef EAX |
| 326 | #undef ECX |
| 327 | #undef EDX |
| 328 | #undef EBX |
| 329 | #undef ESP |
| 330 | #undef EBP |
| 331 | #undef ESI |
| 332 | #undef EDI |
| 333 | #undef EIP |
| 334 | #include <signal.h> |
| 335 | #include <sys/ucontext.h> |
| 336 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 337 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 338 | the effective address of the memory exception. 'is_write' is 1 if a |
| 339 | write caused the exception and otherwise 0'. 'old_set' is the |
| 340 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 341 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 342 | int is_write, sigset_t *old_set) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 343 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 344 | TranslationBlock *tb; |
| 345 | int ret; |
| 346 | uint32_t found_pc; |
| 347 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 348 | #if defined(DEBUG_SIGNAL) |
| 349 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n", |
| 350 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 351 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 352 | /* XXX: locking issue */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 353 | if (is_write && page_unprotect(address)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 354 | return 1; |
| 355 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 356 | tb = tb_find_pc(pc); |
| 357 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 358 | /* the PC is inside the translated code. It means that we have |
| 359 | a virtual CPU fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 360 | ret = cpu_x86_search_pc(tb, &found_pc, pc); |
| 361 | if (ret < 0) |
| 362 | return 0; |
| 363 | env->eip = found_pc - tb->cs_base; |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 364 | env->cr2 = address; |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 365 | /* we restore the process signal mask as the sigreturn should |
| 366 | do it (XXX: use sigsetjmp) */ |
| 367 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 368 | raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 369 | /* never comes here */ |
| 370 | return 1; |
| 371 | } else { |
| 372 | return 0; |
| 373 | } |
| 374 | } |
| 375 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 376 | #if defined(__i386__) |
| 377 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 378 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
| 379 | void *puc) |
| 380 | { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 381 | struct ucontext *uc = puc; |
| 382 | unsigned long pc; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 383 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 384 | #ifndef REG_EIP |
| 385 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 386 | #define REG_EIP EIP |
| 387 | #define REG_ERR ERR |
| 388 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 389 | #endif |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 390 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 391 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 392 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
| 393 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 394 | &uc->uc_sigmask); |
| 395 | } |
| 396 | |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 397 | #elif defined(__powerpc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 398 | |
| 399 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
| 400 | void *puc) |
| 401 | { |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 402 | struct ucontext *uc = puc; |
| 403 | struct pt_regs *regs = uc->uc_mcontext.regs; |
| 404 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 405 | int is_write; |
| 406 | |
| 407 | pc = regs->nip; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 408 | is_write = 0; |
| 409 | #if 0 |
| 410 | /* ppc 4xx case */ |
| 411 | if (regs->dsisr & 0x00800000) |
| 412 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 413 | #else |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 414 | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
| 415 | is_write = 1; |
| 416 | #endif |
| 417 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 418 | is_write, &uc->uc_sigmask); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 419 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 420 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 421 | #elif defined(__alpha__) |
| 422 | |
| 423 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
| 424 | void *puc) |
| 425 | { |
| 426 | struct ucontext *uc = puc; |
| 427 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 428 | uint32_t insn = *pc; |
| 429 | int is_write = 0; |
| 430 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 431 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 432 | switch (insn >> 26) { |
| 433 | case 0x0d: // stw |
| 434 | case 0x0e: // stb |
| 435 | case 0x0f: // stq_u |
| 436 | case 0x24: // stf |
| 437 | case 0x25: // stg |
| 438 | case 0x26: // sts |
| 439 | case 0x27: // stt |
| 440 | case 0x2c: // stl |
| 441 | case 0x2d: // stq |
| 442 | case 0x2e: // stl_c |
| 443 | case 0x2f: // stq_c |
| 444 | is_write = 1; |
| 445 | } |
| 446 | |
| 447 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 448 | is_write, &uc->uc_sigmask); |
| 449 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame^] | 450 | #elif defined(__sparc__) |
| 451 | |
| 452 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
| 453 | void *puc) |
| 454 | { |
| 455 | uint32_t *regs = (uint32_t *)(info + 1); |
| 456 | void *sigmask = (regs + 20); |
| 457 | unsigned long pc; |
| 458 | int is_write; |
| 459 | uint32_t insn; |
| 460 | |
| 461 | /* XXX: is there a standard glibc define ? */ |
| 462 | pc = regs[1]; |
| 463 | /* XXX: need kernel patch to get write flag faster */ |
| 464 | is_write = 0; |
| 465 | insn = *(uint32_t *)pc; |
| 466 | if ((insn >> 30) == 3) { |
| 467 | switch((insn >> 19) & 0x3f) { |
| 468 | case 0x05: // stb |
| 469 | case 0x06: // sth |
| 470 | case 0x04: // st |
| 471 | case 0x07: // std |
| 472 | case 0x24: // stf |
| 473 | case 0x27: // stdf |
| 474 | case 0x25: // stfsr |
| 475 | is_write = 1; |
| 476 | break; |
| 477 | } |
| 478 | } |
| 479 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 480 | is_write, sigmask); |
| 481 | } |
| 482 | |
| 483 | #elif defined(__arm__) |
| 484 | |
| 485 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
| 486 | void *puc) |
| 487 | { |
| 488 | struct ucontext *uc = puc; |
| 489 | unsigned long pc; |
| 490 | int is_write; |
| 491 | |
| 492 | pc = uc->uc_mcontext.gregs[R15]; |
| 493 | /* XXX: compute is_write */ |
| 494 | is_write = 0; |
| 495 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 496 | is_write, |
| 497 | &uc->uc_sigmask); |
| 498 | } |
| 499 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 500 | #else |
| 501 | |
| 502 | #error CPU specific signal handler needed |
| 503 | |
| 504 | #endif |