bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 18 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 20 | #include "exec.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 21 | #include "disas.h" |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 22 | #include "tcg.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 23 | #include "kvm.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 24 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 25 | #if !defined(CONFIG_SOFTMMU) |
| 26 | #undef EAX |
| 27 | #undef ECX |
| 28 | #undef EDX |
| 29 | #undef EBX |
| 30 | #undef ESP |
| 31 | #undef EBP |
| 32 | #undef ESI |
| 33 | #undef EDI |
| 34 | #undef EIP |
| 35 | #include <signal.h> |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 36 | #ifdef __linux__ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 37 | #include <sys/ucontext.h> |
| 38 | #endif |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 39 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 40 | |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 41 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 42 | // Work around ugly bugs in glibc that mangle global register contents |
| 43 | #undef env |
| 44 | #define env cpu_single_env |
| 45 | #endif |
| 46 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 47 | int tb_invalidated_flag; |
| 48 | |
Juan Quintela | f0667e6 | 2009-07-27 16:13:05 +0200 | [diff] [blame] | 49 | //#define CONFIG_DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 50 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 51 | |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 52 | int qemu_cpu_has_work(CPUState *env) |
| 53 | { |
| 54 | return cpu_has_work(env); |
| 55 | } |
| 56 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 57 | void cpu_loop_exit(void) |
| 58 | { |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 59 | /* NOTE: the register at this point must be saved by hand because |
| 60 | longjmp restore them */ |
| 61 | regs_to_env(); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 62 | longjmp(env->jmp_env, 1); |
| 63 | } |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 64 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 65 | /* exit the current TB from a signal handler. The host registers are |
| 66 | restored in a state compatible with the CPU emulator |
| 67 | */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 68 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 69 | { |
| 70 | #if !defined(CONFIG_SOFTMMU) |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 71 | #ifdef __linux__ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 72 | struct ucontext *uc = puc; |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 73 | #elif defined(__OpenBSD__) |
| 74 | struct sigcontext *uc = puc; |
| 75 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 76 | #endif |
| 77 | |
| 78 | env = env1; |
| 79 | |
| 80 | /* XXX: restore cpu registers saved in host registers */ |
| 81 | |
| 82 | #if !defined(CONFIG_SOFTMMU) |
| 83 | if (puc) { |
| 84 | /* XXX: use siglongjmp ? */ |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 85 | #ifdef __linux__ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 86 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 87 | #elif defined(__OpenBSD__) |
| 88 | sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); |
| 89 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 90 | } |
| 91 | #endif |
pbrook | 9a3ea65 | 2008-12-19 12:49:13 +0000 | [diff] [blame] | 92 | env->exception_index = -1; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 93 | longjmp(env->jmp_env, 1); |
| 94 | } |
| 95 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 96 | /* Execute the code without caching the generated code. An interpreter |
| 97 | could be used if available. */ |
| 98 | static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb) |
| 99 | { |
| 100 | unsigned long next_tb; |
| 101 | TranslationBlock *tb; |
| 102 | |
| 103 | /* Should never happen. |
| 104 | We only end up here when an existing TB is too long. */ |
| 105 | if (max_cycles > CF_COUNT_MASK) |
| 106 | max_cycles = CF_COUNT_MASK; |
| 107 | |
| 108 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, |
| 109 | max_cycles); |
| 110 | env->current_tb = tb; |
| 111 | /* execute the generated code */ |
| 112 | next_tb = tcg_qemu_tb_exec(tb->tc_ptr); |
| 113 | |
| 114 | if ((next_tb & 3) == 2) { |
| 115 | /* Restore PC. This may happen if async event occurs before |
| 116 | the TB starts executing. */ |
aliguori | 622ed36 | 2008-11-18 19:36:03 +0000 | [diff] [blame] | 117 | cpu_pc_from_tb(env, tb); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 118 | } |
| 119 | tb_phys_invalidate(tb, -1); |
| 120 | tb_free(tb); |
| 121 | } |
| 122 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 123 | static TranslationBlock *tb_find_slow(target_ulong pc, |
| 124 | target_ulong cs_base, |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 125 | uint64_t flags) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 126 | { |
| 127 | TranslationBlock *tb, **ptb1; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 128 | unsigned int h; |
| 129 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 130 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 131 | tb_invalidated_flag = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 132 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 133 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 134 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 135 | /* find translated block using physical mappings */ |
| 136 | phys_pc = get_phys_addr_code(env, pc); |
| 137 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 138 | phys_page2 = -1; |
| 139 | h = tb_phys_hash_func(phys_pc); |
| 140 | ptb1 = &tb_phys_hash[h]; |
| 141 | for(;;) { |
| 142 | tb = *ptb1; |
| 143 | if (!tb) |
| 144 | goto not_found; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 145 | if (tb->pc == pc && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 146 | tb->page_addr[0] == phys_page1 && |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 147 | tb->cs_base == cs_base && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 148 | tb->flags == flags) { |
| 149 | /* check next page if needed */ |
| 150 | if (tb->page_addr[1] != -1) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 151 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 152 | TARGET_PAGE_SIZE; |
| 153 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 154 | if (tb->page_addr[1] == phys_page2) |
| 155 | goto found; |
| 156 | } else { |
| 157 | goto found; |
| 158 | } |
| 159 | } |
| 160 | ptb1 = &tb->phys_hash_next; |
| 161 | } |
| 162 | not_found: |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 163 | /* if no translated code available, then translate it now */ |
| 164 | tb = tb_gen_code(env, pc, cs_base, flags, 0); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 165 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 166 | found: |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 167 | /* we add the TB in the virtual pc hash table */ |
| 168 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 169 | return tb; |
| 170 | } |
| 171 | |
| 172 | static inline TranslationBlock *tb_find_fast(void) |
| 173 | { |
| 174 | TranslationBlock *tb; |
| 175 | target_ulong cs_base, pc; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 176 | int flags; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 177 | |
| 178 | /* we record a subset of the CPU state. It will |
| 179 | always be the same before a given translated block |
| 180 | is executed. */ |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 181 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bellard | bce6184 | 2008-02-01 22:18:51 +0000 | [diff] [blame] | 182 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 183 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
| 184 | tb->flags != flags)) { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 185 | tb = tb_find_slow(pc, cs_base, flags); |
| 186 | } |
| 187 | return tb; |
| 188 | } |
| 189 | |
aliguori | dde2367 | 2008-11-18 20:50:36 +0000 | [diff] [blame] | 190 | static CPUDebugExcpHandler *debug_excp_handler; |
| 191 | |
| 192 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) |
| 193 | { |
| 194 | CPUDebugExcpHandler *old_handler = debug_excp_handler; |
| 195 | |
| 196 | debug_excp_handler = handler; |
| 197 | return old_handler; |
| 198 | } |
| 199 | |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 200 | static void cpu_handle_debug_exception(CPUState *env) |
| 201 | { |
| 202 | CPUWatchpoint *wp; |
| 203 | |
| 204 | if (!env->watchpoint_hit) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 205 | TAILQ_FOREACH(wp, &env->watchpoints, entry) |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 206 | wp->flags &= ~BP_WATCHPOINT_HIT; |
aliguori | dde2367 | 2008-11-18 20:50:36 +0000 | [diff] [blame] | 207 | |
| 208 | if (debug_excp_handler) |
| 209 | debug_excp_handler(env); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 210 | } |
| 211 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 212 | /* main execution loop */ |
| 213 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 214 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 215 | { |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 216 | #define DECLARE_HOST_REGS 1 |
| 217 | #include "hostregs_helper.h" |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 218 | int ret, interrupt_request; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 219 | TranslationBlock *tb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 220 | uint8_t *tc_ptr; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 221 | unsigned long next_tb; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 222 | |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 223 | if (cpu_halted(env1) == EXCP_HALTED) |
| 224 | return EXCP_HALTED; |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 225 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 226 | cpu_single_env = env1; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 227 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 228 | /* first we save global registers */ |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 229 | #define SAVE_HOST_REGS 1 |
| 230 | #include "hostregs_helper.h" |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 231 | env = env1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 232 | |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 233 | env_to_regs(); |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 234 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 235 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 236 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 237 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 238 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 239 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 240 | #elif defined(TARGET_SPARC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 241 | #elif defined(TARGET_M68K) |
| 242 | env->cc_op = CC_OP_FLAGS; |
| 243 | env->cc_dest = env->sr & 0xf; |
| 244 | env->cc_x = (env->sr >> 4) & 1; |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 245 | #elif defined(TARGET_ALPHA) |
| 246 | #elif defined(TARGET_ARM) |
| 247 | #elif defined(TARGET_PPC) |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 248 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 249 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 250 | #elif defined(TARGET_SH4) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 251 | #elif defined(TARGET_CRIS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 252 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 253 | #else |
| 254 | #error unsupported target CPU |
| 255 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 256 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 257 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 258 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 259 | for(;;) { |
| 260 | if (setjmp(env->jmp_env) == 0) { |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 261 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 9ddff3d | 2009-04-04 07:41:20 +0000 | [diff] [blame] | 262 | #undef env |
| 263 | env = cpu_single_env; |
| 264 | #define env cpu_single_env |
| 265 | #endif |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 266 | env->current_tb = NULL; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 267 | /* if an exception is pending, we execute it here */ |
| 268 | if (env->exception_index >= 0) { |
| 269 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 270 | /* exit request from the cpu execution loop */ |
| 271 | ret = env->exception_index; |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 272 | if (ret == EXCP_DEBUG) |
| 273 | cpu_handle_debug_exception(env); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 274 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 275 | } else { |
| 276 | #if defined(CONFIG_USER_ONLY) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 277 | /* if user mode only, we simulate a fake exception |
ths | 9f08349 | 2006-12-07 18:28:42 +0000 | [diff] [blame] | 278 | which will be handled outside the cpu execution |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 279 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 280 | #if defined(TARGET_I386) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 281 | do_interrupt_user(env->exception_index, |
| 282 | env->exception_is_int, |
| 283 | env->error_code, |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 284 | env->exception_next_eip); |
bellard | eba0162 | 2008-05-12 12:04:40 +0000 | [diff] [blame] | 285 | /* successfully delivered */ |
| 286 | env->old_exception = -1; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 287 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 288 | ret = env->exception_index; |
| 289 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 290 | #else |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 291 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 292 | /* simulate a real cpu exception. On i386, it can |
| 293 | trigger new exceptions, but we do not handle |
| 294 | double or triple faults yet. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 295 | do_interrupt(env->exception_index, |
| 296 | env->exception_is_int, |
| 297 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 298 | env->exception_next_eip, 0); |
ths | 678dde1 | 2007-03-31 20:28:52 +0000 | [diff] [blame] | 299 | /* successfully delivered */ |
| 300 | env->old_exception = -1; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 301 | #elif defined(TARGET_PPC) |
| 302 | do_interrupt(env); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 303 | #elif defined(TARGET_MICROBLAZE) |
| 304 | do_interrupt(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 305 | #elif defined(TARGET_MIPS) |
| 306 | do_interrupt(env); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 307 | #elif defined(TARGET_SPARC) |
blueswir1 | f2bc7e7 | 2008-05-27 17:35:30 +0000 | [diff] [blame] | 308 | do_interrupt(env); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 309 | #elif defined(TARGET_ARM) |
| 310 | do_interrupt(env); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 311 | #elif defined(TARGET_SH4) |
| 312 | do_interrupt(env); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 313 | #elif defined(TARGET_ALPHA) |
| 314 | do_interrupt(env); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 315 | #elif defined(TARGET_CRIS) |
| 316 | do_interrupt(env); |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 317 | #elif defined(TARGET_M68K) |
| 318 | do_interrupt(0); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 319 | #endif |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 320 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 321 | } |
| 322 | env->exception_index = -1; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 323 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 324 | |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 325 | if (kvm_enabled()) { |
aliguori | becfc39 | 2008-11-10 15:55:14 +0000 | [diff] [blame] | 326 | kvm_cpu_exec(env); |
| 327 | longjmp(env->jmp_env, 1); |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 328 | } |
| 329 | |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 330 | next_tb = 0; /* force lookup of first TB */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 331 | for(;;) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 332 | interrupt_request = env->interrupt_request; |
malc | e1638bd | 2008-11-06 18:54:46 +0000 | [diff] [blame] | 333 | if (unlikely(interrupt_request)) { |
| 334 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { |
| 335 | /* Mask out external interrupts for this step. */ |
| 336 | interrupt_request &= ~(CPU_INTERRUPT_HARD | |
| 337 | CPU_INTERRUPT_FIQ | |
| 338 | CPU_INTERRUPT_SMI | |
| 339 | CPU_INTERRUPT_NMI); |
| 340 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 341 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
| 342 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
| 343 | env->exception_index = EXCP_DEBUG; |
| 344 | cpu_loop_exit(); |
| 345 | } |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 346 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 347 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
| 348 | defined(TARGET_MICROBLAZE) |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 349 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
| 350 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 351 | env->halted = 1; |
| 352 | env->exception_index = EXCP_HLT; |
| 353 | cpu_loop_exit(); |
| 354 | } |
| 355 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 356 | #if defined(TARGET_I386) |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 357 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
| 358 | svm_check_intercept(SVM_EXIT_INIT); |
| 359 | do_cpu_init(env); |
| 360 | env->exception_index = EXCP_HALTED; |
| 361 | cpu_loop_exit(); |
| 362 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { |
| 363 | do_cpu_sipi(env); |
| 364 | } else if (env->hflags2 & HF2_GIF_MASK) { |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 365 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
| 366 | !(env->hflags & HF_SMM_MASK)) { |
| 367 | svm_check_intercept(SVM_EXIT_SMI); |
| 368 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
| 369 | do_smm_enter(); |
| 370 | next_tb = 0; |
| 371 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && |
| 372 | !(env->hflags2 & HF2_NMI_MASK)) { |
| 373 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; |
| 374 | env->hflags2 |= HF2_NMI_MASK; |
| 375 | do_interrupt(EXCP02_NMI, 0, 0, 0, 1); |
| 376 | next_tb = 0; |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 377 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
| 378 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; |
| 379 | do_interrupt(EXCP12_MCHK, 0, 0, 0, 0); |
| 380 | next_tb = 0; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 381 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 382 | (((env->hflags2 & HF2_VINTR_MASK) && |
| 383 | (env->hflags2 & HF2_HIF_MASK)) || |
| 384 | (!(env->hflags2 & HF2_VINTR_MASK) && |
| 385 | (env->eflags & IF_MASK && |
| 386 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { |
| 387 | int intno; |
| 388 | svm_check_intercept(SVM_EXIT_INTR); |
| 389 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); |
| 390 | intno = cpu_get_pic_interrupt(env); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 391 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 392 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 9ddff3d | 2009-04-04 07:41:20 +0000 | [diff] [blame] | 393 | #undef env |
| 394 | env = cpu_single_env; |
| 395 | #define env cpu_single_env |
| 396 | #endif |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 397 | do_interrupt(intno, 0, 0, 0, 1); |
| 398 | /* ensure that no TB jump will be modified as |
| 399 | the program flow was changed */ |
| 400 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 401 | #if !defined(CONFIG_USER_ONLY) |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 402 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
| 403 | (env->eflags & IF_MASK) && |
| 404 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
| 405 | int intno; |
| 406 | /* FIXME: this should respect TPR */ |
| 407 | svm_check_intercept(SVM_EXIT_VINTR); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 408 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 409 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 410 | do_interrupt(intno, 0, 0, 0, 1); |
aurel32 | d40c54d | 2008-12-13 12:33:02 +0000 | [diff] [blame] | 411 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 412 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 413 | #endif |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 414 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 415 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 416 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 417 | #if 0 |
| 418 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
| 419 | cpu_ppc_reset(env); |
| 420 | } |
| 421 | #endif |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 422 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 423 | ppc_hw_interrupt(env); |
| 424 | if (env->pending_interrupts == 0) |
| 425 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 426 | next_tb = 0; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 427 | } |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 428 | #elif defined(TARGET_MICROBLAZE) |
| 429 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
| 430 | && (env->sregs[SR_MSR] & MSR_IE) |
| 431 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) |
| 432 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { |
| 433 | env->exception_index = EXCP_IRQ; |
| 434 | do_interrupt(env); |
| 435 | next_tb = 0; |
| 436 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 437 | #elif defined(TARGET_MIPS) |
| 438 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 439 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 440 | (env->CP0_Status & (1 << CP0St_IE)) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 441 | !(env->CP0_Status & (1 << CP0St_EXL)) && |
| 442 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 443 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 444 | /* Raise it */ |
| 445 | env->exception_index = EXCP_EXT_INTERRUPT; |
| 446 | env->error_code = 0; |
| 447 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 448 | next_tb = 0; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 449 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 450 | #elif defined(TARGET_SPARC) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 451 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
Igor Kovalenko | 5210977 | 2009-07-12 12:35:31 +0400 | [diff] [blame] | 452 | cpu_interrupts_enabled(env)) { |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 453 | int pil = env->interrupt_index & 15; |
| 454 | int type = env->interrupt_index & 0xf0; |
| 455 | |
| 456 | if (((type == TT_EXTINT) && |
| 457 | (pil == 15 || pil > env->psrpil)) || |
| 458 | type != TT_EXTINT) { |
| 459 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
blueswir1 | f2bc7e7 | 2008-05-27 17:35:30 +0000 | [diff] [blame] | 460 | env->exception_index = env->interrupt_index; |
| 461 | do_interrupt(env); |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 462 | env->interrupt_index = 0; |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 463 | next_tb = 0; |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 464 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 465 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 466 | //do_interrupt(0, 0, 0, 0, 0); |
| 467 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 468 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 469 | #elif defined(TARGET_ARM) |
| 470 | if (interrupt_request & CPU_INTERRUPT_FIQ |
| 471 | && !(env->uncached_cpsr & CPSR_F)) { |
| 472 | env->exception_index = EXCP_FIQ; |
| 473 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 474 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 475 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 476 | /* ARMv7-M interrupt return works by loading a magic value |
| 477 | into the PC. On real hardware the load causes the |
| 478 | return to occur. The qemu implementation performs the |
| 479 | jump normally, then does the exception return when the |
| 480 | CPU tries to execute code at the magic address. |
| 481 | This will cause the magic PC value to be pushed to |
| 482 | the stack if an interrupt occured at the wrong time. |
| 483 | We avoid this by disabling interrupts when |
| 484 | pc contains a magic address. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 485 | if (interrupt_request & CPU_INTERRUPT_HARD |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 486 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
| 487 | || !(env->uncached_cpsr & CPSR_I))) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 488 | env->exception_index = EXCP_IRQ; |
| 489 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 490 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 491 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 492 | #elif defined(TARGET_SH4) |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 493 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 494 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 495 | next_tb = 0; |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 496 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 497 | #elif defined(TARGET_ALPHA) |
| 498 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 499 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 500 | next_tb = 0; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 501 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 502 | #elif defined(TARGET_CRIS) |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 503 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 504 | && (env->pregs[PR_CCS] & I_FLAG)) { |
| 505 | env->exception_index = EXCP_IRQ; |
| 506 | do_interrupt(env); |
| 507 | next_tb = 0; |
| 508 | } |
| 509 | if (interrupt_request & CPU_INTERRUPT_NMI |
| 510 | && (env->pregs[PR_CCS] & M_FLAG)) { |
| 511 | env->exception_index = EXCP_NMI; |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 512 | do_interrupt(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 513 | next_tb = 0; |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 514 | } |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 515 | #elif defined(TARGET_M68K) |
| 516 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 517 | && ((env->sr & SR_I) >> SR_I_SHIFT) |
| 518 | < env->pending_level) { |
| 519 | /* Real hardware gets the interrupt vector via an |
| 520 | IACK cycle at this point. Current emulated |
| 521 | hardware doesn't rely on this, so we |
| 522 | provide/save the vector when the interrupt is |
| 523 | first signalled. */ |
| 524 | env->exception_index = env->pending_vector; |
| 525 | do_interrupt(1); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 526 | next_tb = 0; |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 527 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 528 | #endif |
bellard | 9d05095 | 2006-05-22 22:03:52 +0000 | [diff] [blame] | 529 | /* Don't use the cached interupt_request value, |
| 530 | do_interrupt may have updated the EXITTB flag. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 531 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 532 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 533 | /* ensure that no TB jump will be modified as |
| 534 | the program flow was changed */ |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 535 | next_tb = 0; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 536 | } |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 537 | } |
| 538 | if (unlikely(env->exit_request)) { |
| 539 | env->exit_request = 0; |
| 540 | env->exception_index = EXCP_INTERRUPT; |
| 541 | cpu_loop_exit(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 542 | } |
Juan Quintela | f0667e6 | 2009-07-27 16:13:05 +0200 | [diff] [blame] | 543 | #ifdef CONFIG_DEBUG_EXEC |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 544 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 545 | /* restore flags in standard format */ |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 546 | regs_to_env(); |
| 547 | #if defined(TARGET_I386) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 548 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 549 | log_cpu_state(env, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 550 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 551 | #elif defined(TARGET_ARM) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 552 | log_cpu_state(env, 0); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 553 | #elif defined(TARGET_SPARC) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 554 | log_cpu_state(env, 0); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 555 | #elif defined(TARGET_PPC) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 556 | log_cpu_state(env, 0); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 557 | #elif defined(TARGET_M68K) |
| 558 | cpu_m68k_flush_flags(env, env->cc_op); |
| 559 | env->cc_op = CC_OP_FLAGS; |
| 560 | env->sr = (env->sr & 0xffe0) |
| 561 | | env->cc_dest | (env->cc_x << 4); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 562 | log_cpu_state(env, 0); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 563 | #elif defined(TARGET_MICROBLAZE) |
| 564 | log_cpu_state(env, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 565 | #elif defined(TARGET_MIPS) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 566 | log_cpu_state(env, 0); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 567 | #elif defined(TARGET_SH4) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 568 | log_cpu_state(env, 0); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 569 | #elif defined(TARGET_ALPHA) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 570 | log_cpu_state(env, 0); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 571 | #elif defined(TARGET_CRIS) |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 572 | log_cpu_state(env, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 573 | #else |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 574 | #error unsupported target CPU |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 575 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 576 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 577 | #endif |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 578 | spin_lock(&tb_lock); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 579 | tb = tb_find_fast(); |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 580 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
| 581 | doing it in tb_find_slow */ |
| 582 | if (tb_invalidated_flag) { |
| 583 | /* as some TB could have been invalidated because |
| 584 | of memory exceptions while generating the code, we |
| 585 | must recompute the hash index here */ |
| 586 | next_tb = 0; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 587 | tb_invalidated_flag = 0; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 588 | } |
Juan Quintela | f0667e6 | 2009-07-27 16:13:05 +0200 | [diff] [blame] | 589 | #ifdef CONFIG_DEBUG_EXEC |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 590 | qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 591 | (long)tb->tc_ptr, tb->pc, |
| 592 | lookup_symbol(tb->pc)); |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 593 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 594 | /* see if we can patch the calling TB. When the TB |
| 595 | spans two pages, we cannot safely do a direct |
| 596 | jump. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 597 | { |
Anthony Liguori | 4a1418e | 2009-08-10 17:07:24 -0500 | [diff] [blame] | 598 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 599 | tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 600 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 601 | } |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 602 | spin_unlock(&tb_lock); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 603 | env->current_tb = tb; |
malc | 55e8b85 | 2008-11-04 14:18:13 +0000 | [diff] [blame] | 604 | |
| 605 | /* cpu_interrupt might be called while translating the |
| 606 | TB, but before it is linked into a potentially |
| 607 | infinite loop and becomes env->current_tb. Avoid |
| 608 | starting execution if there is a pending interrupt. */ |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 609 | if (unlikely (env->exit_request)) |
malc | 55e8b85 | 2008-11-04 14:18:13 +0000 | [diff] [blame] | 610 | env->current_tb = NULL; |
| 611 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 612 | while (env->current_tb) { |
| 613 | tc_ptr = tb->tc_ptr; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 614 | /* execute the generated code */ |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 615 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 616 | #undef env |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 617 | env = cpu_single_env; |
blueswir1 | 572a9d4 | 2008-05-17 07:38:10 +0000 | [diff] [blame] | 618 | #define env cpu_single_env |
| 619 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 620 | next_tb = tcg_qemu_tb_exec(tc_ptr); |
| 621 | env->current_tb = NULL; |
| 622 | if ((next_tb & 3) == 2) { |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 623 | /* Instruction counter expired. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 624 | int insns_left; |
| 625 | tb = (TranslationBlock *)(long)(next_tb & ~3); |
| 626 | /* Restore PC. */ |
aliguori | 622ed36 | 2008-11-18 19:36:03 +0000 | [diff] [blame] | 627 | cpu_pc_from_tb(env, tb); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 628 | insns_left = env->icount_decr.u32; |
| 629 | if (env->icount_extra && insns_left >= 0) { |
| 630 | /* Refill decrementer and continue execution. */ |
| 631 | env->icount_extra += insns_left; |
| 632 | if (env->icount_extra > 0xffff) { |
| 633 | insns_left = 0xffff; |
| 634 | } else { |
| 635 | insns_left = env->icount_extra; |
| 636 | } |
| 637 | env->icount_extra -= insns_left; |
| 638 | env->icount_decr.u16.low = insns_left; |
| 639 | } else { |
| 640 | if (insns_left > 0) { |
| 641 | /* Execute remaining instructions. */ |
| 642 | cpu_exec_nocache(insns_left, tb); |
| 643 | } |
| 644 | env->exception_index = EXCP_INTERRUPT; |
| 645 | next_tb = 0; |
| 646 | cpu_loop_exit(); |
| 647 | } |
| 648 | } |
| 649 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 650 | /* reset soft MMU for next block (it can currently |
| 651 | only be set by a memory fault) */ |
ths | 50a518e | 2007-06-03 18:52:15 +0000 | [diff] [blame] | 652 | } /* for(;;) */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 653 | } else { |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 654 | env_to_regs(); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 655 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 656 | } /* for(;;) */ |
| 657 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 658 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 659 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 660 | /* restore flags in standard format */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 661 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 662 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 663 | /* XXX: Save/restore host fpu exception state?. */ |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 664 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 665 | #elif defined(TARGET_PPC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 666 | #elif defined(TARGET_M68K) |
| 667 | cpu_m68k_flush_flags(env, env->cc_op); |
| 668 | env->cc_op = CC_OP_FLAGS; |
| 669 | env->sr = (env->sr & 0xffe0) |
| 670 | | env->cc_dest | (env->cc_x << 4); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 671 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 672 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 673 | #elif defined(TARGET_SH4) |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 674 | #elif defined(TARGET_ALPHA) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 675 | #elif defined(TARGET_CRIS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 676 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 677 | #else |
| 678 | #error unsupported target CPU |
| 679 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 680 | |
| 681 | /* restore global registers */ |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 682 | #include "hostregs_helper.h" |
| 683 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 684 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 685 | cpu_single_env = NULL; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 686 | return ret; |
| 687 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 688 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 689 | /* must only be called from the generated code as an exception can be |
| 690 | generated */ |
| 691 | void tb_invalidate_page_range(target_ulong start, target_ulong end) |
| 692 | { |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 693 | /* XXX: cannot enable it yet because it yields to MMU exception |
| 694 | where NIP != read address on PowerPC */ |
| 695 | #if 0 |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 696 | target_ulong phys_addr; |
| 697 | phys_addr = get_phys_addr_code(env, start); |
| 698 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 699 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 700 | } |
| 701 | |
bellard | 1a18c71 | 2003-10-30 01:07:51 +0000 | [diff] [blame] | 702 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 703 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 704 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 705 | { |
| 706 | CPUX86State *saved_env; |
| 707 | |
| 708 | saved_env = env; |
| 709 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 710 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 711 | selector &= 0xffff; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 712 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 713 | (selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 714 | } else { |
bellard | 5d97559 | 2008-05-12 22:05:33 +0000 | [diff] [blame] | 715 | helper_load_seg(seg_reg, selector); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 716 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 717 | env = saved_env; |
| 718 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 719 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 720 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 721 | { |
| 722 | CPUX86State *saved_env; |
| 723 | |
| 724 | saved_env = env; |
| 725 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 726 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 727 | helper_fsave(ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 728 | |
| 729 | env = saved_env; |
| 730 | } |
| 731 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 732 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 733 | { |
| 734 | CPUX86State *saved_env; |
| 735 | |
| 736 | saved_env = env; |
| 737 | env = s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 738 | |
bellard | 6f12a2a | 2007-11-11 22:16:56 +0000 | [diff] [blame] | 739 | helper_frstor(ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 740 | |
| 741 | env = saved_env; |
| 742 | } |
| 743 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 744 | #endif /* TARGET_I386 */ |
| 745 | |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 746 | #if !defined(CONFIG_SOFTMMU) |
| 747 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 748 | #if defined(TARGET_I386) |
| 749 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 750 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 751 | the effective address of the memory exception. 'is_write' is 1 if a |
| 752 | write caused the exception and otherwise 0'. 'old_set' is the |
| 753 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 754 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 755 | int is_write, sigset_t *old_set, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 756 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 757 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 758 | TranslationBlock *tb; |
| 759 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 760 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 761 | if (cpu_single_env) |
| 762 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 763 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 764 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 765 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 766 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 767 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 768 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 769 | return 1; |
| 770 | } |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 771 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 772 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 773 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 774 | if (ret < 0) |
| 775 | return 0; /* not an MMU fault */ |
| 776 | if (ret == 0) |
| 777 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 778 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 779 | tb = tb_find_pc(pc); |
| 780 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 781 | /* the PC is inside the translated code. It means that we have |
| 782 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 783 | cpu_restore_state(tb, env, pc, puc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 784 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 785 | if (ret == 1) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 786 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 787 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 788 | env->eip, env->cr[2], env->error_code); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 789 | #endif |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 790 | /* we restore the process signal mask as the sigreturn should |
| 791 | do it (XXX: use sigsetjmp) */ |
| 792 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 54ca909 | 2005-12-04 18:46:06 +0000 | [diff] [blame] | 793 | raise_exception_err(env->exception_index, env->error_code); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 794 | } else { |
| 795 | /* activate soft MMU for this block */ |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 796 | env->hflags |= HF_SOFTMMU_MASK; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 797 | cpu_resume_from_signal(env, puc); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 798 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 799 | /* never comes here */ |
| 800 | return 1; |
| 801 | } |
| 802 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 803 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 804 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 805 | int is_write, sigset_t *old_set, |
| 806 | void *puc) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 807 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 808 | TranslationBlock *tb; |
| 809 | int ret; |
| 810 | |
| 811 | if (cpu_single_env) |
| 812 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 813 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 814 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 815 | pc, address, is_write, *(unsigned long *)old_set); |
| 816 | #endif |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 817 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 818 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 819 | return 1; |
| 820 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 821 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 822 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 823 | if (ret < 0) |
| 824 | return 0; /* not an MMU fault */ |
| 825 | if (ret == 0) |
| 826 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 827 | /* now we have a real cpu fault */ |
| 828 | tb = tb_find_pc(pc); |
| 829 | if (tb) { |
| 830 | /* the PC is inside the translated code. It means that we have |
| 831 | a virtual CPU fault */ |
| 832 | cpu_restore_state(tb, env, pc, puc); |
| 833 | } |
| 834 | /* we restore the process signal mask as the sigreturn should |
| 835 | do it (XXX: use sigsetjmp) */ |
| 836 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 837 | cpu_loop_exit(); |
aurel32 | 968c74d | 2008-04-11 04:55:17 +0000 | [diff] [blame] | 838 | /* never comes here */ |
| 839 | return 1; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 840 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 841 | #elif defined(TARGET_SPARC) |
| 842 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 843 | int is_write, sigset_t *old_set, |
| 844 | void *puc) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 845 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 846 | TranslationBlock *tb; |
| 847 | int ret; |
| 848 | |
| 849 | if (cpu_single_env) |
| 850 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 851 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 852 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 853 | pc, address, is_write, *(unsigned long *)old_set); |
| 854 | #endif |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 855 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 856 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 857 | return 1; |
| 858 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 859 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 860 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 861 | if (ret < 0) |
| 862 | return 0; /* not an MMU fault */ |
| 863 | if (ret == 0) |
| 864 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 865 | /* now we have a real cpu fault */ |
| 866 | tb = tb_find_pc(pc); |
| 867 | if (tb) { |
| 868 | /* the PC is inside the translated code. It means that we have |
| 869 | a virtual CPU fault */ |
| 870 | cpu_restore_state(tb, env, pc, puc); |
| 871 | } |
| 872 | /* we restore the process signal mask as the sigreturn should |
| 873 | do it (XXX: use sigsetjmp) */ |
| 874 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 875 | cpu_loop_exit(); |
aurel32 | 968c74d | 2008-04-11 04:55:17 +0000 | [diff] [blame] | 876 | /* never comes here */ |
| 877 | return 1; |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 878 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 879 | #elif defined (TARGET_PPC) |
| 880 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 881 | int is_write, sigset_t *old_set, |
| 882 | void *puc) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 883 | { |
| 884 | TranslationBlock *tb; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 885 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 886 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 887 | if (cpu_single_env) |
| 888 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 889 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 890 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 891 | pc, address, is_write, *(unsigned long *)old_set); |
| 892 | #endif |
| 893 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 894 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 895 | return 1; |
| 896 | } |
| 897 | |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 898 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 899 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 900 | if (ret < 0) |
| 901 | return 0; /* not an MMU fault */ |
| 902 | if (ret == 0) |
| 903 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 904 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 905 | /* now we have a real cpu fault */ |
| 906 | tb = tb_find_pc(pc); |
| 907 | if (tb) { |
| 908 | /* the PC is inside the translated code. It means that we have |
| 909 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 910 | cpu_restore_state(tb, env, pc, puc); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 911 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 912 | if (ret == 1) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 913 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 914 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 915 | env->nip, env->error_code, tb); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 916 | #endif |
| 917 | /* we restore the process signal mask as the sigreturn should |
| 918 | do it (XXX: use sigsetjmp) */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 919 | sigprocmask(SIG_SETMASK, old_set, NULL); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 920 | cpu_loop_exit(); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 921 | } else { |
| 922 | /* activate soft MMU for this block */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 923 | cpu_resume_from_signal(env, puc); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 924 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 925 | /* never comes here */ |
| 926 | return 1; |
| 927 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 928 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 929 | #elif defined(TARGET_M68K) |
| 930 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 931 | int is_write, sigset_t *old_set, |
| 932 | void *puc) |
| 933 | { |
| 934 | TranslationBlock *tb; |
| 935 | int ret; |
| 936 | |
| 937 | if (cpu_single_env) |
| 938 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 939 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 940 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 941 | pc, address, is_write, *(unsigned long *)old_set); |
| 942 | #endif |
| 943 | /* XXX: locking issue */ |
| 944 | if (is_write && page_unprotect(address, pc, puc)) { |
| 945 | return 1; |
| 946 | } |
| 947 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 948 | ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 949 | if (ret < 0) |
| 950 | return 0; /* not an MMU fault */ |
| 951 | if (ret == 0) |
| 952 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 953 | /* now we have a real cpu fault */ |
| 954 | tb = tb_find_pc(pc); |
| 955 | if (tb) { |
| 956 | /* the PC is inside the translated code. It means that we have |
| 957 | a virtual CPU fault */ |
| 958 | cpu_restore_state(tb, env, pc, puc); |
| 959 | } |
| 960 | /* we restore the process signal mask as the sigreturn should |
| 961 | do it (XXX: use sigsetjmp) */ |
| 962 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 963 | cpu_loop_exit(); |
| 964 | /* never comes here */ |
| 965 | return 1; |
| 966 | } |
| 967 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 968 | #elif defined (TARGET_MIPS) |
| 969 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 970 | int is_write, sigset_t *old_set, |
| 971 | void *puc) |
| 972 | { |
| 973 | TranslationBlock *tb; |
| 974 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 975 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 976 | if (cpu_single_env) |
| 977 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 978 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 979 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 980 | pc, address, is_write, *(unsigned long *)old_set); |
| 981 | #endif |
| 982 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 983 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 984 | return 1; |
| 985 | } |
| 986 | |
| 987 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 988 | ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 989 | if (ret < 0) |
| 990 | return 0; /* not an MMU fault */ |
| 991 | if (ret == 0) |
| 992 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 993 | |
| 994 | /* now we have a real cpu fault */ |
| 995 | tb = tb_find_pc(pc); |
| 996 | if (tb) { |
| 997 | /* the PC is inside the translated code. It means that we have |
| 998 | a virtual CPU fault */ |
| 999 | cpu_restore_state(tb, env, pc, puc); |
| 1000 | } |
| 1001 | if (ret == 1) { |
| 1002 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1003 | printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n", |
ths | 1eb5207 | 2007-05-12 16:57:42 +0000 | [diff] [blame] | 1004 | env->PC, env->error_code, tb); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1005 | #endif |
| 1006 | /* we restore the process signal mask as the sigreturn should |
| 1007 | do it (XXX: use sigsetjmp) */ |
| 1008 | sigprocmask(SIG_SETMASK, old_set, NULL); |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 1009 | cpu_loop_exit(); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1010 | } else { |
| 1011 | /* activate soft MMU for this block */ |
| 1012 | cpu_resume_from_signal(env, puc); |
| 1013 | } |
| 1014 | /* never comes here */ |
| 1015 | return 1; |
| 1016 | } |
| 1017 | |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 1018 | #elif defined (TARGET_MICROBLAZE) |
| 1019 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1020 | int is_write, sigset_t *old_set, |
| 1021 | void *puc) |
| 1022 | { |
| 1023 | TranslationBlock *tb; |
| 1024 | int ret; |
| 1025 | |
| 1026 | if (cpu_single_env) |
| 1027 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1028 | #if defined(DEBUG_SIGNAL) |
| 1029 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1030 | pc, address, is_write, *(unsigned long *)old_set); |
| 1031 | #endif |
| 1032 | /* XXX: locking issue */ |
| 1033 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1034 | return 1; |
| 1035 | } |
| 1036 | |
| 1037 | /* see if it is an MMU fault */ |
| 1038 | ret = cpu_mb_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
| 1039 | if (ret < 0) |
| 1040 | return 0; /* not an MMU fault */ |
| 1041 | if (ret == 0) |
| 1042 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1043 | |
| 1044 | /* now we have a real cpu fault */ |
| 1045 | tb = tb_find_pc(pc); |
| 1046 | if (tb) { |
| 1047 | /* the PC is inside the translated code. It means that we have |
| 1048 | a virtual CPU fault */ |
| 1049 | cpu_restore_state(tb, env, pc, puc); |
| 1050 | } |
| 1051 | if (ret == 1) { |
| 1052 | #if 0 |
| 1053 | printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n", |
| 1054 | env->PC, env->error_code, tb); |
| 1055 | #endif |
| 1056 | /* we restore the process signal mask as the sigreturn should |
| 1057 | do it (XXX: use sigsetjmp) */ |
| 1058 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1059 | cpu_loop_exit(); |
| 1060 | } else { |
| 1061 | /* activate soft MMU for this block */ |
| 1062 | cpu_resume_from_signal(env, puc); |
| 1063 | } |
| 1064 | /* never comes here */ |
| 1065 | return 1; |
| 1066 | } |
| 1067 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1068 | #elif defined (TARGET_SH4) |
| 1069 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1070 | int is_write, sigset_t *old_set, |
| 1071 | void *puc) |
| 1072 | { |
| 1073 | TranslationBlock *tb; |
| 1074 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1075 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1076 | if (cpu_single_env) |
| 1077 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1078 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1079 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1080 | pc, address, is_write, *(unsigned long *)old_set); |
| 1081 | #endif |
| 1082 | /* XXX: locking issue */ |
| 1083 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1084 | return 1; |
| 1085 | } |
| 1086 | |
| 1087 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1088 | ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1089 | if (ret < 0) |
| 1090 | return 0; /* not an MMU fault */ |
| 1091 | if (ret == 0) |
| 1092 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1093 | |
| 1094 | /* now we have a real cpu fault */ |
| 1095 | tb = tb_find_pc(pc); |
| 1096 | if (tb) { |
| 1097 | /* the PC is inside the translated code. It means that we have |
| 1098 | a virtual CPU fault */ |
| 1099 | cpu_restore_state(tb, env, pc, puc); |
| 1100 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1101 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1102 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1103 | env->nip, env->error_code, tb); |
| 1104 | #endif |
| 1105 | /* we restore the process signal mask as the sigreturn should |
| 1106 | do it (XXX: use sigsetjmp) */ |
pbrook | 355fb23 | 2006-06-17 19:58:25 +0000 | [diff] [blame] | 1107 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1108 | cpu_loop_exit(); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1109 | /* never comes here */ |
| 1110 | return 1; |
| 1111 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1112 | |
| 1113 | #elif defined (TARGET_ALPHA) |
| 1114 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1115 | int is_write, sigset_t *old_set, |
| 1116 | void *puc) |
| 1117 | { |
| 1118 | TranslationBlock *tb; |
| 1119 | int ret; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1120 | |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1121 | if (cpu_single_env) |
| 1122 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1123 | #if defined(DEBUG_SIGNAL) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1124 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1125 | pc, address, is_write, *(unsigned long *)old_set); |
| 1126 | #endif |
| 1127 | /* XXX: locking issue */ |
| 1128 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1129 | return 1; |
| 1130 | } |
| 1131 | |
| 1132 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1133 | ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1134 | if (ret < 0) |
| 1135 | return 0; /* not an MMU fault */ |
| 1136 | if (ret == 0) |
| 1137 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1138 | |
| 1139 | /* now we have a real cpu fault */ |
| 1140 | tb = tb_find_pc(pc); |
| 1141 | if (tb) { |
| 1142 | /* the PC is inside the translated code. It means that we have |
| 1143 | a virtual CPU fault */ |
| 1144 | cpu_restore_state(tb, env, pc, puc); |
| 1145 | } |
| 1146 | #if 0 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1147 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1148 | env->nip, env->error_code, tb); |
| 1149 | #endif |
| 1150 | /* we restore the process signal mask as the sigreturn should |
| 1151 | do it (XXX: use sigsetjmp) */ |
| 1152 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1153 | cpu_loop_exit(); |
| 1154 | /* never comes here */ |
| 1155 | return 1; |
| 1156 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 1157 | #elif defined (TARGET_CRIS) |
| 1158 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1159 | int is_write, sigset_t *old_set, |
| 1160 | void *puc) |
| 1161 | { |
| 1162 | TranslationBlock *tb; |
| 1163 | int ret; |
| 1164 | |
| 1165 | if (cpu_single_env) |
| 1166 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1167 | #if defined(DEBUG_SIGNAL) |
| 1168 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1169 | pc, address, is_write, *(unsigned long *)old_set); |
| 1170 | #endif |
| 1171 | /* XXX: locking issue */ |
| 1172 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1173 | return 1; |
| 1174 | } |
| 1175 | |
| 1176 | /* see if it is an MMU fault */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1177 | ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 1178 | if (ret < 0) |
| 1179 | return 0; /* not an MMU fault */ |
| 1180 | if (ret == 0) |
| 1181 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1182 | |
| 1183 | /* now we have a real cpu fault */ |
| 1184 | tb = tb_find_pc(pc); |
| 1185 | if (tb) { |
| 1186 | /* the PC is inside the translated code. It means that we have |
| 1187 | a virtual CPU fault */ |
| 1188 | cpu_restore_state(tb, env, pc, puc); |
| 1189 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 1190 | /* we restore the process signal mask as the sigreturn should |
| 1191 | do it (XXX: use sigsetjmp) */ |
| 1192 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1193 | cpu_loop_exit(); |
| 1194 | /* never comes here */ |
| 1195 | return 1; |
| 1196 | } |
| 1197 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1198 | #else |
| 1199 | #error unsupported target CPU |
| 1200 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1201 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1202 | #if defined(__i386__) |
| 1203 | |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1204 | #if defined(__APPLE__) |
| 1205 | # include <sys/ucontext.h> |
| 1206 | |
| 1207 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) |
| 1208 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) |
| 1209 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 1210 | # define MASK_sig(context) ((context)->uc_sigmask) |
| 1211 | #elif defined(__OpenBSD__) |
| 1212 | # define EIP_sig(context) ((context)->sc_eip) |
| 1213 | # define TRAP_sig(context) ((context)->sc_trapno) |
| 1214 | # define ERROR_sig(context) ((context)->sc_err) |
| 1215 | # define MASK_sig(context) ((context)->sc_mask) |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1216 | #else |
| 1217 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) |
| 1218 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 1219 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 1220 | # define MASK_sig(context) ((context)->uc_sigmask) |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1221 | #endif |
| 1222 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1223 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1224 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1225 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1226 | siginfo_t *info = pinfo; |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 1227 | #if defined(__OpenBSD__) |
| 1228 | struct sigcontext *uc = puc; |
| 1229 | #else |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1230 | struct ucontext *uc = puc; |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 1231 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1232 | unsigned long pc; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1233 | int trapno; |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 1234 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1235 | #ifndef REG_EIP |
| 1236 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1237 | #define REG_EIP EIP |
| 1238 | #define REG_ERR ERR |
| 1239 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1240 | #endif |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1241 | pc = EIP_sig(uc); |
| 1242 | trapno = TRAP_sig(uc); |
bellard | ec6338b | 2007-11-08 14:25:03 +0000 | [diff] [blame] | 1243 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1244 | trapno == 0xe ? |
| 1245 | (ERROR_sig(uc) >> 1) & 1 : 0, |
blueswir1 | d39bb24 | 2009-04-10 07:29:34 +0000 | [diff] [blame] | 1246 | &MASK_sig(uc), puc); |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1247 | } |
| 1248 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1249 | #elif defined(__x86_64__) |
| 1250 | |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 1251 | #ifdef __NetBSD__ |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 1252 | #define PC_sig(context) _UC_MACHINE_PC(context) |
| 1253 | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) |
| 1254 | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) |
| 1255 | #define MASK_sig(context) ((context)->uc_sigmask) |
| 1256 | #elif defined(__OpenBSD__) |
| 1257 | #define PC_sig(context) ((context)->sc_rip) |
| 1258 | #define TRAP_sig(context) ((context)->sc_trapno) |
| 1259 | #define ERROR_sig(context) ((context)->sc_err) |
| 1260 | #define MASK_sig(context) ((context)->sc_mask) |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 1261 | #else |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 1262 | #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) |
| 1263 | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 1264 | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
| 1265 | #define MASK_sig(context) ((context)->uc_sigmask) |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 1266 | #endif |
| 1267 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1268 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1269 | void *puc) |
| 1270 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1271 | siginfo_t *info = pinfo; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1272 | unsigned long pc; |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 1273 | #ifdef __NetBSD__ |
| 1274 | ucontext_t *uc = puc; |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 1275 | #elif defined(__OpenBSD__) |
| 1276 | struct sigcontext *uc = puc; |
blueswir1 | b3efe5c | 2008-12-05 17:55:45 +0000 | [diff] [blame] | 1277 | #else |
| 1278 | struct ucontext *uc = puc; |
| 1279 | #endif |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1280 | |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 1281 | pc = PC_sig(uc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1282 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
blueswir1 | d397abb | 2009-04-10 13:00:29 +0000 | [diff] [blame] | 1283 | TRAP_sig(uc) == 0xe ? |
| 1284 | (ERROR_sig(uc) >> 1) & 1 : 0, |
| 1285 | &MASK_sig(uc), puc); |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1286 | } |
| 1287 | |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 1288 | #elif defined(_ARCH_PPC) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1289 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1290 | /*********************************************************************** |
| 1291 | * signal context platform-specific definitions |
| 1292 | * From Wine |
| 1293 | */ |
| 1294 | #ifdef linux |
| 1295 | /* All Registers access - only for local access */ |
| 1296 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) |
| 1297 | /* Gpr Registers access */ |
| 1298 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
| 1299 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 1300 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 1301 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 1302 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 1303 | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 1304 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 1305 | /* Float Registers access */ |
| 1306 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 1307 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 1308 | /* Exception Registers access */ |
| 1309 | # define DAR_sig(context) REG_sig(dar, context) |
| 1310 | # define DSISR_sig(context) REG_sig(dsisr, context) |
| 1311 | # define TRAP_sig(context) REG_sig(trap, context) |
| 1312 | #endif /* linux */ |
| 1313 | |
| 1314 | #ifdef __APPLE__ |
| 1315 | # include <sys/ucontext.h> |
| 1316 | typedef struct ucontext SIGCONTEXT; |
| 1317 | /* All Registers access - only for local access */ |
| 1318 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) |
| 1319 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) |
| 1320 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) |
| 1321 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) |
| 1322 | /* Gpr Registers access */ |
| 1323 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 1324 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 1325 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 1326 | # define CTR_sig(context) REG_sig(ctr, context) |
| 1327 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 1328 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 1329 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 1330 | /* Float Registers access */ |
| 1331 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) |
| 1332 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 1333 | /* Exception Registers access */ |
| 1334 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 1335 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
| 1336 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 1337 | #endif /* __APPLE__ */ |
| 1338 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1339 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1340 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1341 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1342 | siginfo_t *info = pinfo; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1343 | struct ucontext *uc = puc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1344 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1345 | int is_write; |
| 1346 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1347 | pc = IAR_sig(uc); |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1348 | is_write = 0; |
| 1349 | #if 0 |
| 1350 | /* ppc 4xx case */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1351 | if (DSISR_sig(uc) & 0x00800000) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1352 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1353 | #else |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1354 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1355 | is_write = 1; |
| 1356 | #endif |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1357 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1358 | is_write, &uc->uc_sigmask, puc); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1359 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1360 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1361 | #elif defined(__alpha__) |
| 1362 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1363 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1364 | void *puc) |
| 1365 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1366 | siginfo_t *info = pinfo; |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1367 | struct ucontext *uc = puc; |
| 1368 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 1369 | uint32_t insn = *pc; |
| 1370 | int is_write = 0; |
| 1371 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1372 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1373 | switch (insn >> 26) { |
| 1374 | case 0x0d: // stw |
| 1375 | case 0x0e: // stb |
| 1376 | case 0x0f: // stq_u |
| 1377 | case 0x24: // stf |
| 1378 | case 0x25: // stg |
| 1379 | case 0x26: // sts |
| 1380 | case 0x27: // stt |
| 1381 | case 0x2c: // stl |
| 1382 | case 0x2d: // stq |
| 1383 | case 0x2e: // stl_c |
| 1384 | case 0x2f: // stq_c |
| 1385 | is_write = 1; |
| 1386 | } |
| 1387 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1388 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1389 | is_write, &uc->uc_sigmask, puc); |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1390 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1391 | #elif defined(__sparc__) |
| 1392 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1393 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1394 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1395 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1396 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1397 | int is_write; |
| 1398 | uint32_t insn; |
Juan Quintela | dfe5fff | 2009-07-27 16:12:40 +0200 | [diff] [blame] | 1399 | #if !defined(__arch64__) || defined(CONFIG_SOLARIS) |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1400 | uint32_t *regs = (uint32_t *)(info + 1); |
| 1401 | void *sigmask = (regs + 20); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1402 | /* XXX: is there a standard glibc define ? */ |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1403 | unsigned long pc = regs[1]; |
| 1404 | #else |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 1405 | #ifdef __linux__ |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1406 | struct sigcontext *sc = puc; |
| 1407 | unsigned long pc = sc->sigc_regs.tpc; |
| 1408 | void *sigmask = (void *)sc->sigc_mask; |
blueswir1 | 8477850 | 2008-10-26 20:33:16 +0000 | [diff] [blame] | 1409 | #elif defined(__OpenBSD__) |
| 1410 | struct sigcontext *uc = puc; |
| 1411 | unsigned long pc = uc->sc_pc; |
| 1412 | void *sigmask = (void *)(long)uc->sc_mask; |
| 1413 | #endif |
blueswir1 | c9e1e2b | 2008-05-18 06:40:16 +0000 | [diff] [blame] | 1414 | #endif |
| 1415 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1416 | /* XXX: need kernel patch to get write flag faster */ |
| 1417 | is_write = 0; |
| 1418 | insn = *(uint32_t *)pc; |
| 1419 | if ((insn >> 30) == 3) { |
| 1420 | switch((insn >> 19) & 0x3f) { |
| 1421 | case 0x05: // stb |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1422 | case 0x15: // stba |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1423 | case 0x06: // sth |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1424 | case 0x16: // stha |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1425 | case 0x04: // st |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1426 | case 0x14: // sta |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1427 | case 0x07: // std |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1428 | case 0x17: // stda |
| 1429 | case 0x0e: // stx |
| 1430 | case 0x1e: // stxa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1431 | case 0x24: // stf |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1432 | case 0x34: // stfa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1433 | case 0x27: // stdf |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1434 | case 0x37: // stdfa |
| 1435 | case 0x26: // stqf |
| 1436 | case 0x36: // stqfa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1437 | case 0x25: // stfsr |
Blue Swirl | d877fa5 | 2009-04-25 19:07:16 +0000 | [diff] [blame] | 1438 | case 0x3c: // casa |
| 1439 | case 0x3e: // casxa |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1440 | is_write = 1; |
| 1441 | break; |
| 1442 | } |
| 1443 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1444 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1445 | is_write, sigmask, NULL); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1446 | } |
| 1447 | |
| 1448 | #elif defined(__arm__) |
| 1449 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1450 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1451 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1452 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1453 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1454 | struct ucontext *uc = puc; |
| 1455 | unsigned long pc; |
| 1456 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1457 | |
blueswir1 | 48bbf11 | 2008-07-08 18:35:02 +0000 | [diff] [blame] | 1458 | #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
balrog | 5c49b36 | 2008-06-02 01:01:18 +0000 | [diff] [blame] | 1459 | pc = uc->uc_mcontext.gregs[R15]; |
| 1460 | #else |
balrog | 4eee57f | 2008-05-06 14:47:19 +0000 | [diff] [blame] | 1461 | pc = uc->uc_mcontext.arm_pc; |
balrog | 5c49b36 | 2008-06-02 01:01:18 +0000 | [diff] [blame] | 1462 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1463 | /* XXX: compute is_write */ |
| 1464 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1465 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1466 | is_write, |
pbrook | f3a9676 | 2006-07-29 19:09:31 +0000 | [diff] [blame] | 1467 | &uc->uc_sigmask, puc); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1468 | } |
| 1469 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1470 | #elif defined(__mc68000) |
| 1471 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1472 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1473 | void *puc) |
| 1474 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1475 | siginfo_t *info = pinfo; |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1476 | struct ucontext *uc = puc; |
| 1477 | unsigned long pc; |
| 1478 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1479 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1480 | pc = uc->uc_mcontext.gregs[16]; |
| 1481 | /* XXX: compute is_write */ |
| 1482 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1483 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1484 | is_write, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1485 | &uc->uc_sigmask, puc); |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1486 | } |
| 1487 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1488 | #elif defined(__ia64) |
| 1489 | |
| 1490 | #ifndef __ISR_VALID |
| 1491 | /* This ought to be in <bits/siginfo.h>... */ |
| 1492 | # define __ISR_VALID 1 |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1493 | #endif |
| 1494 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1495 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1496 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1497 | siginfo_t *info = pinfo; |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1498 | struct ucontext *uc = puc; |
| 1499 | unsigned long ip; |
| 1500 | int is_write = 0; |
| 1501 | |
| 1502 | ip = uc->uc_mcontext.sc_ip; |
| 1503 | switch (host_signum) { |
| 1504 | case SIGILL: |
| 1505 | case SIGFPE: |
| 1506 | case SIGSEGV: |
| 1507 | case SIGBUS: |
| 1508 | case SIGTRAP: |
bellard | fd4a43e | 2006-04-24 20:32:17 +0000 | [diff] [blame] | 1509 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1510 | /* ISR.W (write-access) is bit 33: */ |
| 1511 | is_write = (info->si_isr >> 33) & 1; |
| 1512 | break; |
| 1513 | |
| 1514 | default: |
| 1515 | break; |
| 1516 | } |
| 1517 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1518 | is_write, |
| 1519 | &uc->uc_sigmask, puc); |
| 1520 | } |
| 1521 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1522 | #elif defined(__s390__) |
| 1523 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1524 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1525 | void *puc) |
| 1526 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1527 | siginfo_t *info = pinfo; |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1528 | struct ucontext *uc = puc; |
| 1529 | unsigned long pc; |
| 1530 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1531 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1532 | pc = uc->uc_mcontext.psw.addr; |
| 1533 | /* XXX: compute is_write */ |
| 1534 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1535 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1536 | is_write, &uc->uc_sigmask, puc); |
| 1537 | } |
| 1538 | |
| 1539 | #elif defined(__mips__) |
| 1540 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1541 | int cpu_signal_handler(int host_signum, void *pinfo, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1542 | void *puc) |
| 1543 | { |
ths | 9617efe | 2007-05-08 21:05:55 +0000 | [diff] [blame] | 1544 | siginfo_t *info = pinfo; |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1545 | struct ucontext *uc = puc; |
| 1546 | greg_t pc = uc->uc_mcontext.pc; |
| 1547 | int is_write; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1548 | |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1549 | /* XXX: compute is_write */ |
| 1550 | is_write = 0; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1551 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1552 | is_write, &uc->uc_sigmask, puc); |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1553 | } |
| 1554 | |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 1555 | #elif defined(__hppa__) |
| 1556 | |
| 1557 | int cpu_signal_handler(int host_signum, void *pinfo, |
| 1558 | void *puc) |
| 1559 | { |
| 1560 | struct siginfo *info = pinfo; |
| 1561 | struct ucontext *uc = puc; |
| 1562 | unsigned long pc; |
| 1563 | int is_write; |
| 1564 | |
| 1565 | pc = uc->uc_mcontext.sc_iaoq[0]; |
| 1566 | /* FIXME: compute is_write */ |
| 1567 | is_write = 0; |
| 1568 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1569 | is_write, |
| 1570 | &uc->uc_sigmask, puc); |
| 1571 | } |
| 1572 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1573 | #else |
| 1574 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 1575 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1576 | |
| 1577 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 1578 | |
| 1579 | #endif /* !defined(CONFIG_SOFTMMU) */ |