Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or |
| 3 | * modify it under the terms of the GNU General Public |
| 4 | * License v2 as published by the Free Software Foundation. |
| 5 | * |
| 6 | * This program is distributed in the hope that it will be useful, |
| 7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 9 | * General Public License for more details. |
| 10 | * |
| 11 | * You should have received a copy of the GNU General Public |
| 12 | * License along with this program; if not, write to the |
| 13 | * Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
| 14 | * Boston, MA 021110-1307, USA. |
| 15 | */ |
| 16 | |
| 17 | #include <asm-generic/int-ll64.h> |
| 18 | #include <linux/mmc/ioctl.h> |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 19 | #include <stdio.h> |
| 20 | |
| 21 | #define CHECK(expr, msg, err_stmt) { if (expr) { fprintf(stderr, msg); err_stmt; } } |
| 22 | |
Roman Peniaev | c6cb053 | 2014-08-12 23:25:45 +0900 | [diff] [blame] | 23 | #ifndef offsetof |
| 24 | #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) |
| 25 | #endif |
| 26 | |
Oleg Matcovschi | 294bf86 | 2013-05-23 17:11:06 -0700 | [diff] [blame] | 27 | /* From kernel linux/major.h */ |
| 28 | #define MMC_BLOCK_MAJOR 179 |
| 29 | |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 30 | /* From kernel linux/mmc/mmc.h */ |
| 31 | #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ |
| 32 | #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ |
Ben Gardiner | 27c357d | 2013-05-30 17:12:47 -0400 | [diff] [blame] | 33 | #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ |
| 34 | #define R1_SWITCH_ERROR (1 << 7) /* sx, c */ |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 35 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ |
Roman Peniaev | c6cb053 | 2014-08-12 23:25:45 +0900 | [diff] [blame] | 36 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ |
| 37 | #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 38 | |
| 39 | /* |
| 40 | * EXT_CSD fields |
| 41 | */ |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 42 | #define EXT_CSD_S_CMD_SET 504 |
| 43 | #define EXT_CSD_HPI_FEATURE 503 |
Jaehoon Chung | 8649651 | 2012-09-21 10:08:05 +0000 | [diff] [blame] | 44 | #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ |
Al Cooper | d0b4644 | 2015-04-29 18:12:35 -0400 | [diff] [blame] | 45 | #define EXT_CSD_CACHE_SIZE_3 252 |
| 46 | #define EXT_CSD_CACHE_SIZE_2 251 |
| 47 | #define EXT_CSD_CACHE_SIZE_1 250 |
| 48 | #define EXT_CSD_CACHE_SIZE_0 249 |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 49 | #define EXT_CSD_BOOT_INFO 228 /* R/W */ |
Ben Gardiner | 4e85023 | 2013-05-30 17:12:49 -0400 | [diff] [blame] | 50 | #define EXT_CSD_SEC_COUNT_3 215 |
| 51 | #define EXT_CSD_SEC_COUNT_2 214 |
| 52 | #define EXT_CSD_SEC_COUNT_1 213 |
| 53 | #define EXT_CSD_SEC_COUNT_0 212 |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 54 | #define EXT_CSD_PART_SWITCH_TIME 199 |
Al Cooper | d0b4644 | 2015-04-29 18:12:35 -0400 | [diff] [blame] | 55 | #define EXT_CSD_REV 192 |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 56 | #define EXT_CSD_BOOT_CFG 179 |
Giuseppe CAVALLARO | 7bd1320 | 2012-04-19 10:58:37 +0200 | [diff] [blame] | 57 | #define EXT_CSD_PART_CONFIG 179 |
Al Cooper | 64c2de8 | 2015-05-01 08:24:37 -0400 | [diff] [blame] | 58 | #define EXT_CSD_BOOT_BUS_CONDITIONS 177 |
Ben Gardiner | d91d369 | 2013-05-30 17:12:51 -0400 | [diff] [blame] | 59 | #define EXT_CSD_ERASE_GROUP_DEF 175 |
Saugata Das | b7e2599 | 2012-05-17 09:26:34 -0400 | [diff] [blame] | 60 | #define EXT_CSD_BOOT_WP 173 |
Al Cooper | 64c2de8 | 2015-05-01 08:24:37 -0400 | [diff] [blame] | 61 | #define EXT_CSD_WR_REL_SET 167 |
Saugata Das | b7e2599 | 2012-05-17 09:26:34 -0400 | [diff] [blame] | 62 | #define EXT_CSD_WR_REL_PARAM 166 |
Yaniv Gardi | 21bb473 | 2013-05-26 13:25:33 -0400 | [diff] [blame] | 63 | #define EXT_CSD_SANITIZE_START 165 |
Jaehoon Chung | 8649651 | 2012-09-21 10:08:05 +0000 | [diff] [blame] | 64 | #define EXT_CSD_BKOPS_EN 163 /* R/W */ |
Chris Ball | f74dfe2 | 2012-10-19 16:49:55 -0400 | [diff] [blame] | 65 | #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ |
Ben Gardiner | 82bd950 | 2013-06-27 11:04:10 -0400 | [diff] [blame] | 66 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ |
Oliver Metz | 22f2641 | 2013-09-23 08:40:51 +0200 | [diff] [blame] | 67 | #define EXT_CSD_MAX_ENH_SIZE_MULT_2 159 |
| 68 | #define EXT_CSD_MAX_ENH_SIZE_MULT_1 158 |
| 69 | #define EXT_CSD_MAX_ENH_SIZE_MULT_0 157 |
Ben Gardiner | d91d369 | 2013-05-30 17:12:51 -0400 | [diff] [blame] | 70 | #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ |
Ben Gardiner | a6cd98d | 2013-05-30 17:12:46 -0400 | [diff] [blame] | 71 | #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ |
Balaji T K | 4afc8c8 | 2015-04-29 18:12:32 -0400 | [diff] [blame] | 72 | #define EXT_CSD_GP_SIZE_MULT_4_2 154 |
| 73 | #define EXT_CSD_GP_SIZE_MULT_4_1 153 |
| 74 | #define EXT_CSD_GP_SIZE_MULT_4_0 152 |
| 75 | #define EXT_CSD_GP_SIZE_MULT_3_2 151 |
| 76 | #define EXT_CSD_GP_SIZE_MULT_3_1 150 |
| 77 | #define EXT_CSD_GP_SIZE_MULT_3_0 149 |
| 78 | #define EXT_CSD_GP_SIZE_MULT_2_2 148 |
| 79 | #define EXT_CSD_GP_SIZE_MULT_2_1 147 |
| 80 | #define EXT_CSD_GP_SIZE_MULT_2_0 146 |
| 81 | #define EXT_CSD_GP_SIZE_MULT_1_2 145 |
| 82 | #define EXT_CSD_GP_SIZE_MULT_1_1 144 |
| 83 | #define EXT_CSD_GP_SIZE_MULT_1_0 143 |
Ben Gardiner | f82e27a | 2013-05-30 17:12:50 -0400 | [diff] [blame] | 84 | #define EXT_CSD_ENH_SIZE_MULT_2 142 |
| 85 | #define EXT_CSD_ENH_SIZE_MULT_1 141 |
| 86 | #define EXT_CSD_ENH_SIZE_MULT_0 140 |
Ben Gardiner | 68f490b | 2013-05-30 17:12:48 -0400 | [diff] [blame] | 87 | #define EXT_CSD_ENH_START_ADDR_3 139 |
| 88 | #define EXT_CSD_ENH_START_ADDR_2 138 |
| 89 | #define EXT_CSD_ENH_START_ADDR_1 137 |
| 90 | #define EXT_CSD_ENH_START_ADDR_0 136 |
Saugata Das | b7e2599 | 2012-05-17 09:26:34 -0400 | [diff] [blame] | 91 | #define EXT_CSD_NATIVE_SECTOR_SIZE 63 /* R */ |
| 92 | #define EXT_CSD_USE_NATIVE_SECTOR 62 /* R/W */ |
| 93 | #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ |
Balaji T K | 7891236 | 2015-04-29 18:12:33 -0400 | [diff] [blame] | 94 | #define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_1 53 |
| 95 | #define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_0 52 |
Al Cooper | d0b4644 | 2015-04-29 18:12:35 -0400 | [diff] [blame] | 96 | #define EXT_CSD_CACHE_CTRL 33 |
Saugata Das | b7e2599 | 2012-05-17 09:26:34 -0400 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * WR_REL_PARAM field definitions |
| 100 | */ |
| 101 | #define HS_CTRL_REL (1<<0) |
| 102 | #define EN_REL_WR (1<<2) |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 103 | |
| 104 | /* |
Jaehoon Chung | 8649651 | 2012-09-21 10:08:05 +0000 | [diff] [blame] | 105 | * BKOPS_EN field definition |
| 106 | */ |
| 107 | #define BKOPS_ENABLE (1<<0) |
| 108 | |
| 109 | /* |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 110 | * EXT_CSD field definitions |
| 111 | */ |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 112 | #define EXT_CSD_HPI_SUPP (1<<0) |
| 113 | #define EXT_CSD_HPI_IMPL (1<<1) |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 114 | #define EXT_CSD_CMD_SET_NORMAL (1<<0) |
| 115 | #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) |
| 116 | #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) |
| 117 | #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) |
| 118 | #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) |
Giuseppe CAVALLARO | a5bf4a2 | 2012-02-20 09:45:29 +0100 | [diff] [blame] | 119 | #define EXT_CSD_BOOT_INFO_HS_MODE (1<<2) |
| 120 | #define EXT_CSD_BOOT_INFO_DDR_DDR (1<<1) |
| 121 | #define EXT_CSD_BOOT_INFO_ALT (1<<0) |
| 122 | #define EXT_CSD_BOOT_CFG_ACK (1<<6) |
| 123 | #define EXT_CSD_BOOT_CFG_EN (0x38) |
Mario Schuknecht | 8c0c40d | 2013-05-15 08:28:04 +0200 | [diff] [blame] | 124 | #define EXT_CSD_BOOT_CFG_ACC (0x07) |
Chris Ball | f74dfe2 | 2012-10-19 16:49:55 -0400 | [diff] [blame] | 125 | #define EXT_CSD_RST_N_EN_MASK (0x03) |
| 126 | #define EXT_CSD_HW_RESET_EN (0x01) |
| 127 | #define EXT_CSD_HW_RESET_DIS (0x02) |
Giuseppe CAVALLARO | 7bd1320 | 2012-04-19 10:58:37 +0200 | [diff] [blame] | 128 | #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) |
| 129 | #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) |
| 130 | #define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2) |
| 131 | #define EXT_CSD_PART_CONFIG_ACC_USER_AREA (0x7) |
| 132 | #define EXT_CSD_PART_CONFIG_ACC_ACK (0x40) |
Ben Gardiner | 82bd950 | 2013-06-27 11:04:10 -0400 | [diff] [blame] | 133 | #define EXT_CSD_PARTITIONING_EN (1<<0) |
| 134 | #define EXT_CSD_ENH_ATTRIBUTE_EN (1<<1) |
Balaji T K | 4afc8c8 | 2015-04-29 18:12:32 -0400 | [diff] [blame] | 135 | #define EXT_CSD_ENH_4 (1<<4) |
| 136 | #define EXT_CSD_ENH_3 (1<<3) |
| 137 | #define EXT_CSD_ENH_2 (1<<2) |
| 138 | #define EXT_CSD_ENH_1 (1<<1) |
Ben Gardiner | d91d369 | 2013-05-30 17:12:51 -0400 | [diff] [blame] | 139 | #define EXT_CSD_ENH_USR (1<<0) |
Al Cooper | d0b4644 | 2015-04-29 18:12:35 -0400 | [diff] [blame] | 140 | #define EXT_CSD_REV_V5_1 8 |
| 141 | #define EXT_CSD_REV_V5_0 7 |
| 142 | #define EXT_CSD_REV_V4_5 6 |
| 143 | #define EXT_CSD_REV_V4_4_1 5 |
| 144 | #define EXT_CSD_REV_V4_3 3 |
| 145 | #define EXT_CSD_REV_V4_2 2 |
| 146 | #define EXT_CSD_REV_V4_1 1 |
| 147 | #define EXT_CSD_REV_V4_0 0 |
| 148 | |
Johan RUDHOLM | a8bfde7 | 2012-02-12 11:46:44 -0500 | [diff] [blame] | 149 | |
| 150 | /* From kernel linux/mmc/core.h */ |
| 151 | #define MMC_RSP_PRESENT (1 << 0) |
| 152 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
| 153 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ |
| 154 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ |
| 155 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ |
| 156 | |
| 157 | #define MMC_CMD_AC (0 << 5) |
| 158 | #define MMC_CMD_ADTC (1 << 5) |
| 159 | |
| 160 | #define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ |
| 161 | #define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ |
| 162 | |
| 163 | #define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1) |
| 164 | #define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY) |
| 165 | |
| 166 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
| 167 | #define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) |