blob: 7af16c26f6bb90b13a17296e113c0063772786b7 [file] [log] [blame]
Niklas Schulze878fed42017-02-08 15:29:21 +01001/*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7#ifdef DRV_VC4
8
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -07009#include <errno.h>
Niklas Schulze878fed42017-02-08 15:29:21 +010010#include <stdio.h>
11#include <string.h>
12#include <sys/mman.h>
13#include <vc4_drm.h>
14#include <xf86drm.h>
15
16#include "drv_priv.h"
17#include "helpers.h"
18#include "util.h"
19
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070020static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
21 DRM_FORMAT_XRGB8888 };
Niklas Schulze878fed42017-02-08 15:29:21 +010022
23static int vc4_init(struct driver *drv)
24{
Gurchetan Singhd3001452017-11-03 17:18:36 -070025 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
26 &LINEAR_METADATA, BO_USE_RENDER_MASK);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070027
28 return drv_modify_linear_combinations(drv);
Niklas Schulze878fed42017-02-08 15:29:21 +010029}
30
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080031static int vc4_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
Gurchetan Singha1892b22017-09-28 16:40:52 -070032 uint64_t use_flags)
Niklas Schulze878fed42017-02-08 15:29:21 +010033{
34 int ret;
35 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070036 uint32_t stride;
Niklas Schulze878fed42017-02-08 15:29:21 +010037 struct drm_vc4_create_bo bo_create;
38
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070039 /*
40 * Since the ARM L1 cache line size is 64 bytes, align to that as a
41 * performance optimization.
42 */
43 stride = drv_stride_from_format(format, width, 0);
44 stride = ALIGN(stride, 64);
45 drv_bo_from_format(bo, stride, height, format);
Niklas Schulze878fed42017-02-08 15:29:21 +010046
47 memset(&bo_create, 0, sizeof(bo_create));
Gurchetan Singh298b7572019-09-19 09:55:18 -070048 bo_create.size = bo->meta.total_size;
Niklas Schulze878fed42017-02-08 15:29:21 +010049
50 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VC4_CREATE_BO, &bo_create);
51 if (ret) {
Gurchetan Singh298b7572019-09-19 09:55:18 -070052 drv_log("DRM_IOCTL_VC4_GEM_CREATE failed (size=%zu)\n", bo->meta.total_size);
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -070053 return -errno;
Niklas Schulze878fed42017-02-08 15:29:21 +010054 }
55
Gurchetan Singh298b7572019-09-19 09:55:18 -070056 for (plane = 0; plane < bo->meta.num_planes; plane++)
Niklas Schulze878fed42017-02-08 15:29:21 +010057 bo->handles[plane].u32 = bo_create.handle;
58
59 return 0;
60}
61
Gurchetan Singhee43c302017-11-14 18:20:27 -080062static void *vc4_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
Niklas Schulze878fed42017-02-08 15:29:21 +010063{
64 int ret;
65 struct drm_vc4_mmap_bo bo_map;
66
67 memset(&bo_map, 0, sizeof(bo_map));
68 bo_map.handle = bo->handles[0].u32;
69
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080070 ret = drmCommandWriteRead(bo->drv->fd, DRM_VC4_MMAP_BO, &bo_map, sizeof(bo_map));
Niklas Schulze878fed42017-02-08 15:29:21 +010071 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -070072 drv_log("DRM_VC4_MMAP_BO failed\n");
Niklas Schulze878fed42017-02-08 15:29:21 +010073 return MAP_FAILED;
74 }
75
Gurchetan Singh298b7572019-09-19 09:55:18 -070076 vma->length = bo->meta.total_size;
77 return mmap(NULL, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
Gurchetan Singhcfb88762017-09-28 17:14:50 -070078 bo_map.offset);
Niklas Schulze878fed42017-02-08 15:29:21 +010079}
80
Gurchetan Singh3e9d3832017-10-31 10:36:25 -070081const struct backend backend_vc4 = {
Niklas Schulze878fed42017-02-08 15:29:21 +010082 .name = "vc4",
83 .init = vc4_init,
84 .bo_create = vc4_bo_create,
85 .bo_import = drv_prime_bo_import,
86 .bo_destroy = drv_gem_bo_destroy,
87 .bo_map = vc4_bo_map,
Gurchetan Singhba6bd502017-09-18 15:29:47 -070088 .bo_unmap = drv_bo_munmap,
Niklas Schulze878fed42017-02-08 15:29:21 +010089};
90
91#endif