blob: 99896b9b77292e73d08538123121b69d42664396 [file] [log] [blame]
Niklas Schulze878fed42017-02-08 15:29:21 +01001/*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7#ifdef DRV_VC4
8
9#include <stdio.h>
10#include <string.h>
11#include <sys/mman.h>
12#include <vc4_drm.h>
13#include <xf86drm.h>
14
15#include "drv_priv.h"
16#include "helpers.h"
17#include "util.h"
18
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070019static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
20 DRM_FORMAT_XRGB8888 };
Niklas Schulze878fed42017-02-08 15:29:21 +010021
22static int vc4_init(struct driver *drv)
23{
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070024 int ret;
25 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
26 &LINEAR_METADATA, BO_USE_RENDER_MASK);
27 if (ret)
28 return ret;
29
30 return drv_modify_linear_combinations(drv);
Niklas Schulze878fed42017-02-08 15:29:21 +010031}
32
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080033static int vc4_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
34 uint32_t flags)
Niklas Schulze878fed42017-02-08 15:29:21 +010035{
36 int ret;
37 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070038 uint32_t stride;
Niklas Schulze878fed42017-02-08 15:29:21 +010039 struct drm_vc4_create_bo bo_create;
40
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070041 /*
42 * Since the ARM L1 cache line size is 64 bytes, align to that as a
43 * performance optimization.
44 */
45 stride = drv_stride_from_format(format, width, 0);
46 stride = ALIGN(stride, 64);
47 drv_bo_from_format(bo, stride, height, format);
Niklas Schulze878fed42017-02-08 15:29:21 +010048
49 memset(&bo_create, 0, sizeof(bo_create));
50 bo_create.size = bo->total_size;
51
52 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VC4_CREATE_BO, &bo_create);
53 if (ret) {
Gurchetan Singh085bff12017-03-20 13:05:49 -070054 fprintf(stderr, "drv: DRM_IOCTL_VC4_GEM_CREATE failed (size=%zu)\n",
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080055 bo->total_size);
Niklas Schulze878fed42017-02-08 15:29:21 +010056 return ret;
57 }
58
59 for (plane = 0; plane < bo->num_planes; plane++)
60 bo->handles[plane].u32 = bo_create.handle;
61
62 return 0;
63}
64
65static void *vc4_bo_map(struct bo *bo, struct map_info *data, size_t plane)
66{
67 int ret;
68 struct drm_vc4_mmap_bo bo_map;
69
70 memset(&bo_map, 0, sizeof(bo_map));
71 bo_map.handle = bo->handles[0].u32;
72
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080073 ret = drmCommandWriteRead(bo->drv->fd, DRM_VC4_MMAP_BO, &bo_map, sizeof(bo_map));
Niklas Schulze878fed42017-02-08 15:29:21 +010074 if (ret) {
75 fprintf(stderr, "drv: DRM_VC4_MMAP_BO failed\n");
76 return MAP_FAILED;
77 }
78
79 data->length = bo->total_size;
80
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080081 return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
82 bo_map.offset);
Niklas Schulze878fed42017-02-08 15:29:21 +010083}
84
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080085struct backend backend_vc4 = {
Niklas Schulze878fed42017-02-08 15:29:21 +010086 .name = "vc4",
87 .init = vc4_init,
88 .bo_create = vc4_bo_create,
89 .bo_import = drv_prime_bo_import,
90 .bo_destroy = drv_gem_bo_destroy,
91 .bo_map = vc4_bo_map,
92};
93
94#endif