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Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001/*
2 * omap iommu: tlb and pagetable primitives
3 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08004 * Copyright (C) 2008-2010 Nokia Corporation
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02005 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090016#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020017#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/clk.h>
20#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030021#include <linux/iommu.h>
22#include <linux/mutex.h>
23#include <linux/spinlock.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020024
25#include <asm/cacheflush.h>
26
Tony Lindgrence491cf2009-10-20 09:40:47 -070027#include <plat/iommu.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020028
Ohad Ben-Cohenfcf3a6e2011-08-15 23:21:41 +030029#include <plat/iopgtable.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020030
Hiroshi DOYU37c28362010-04-27 05:37:12 +000031#define for_each_iotlb_cr(obj, n, __i, cr) \
32 for (__i = 0; \
33 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
34 __i++)
35
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020036/* bitmap of the page sizes currently supported */
37#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
38
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030039/**
40 * struct omap_iommu_domain - omap iommu domain
41 * @pgtable: the page table
42 * @iommu_dev: an omap iommu device attached to this domain. only a single
43 * iommu device can be attached for now.
44 * @lock: domain lock, should be taken when attaching/detaching
45 */
46struct omap_iommu_domain {
47 u32 *pgtable;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030048 struct omap_iommu *iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030049 spinlock_t lock;
50};
51
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020052/* accommodate the difference between omap1 and omap2/3 */
53static const struct iommu_functions *arch_iommu;
54
55static struct platform_driver omap_iommu_driver;
56static struct kmem_cache *iopte_cachep;
57
58/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030059 * omap_install_iommu_arch - Install archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020060 * @ops: a pointer to architecture specific iommu functions
61 *
62 * There are several kind of iommu algorithm(tlb, pagetable) among
63 * omap series. This interface installs such an iommu algorighm.
64 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030065int omap_install_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020066{
67 if (arch_iommu)
68 return -EBUSY;
69
70 arch_iommu = ops;
71 return 0;
72}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030073EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020074
75/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030076 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020077 * @ops: a pointer to architecture specific iommu functions
78 *
79 * This interface uninstalls the iommu algorighm installed previously.
80 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030081void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020082{
83 if (arch_iommu != ops)
84 pr_err("%s: not your arch\n", __func__);
85
86 arch_iommu = NULL;
87}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030088EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020089
90/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030091 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020092 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020093 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020094void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020095{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020096 struct omap_iommu *obj = dev_to_omap_iommu(dev);
97
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020098 arch_iommu->save_ctx(obj);
99}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300100EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200101
102/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300103 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200104 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200105 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200106void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200107{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200108 struct omap_iommu *obj = dev_to_omap_iommu(dev);
109
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200110 arch_iommu->restore_ctx(obj);
111}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300112EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200113
114/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300115 * omap_iommu_arch_version - Return running iommu arch version
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200116 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300117u32 omap_iommu_arch_version(void)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200118{
119 return arch_iommu->version;
120}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300121EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200122
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300123static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200124{
125 int err;
126
127 if (!obj)
128 return -EINVAL;
129
Martin Hostettleref4815a2011-02-24 12:51:31 -0800130 if (!arch_iommu)
131 return -ENODEV;
132
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200133 clk_enable(obj->clk);
134
135 err = arch_iommu->enable(obj);
136
137 clk_disable(obj->clk);
138 return err;
139}
140
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300141static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200142{
143 if (!obj)
144 return;
145
146 clk_enable(obj->clk);
147
148 arch_iommu->disable(obj);
149
150 clk_disable(obj->clk);
151}
152
153/*
154 * TLB operations
155 */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300156void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200157{
158 BUG_ON(!cr || !e);
159
160 arch_iommu->cr_to_e(cr, e);
161}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300162EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200163
164static inline int iotlb_cr_valid(struct cr_regs *cr)
165{
166 if (!cr)
167 return -EINVAL;
168
169 return arch_iommu->cr_valid(cr);
170}
171
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300172static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200173 struct iotlb_entry *e)
174{
175 if (!e)
176 return NULL;
177
178 return arch_iommu->alloc_cr(obj, e);
179}
180
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300181static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200182{
183 return arch_iommu->cr_to_virt(cr);
184}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200185
186static u32 get_iopte_attr(struct iotlb_entry *e)
187{
188 return arch_iommu->get_pte_attr(e);
189}
190
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300191static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200192{
193 return arch_iommu->fault_isr(obj, da);
194}
195
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300196static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200197{
198 u32 val;
199
200 val = iommu_read_reg(obj, MMU_LOCK);
201
202 l->base = MMU_LOCK_BASE(val);
203 l->vict = MMU_LOCK_VICT(val);
204
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200205}
206
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300207static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200208{
209 u32 val;
210
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200211 val = (l->base << MMU_LOCK_BASE_SHIFT);
212 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
213
214 iommu_write_reg(obj, val, MMU_LOCK);
215}
216
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300217static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200218{
219 arch_iommu->tlb_read_cr(obj, cr);
220}
221
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300222static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200223{
224 arch_iommu->tlb_load_cr(obj, cr);
225
226 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
227 iommu_write_reg(obj, 1, MMU_LD_TLB);
228}
229
230/**
231 * iotlb_dump_cr - Dump an iommu tlb entry into buf
232 * @obj: target iommu
233 * @cr: contents of cam and ram register
234 * @buf: output buffer
235 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300236static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200237 char *buf)
238{
239 BUG_ON(!cr || !buf);
240
241 return arch_iommu->dump_cr(obj, cr, buf);
242}
243
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000244/* only used in iotlb iteration for-loop */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300245static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000246{
247 struct cr_regs cr;
248 struct iotlb_lock l;
249
250 iotlb_lock_get(obj, &l);
251 l.vict = n;
252 iotlb_lock_set(obj, &l);
253 iotlb_read_cr(obj, &cr);
254
255 return cr;
256}
257
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200258/**
259 * load_iotlb_entry - Set an iommu tlb entry
260 * @obj: target iommu
261 * @e: an iommu tlb entry info
262 **/
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300263#ifdef PREFETCH_IOTLB
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300264static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200265{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200266 int err = 0;
267 struct iotlb_lock l;
268 struct cr_regs *cr;
269
270 if (!obj || !obj->nr_tlb_entries || !e)
271 return -EINVAL;
272
273 clk_enable(obj->clk);
274
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000275 iotlb_lock_get(obj, &l);
276 if (l.base == obj->nr_tlb_entries) {
277 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200278 err = -EBUSY;
279 goto out;
280 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000281 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000282 int i;
283 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000284
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000285 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000286 if (!iotlb_cr_valid(&tmp))
287 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000288
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000289 if (i == obj->nr_tlb_entries) {
290 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
291 err = -EBUSY;
292 goto out;
293 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000294
295 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000296 } else {
297 l.vict = l.base;
298 iotlb_lock_set(obj, &l);
299 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200300
301 cr = iotlb_alloc_cr(obj, e);
302 if (IS_ERR(cr)) {
303 clk_disable(obj->clk);
304 return PTR_ERR(cr);
305 }
306
307 iotlb_load_cr(obj, cr);
308 kfree(cr);
309
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000310 if (e->prsvd)
311 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200312 /* increment victim for next tlb load */
313 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000314 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200315 iotlb_lock_set(obj, &l);
316out:
317 clk_disable(obj->clk);
318 return err;
319}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200320
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300321#else /* !PREFETCH_IOTLB */
322
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300323static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300324{
325 return 0;
326}
327
328#endif /* !PREFETCH_IOTLB */
329
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300330static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300331{
332 return load_iotlb_entry(obj, e);
333}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200334
335/**
336 * flush_iotlb_page - Clear an iommu tlb entry
337 * @obj: target iommu
338 * @da: iommu device virtual address
339 *
340 * Clear an iommu tlb entry which includes 'da' address.
341 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300342static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200343{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200344 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000345 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200346
347 clk_enable(obj->clk);
348
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000349 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200350 u32 start;
351 size_t bytes;
352
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200353 if (!iotlb_cr_valid(&cr))
354 continue;
355
356 start = iotlb_cr_to_virt(&cr);
357 bytes = iopgsz_to_bytes(cr.cam & 3);
358
359 if ((start <= da) && (da < start + bytes)) {
360 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
361 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000362 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200363 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
364 }
365 }
366 clk_disable(obj->clk);
367
368 if (i == obj->nr_tlb_entries)
369 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
370}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200371
372/**
373 * flush_iotlb_all - Clear all iommu tlb entries
374 * @obj: target iommu
375 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300376static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200377{
378 struct iotlb_lock l;
379
380 clk_enable(obj->clk);
381
382 l.base = 0;
383 l.vict = 0;
384 iotlb_lock_set(obj, &l);
385
386 iommu_write_reg(obj, 1, MMU_GFLUSH);
387
388 clk_disable(obj->clk);
389}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200390
Arnd Bergmanne4efd942011-10-02 14:34:05 -0400391#if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
Kanigeri, Hariddfa9752010-05-24 02:01:51 +0000392
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300393ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200394{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200395 if (!obj || !buf)
396 return -EINVAL;
397
398 clk_enable(obj->clk);
399
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700400 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200401
402 clk_disable(obj->clk);
403
404 return bytes;
405}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300406EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200407
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300408static int
409__dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200410{
411 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000412 struct iotlb_lock saved;
413 struct cr_regs tmp;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200414 struct cr_regs *p = crs;
415
416 clk_enable(obj->clk);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200417 iotlb_lock_get(obj, &saved);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200418
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000419 for_each_iotlb_cr(obj, num, i, tmp) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200420 if (!iotlb_cr_valid(&tmp))
421 continue;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200422 *p++ = tmp;
423 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000424
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200425 iotlb_lock_set(obj, &saved);
426 clk_disable(obj->clk);
427
428 return p - crs;
429}
430
431/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300432 * omap_dump_tlb_entries - dump cr arrays to given buffer
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200433 * @obj: target iommu
434 * @buf: output buffer
435 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300436size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200437{
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700438 int i, num;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200439 struct cr_regs *cr;
440 char *p = buf;
441
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700442 num = bytes / sizeof(*cr);
443 num = min(obj->nr_tlb_entries, num);
444
445 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200446 if (!cr)
447 return 0;
448
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700449 num = __dump_tlb_entries(obj, cr, num);
450 for (i = 0; i < num; i++)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200451 p += iotlb_dump_cr(obj, cr + i, p);
452 kfree(cr);
453
454 return p - buf;
455}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300456EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200457
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300458int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200459{
460 return driver_for_each_device(&omap_iommu_driver.driver,
461 NULL, data, fn);
462}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300463EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200464
465#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
466
467/*
468 * H/W pagetable operations
469 */
470static void flush_iopgd_range(u32 *first, u32 *last)
471{
472 /* FIXME: L2 cache should be taken care of if it exists */
473 do {
474 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
475 : : "r" (first));
476 first += L1_CACHE_BYTES / sizeof(*first);
477 } while (first <= last);
478}
479
480static void flush_iopte_range(u32 *first, u32 *last)
481{
482 /* FIXME: L2 cache should be taken care of if it exists */
483 do {
484 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
485 : : "r" (first));
486 first += L1_CACHE_BYTES / sizeof(*first);
487 } while (first <= last);
488}
489
490static void iopte_free(u32 *iopte)
491{
492 /* Note: freed iopte's must be clean ready for re-use */
493 kmem_cache_free(iopte_cachep, iopte);
494}
495
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300496static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200497{
498 u32 *iopte;
499
500 /* a table has already existed */
501 if (*iopgd)
502 goto pte_ready;
503
504 /*
505 * do the allocation outside the page table lock
506 */
507 spin_unlock(&obj->page_table_lock);
508 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
509 spin_lock(&obj->page_table_lock);
510
511 if (!*iopgd) {
512 if (!iopte)
513 return ERR_PTR(-ENOMEM);
514
515 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
516 flush_iopgd_range(iopgd, iopgd);
517
518 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
519 } else {
520 /* We raced, free the reduniovant table */
521 iopte_free(iopte);
522 }
523
524pte_ready:
525 iopte = iopte_offset(iopgd, da);
526
527 dev_vdbg(obj->dev,
528 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
529 __func__, da, iopgd, *iopgd, iopte, *iopte);
530
531 return iopte;
532}
533
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300534static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200535{
536 u32 *iopgd = iopgd_offset(obj, da);
537
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300538 if ((da | pa) & ~IOSECTION_MASK) {
539 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
540 __func__, da, pa, IOSECTION_SIZE);
541 return -EINVAL;
542 }
543
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200544 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
545 flush_iopgd_range(iopgd, iopgd);
546 return 0;
547}
548
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300549static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200550{
551 u32 *iopgd = iopgd_offset(obj, da);
552 int i;
553
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300554 if ((da | pa) & ~IOSUPER_MASK) {
555 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
556 __func__, da, pa, IOSUPER_SIZE);
557 return -EINVAL;
558 }
559
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200560 for (i = 0; i < 16; i++)
561 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
562 flush_iopgd_range(iopgd, iopgd + 15);
563 return 0;
564}
565
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300566static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200567{
568 u32 *iopgd = iopgd_offset(obj, da);
569 u32 *iopte = iopte_alloc(obj, iopgd, da);
570
571 if (IS_ERR(iopte))
572 return PTR_ERR(iopte);
573
574 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
575 flush_iopte_range(iopte, iopte);
576
577 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
578 __func__, da, pa, iopte, *iopte);
579
580 return 0;
581}
582
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300583static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200584{
585 u32 *iopgd = iopgd_offset(obj, da);
586 u32 *iopte = iopte_alloc(obj, iopgd, da);
587 int i;
588
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300589 if ((da | pa) & ~IOLARGE_MASK) {
590 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
591 __func__, da, pa, IOLARGE_SIZE);
592 return -EINVAL;
593 }
594
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200595 if (IS_ERR(iopte))
596 return PTR_ERR(iopte);
597
598 for (i = 0; i < 16; i++)
599 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
600 flush_iopte_range(iopte, iopte + 15);
601 return 0;
602}
603
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300604static int
605iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200606{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300607 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200608 u32 prot;
609 int err;
610
611 if (!obj || !e)
612 return -EINVAL;
613
614 switch (e->pgsz) {
615 case MMU_CAM_PGSZ_16M:
616 fn = iopgd_alloc_super;
617 break;
618 case MMU_CAM_PGSZ_1M:
619 fn = iopgd_alloc_section;
620 break;
621 case MMU_CAM_PGSZ_64K:
622 fn = iopte_alloc_large;
623 break;
624 case MMU_CAM_PGSZ_4K:
625 fn = iopte_alloc_page;
626 break;
627 default:
628 fn = NULL;
629 BUG();
630 break;
631 }
632
633 prot = get_iopte_attr(e);
634
635 spin_lock(&obj->page_table_lock);
636 err = fn(obj, e->da, e->pa, prot);
637 spin_unlock(&obj->page_table_lock);
638
639 return err;
640}
641
642/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300643 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200644 * @obj: target iommu
645 * @e: an iommu tlb entry info
646 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300647int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200648{
649 int err;
650
651 flush_iotlb_page(obj, e->da);
652 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200653 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300654 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200655 return err;
656}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300657EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200658
659/**
660 * iopgtable_lookup_entry - Lookup an iommu pte entry
661 * @obj: target iommu
662 * @da: iommu device virtual address
663 * @ppgd: iommu pgd entry pointer to be returned
664 * @ppte: iommu pte entry pointer to be returned
665 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300666static void
667iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200668{
669 u32 *iopgd, *iopte = NULL;
670
671 iopgd = iopgd_offset(obj, da);
672 if (!*iopgd)
673 goto out;
674
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300675 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200676 iopte = iopte_offset(iopgd, da);
677out:
678 *ppgd = iopgd;
679 *ppte = iopte;
680}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200681
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300682static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200683{
684 size_t bytes;
685 u32 *iopgd = iopgd_offset(obj, da);
686 int nent = 1;
687
688 if (!*iopgd)
689 return 0;
690
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300691 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200692 int i;
693 u32 *iopte = iopte_offset(iopgd, da);
694
695 bytes = IOPTE_SIZE;
696 if (*iopte & IOPTE_LARGE) {
697 nent *= 16;
698 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800699 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200700 }
701 bytes *= nent;
702 memset(iopte, 0, nent * sizeof(*iopte));
703 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
704
705 /*
706 * do table walk to check if this table is necessary or not
707 */
708 iopte = iopte_offset(iopgd, 0);
709 for (i = 0; i < PTRS_PER_IOPTE; i++)
710 if (iopte[i])
711 goto out;
712
713 iopte_free(iopte);
714 nent = 1; /* for the next L1 entry */
715 } else {
716 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700717 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200718 nent *= 16;
719 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800720 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200721 }
722 bytes *= nent;
723 }
724 memset(iopgd, 0, nent * sizeof(*iopgd));
725 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
726out:
727 return bytes;
728}
729
730/**
731 * iopgtable_clear_entry - Remove an iommu pte entry
732 * @obj: target iommu
733 * @da: iommu device virtual address
734 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300735static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200736{
737 size_t bytes;
738
739 spin_lock(&obj->page_table_lock);
740
741 bytes = iopgtable_clear_entry_core(obj, da);
742 flush_iotlb_page(obj, da);
743
744 spin_unlock(&obj->page_table_lock);
745
746 return bytes;
747}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200748
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300749static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200750{
751 int i;
752
753 spin_lock(&obj->page_table_lock);
754
755 for (i = 0; i < PTRS_PER_IOPGD; i++) {
756 u32 da;
757 u32 *iopgd;
758
759 da = i << IOPGD_SHIFT;
760 iopgd = iopgd_offset(obj, da);
761
762 if (!*iopgd)
763 continue;
764
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300765 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200766 iopte_free(iopte_offset(iopgd, 0));
767
768 *iopgd = 0;
769 flush_iopgd_range(iopgd, iopgd);
770 }
771
772 flush_iotlb_all(obj);
773
774 spin_unlock(&obj->page_table_lock);
775}
776
777/*
778 * Device IOMMU generic operations
779 */
780static irqreturn_t iommu_fault_handler(int irq, void *data)
781{
David Cohend594f1f2011-02-16 19:35:51 +0000782 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200783 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300784 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400785 struct iommu_domain *domain = obj->domain;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200786
787 if (!obj->refcount)
788 return IRQ_NONE;
789
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200790 clk_enable(obj->clk);
David Cohend594f1f2011-02-16 19:35:51 +0000791 errs = iommu_report_fault(obj, &da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200792 clk_disable(obj->clk);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200793 if (errs == 0)
794 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000795
796 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400797 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200798 return IRQ_HANDLED;
799
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000800 iommu_disable(obj);
801
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200802 iopgd = iopgd_offset(obj, da);
803
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300804 if (!iopgd_is_table(*iopgd)) {
David Cohend594f1f2011-02-16 19:35:51 +0000805 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
806 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200807 return IRQ_NONE;
808 }
809
810 iopte = iopte_offset(iopgd, da);
811
David Cohend594f1f2011-02-16 19:35:51 +0000812 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
813 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
814 iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200815
816 return IRQ_NONE;
817}
818
819static int device_match_by_alias(struct device *dev, void *data)
820{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300821 struct omap_iommu *obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200822 const char *name = data;
823
824 pr_debug("%s: %s %s\n", __func__, obj->name, name);
825
826 return strcmp(obj->name, name) == 0;
827}
828
829/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300830 * omap_iommu_attach() - attach iommu device to an iommu domain
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200831 * @name: name of target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300832 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200833 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200834static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200835{
836 int err = -ENOMEM;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200837 struct device *dev;
838 struct omap_iommu *obj;
839
840 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
841 (void *)name,
842 device_match_by_alias);
843 if (!dev)
844 return NULL;
845
846 obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200847
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300848 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200849
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300850 /* an iommu device can only be attached once */
851 if (++obj->refcount > 1) {
852 dev_err(dev, "%s: already attached!\n", obj->name);
853 err = -EBUSY;
854 goto err_enable;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200855 }
856
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300857 obj->iopgd = iopgd;
858 err = iommu_enable(obj);
859 if (err)
860 goto err_enable;
861 flush_iotlb_all(obj);
862
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200863 if (!try_module_get(obj->owner))
864 goto err_module;
865
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300866 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200867
868 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
869 return obj;
870
871err_module:
872 if (obj->refcount == 1)
873 iommu_disable(obj);
874err_enable:
875 obj->refcount--;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300876 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200877 return ERR_PTR(err);
878}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200879
880/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300881 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200882 * @obj: target iommu
883 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300884static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200885{
Roel Kluinacf9d462010-01-08 10:29:05 -0800886 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200887 return;
888
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300889 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200890
891 if (--obj->refcount == 0)
892 iommu_disable(obj);
893
894 module_put(obj->owner);
895
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300896 obj->iopgd = NULL;
897
898 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200899
900 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
901}
David Cohend594f1f2011-02-16 19:35:51 +0000902
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200903/*
904 * OMAP Device MMU(IOMMU) detection
905 */
906static int __devinit omap_iommu_probe(struct platform_device *pdev)
907{
908 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200909 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300910 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200911 struct resource *res;
912 struct iommu_platform_data *pdata = pdev->dev.platform_data;
913
914 if (pdev->num_resources != 2)
915 return -EINVAL;
916
917 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
918 if (!obj)
919 return -ENOMEM;
920
921 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
922 if (IS_ERR(obj->clk))
923 goto err_clk;
924
925 obj->nr_tlb_entries = pdata->nr_tlb_entries;
926 obj->name = pdata->name;
927 obj->dev = &pdev->dev;
928 obj->ctx = (void *)obj + sizeof(*obj);
Guzman Lugo, Fernandoc7f4ab22010-12-15 00:54:03 +0000929 obj->da_start = pdata->da_start;
930 obj->da_end = pdata->da_end;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200931
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300932 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200933 mutex_init(&obj->mmap_lock);
934 spin_lock_init(&obj->page_table_lock);
935 INIT_LIST_HEAD(&obj->mmap);
936
937 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
938 if (!res) {
939 err = -ENODEV;
940 goto err_mem;
941 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200942
943 res = request_mem_region(res->start, resource_size(res),
944 dev_name(&pdev->dev));
945 if (!res) {
946 err = -EIO;
947 goto err_mem;
948 }
949
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000950 obj->regbase = ioremap(res->start, resource_size(res));
951 if (!obj->regbase) {
952 err = -ENOMEM;
953 goto err_ioremap;
954 }
955
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200956 irq = platform_get_irq(pdev, 0);
957 if (irq < 0) {
958 err = -ENODEV;
959 goto err_irq;
960 }
961 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
962 dev_name(&pdev->dev), obj);
963 if (err < 0)
964 goto err_irq;
965 platform_set_drvdata(pdev, obj);
966
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200967 dev_info(&pdev->dev, "%s registered\n", obj->name);
968 return 0;
969
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200970err_irq:
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200971 iounmap(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000972err_ioremap:
973 release_mem_region(res->start, resource_size(res));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200974err_mem:
975 clk_put(obj->clk);
976err_clk:
977 kfree(obj);
978 return err;
979}
980
981static int __devexit omap_iommu_remove(struct platform_device *pdev)
982{
983 int irq;
984 struct resource *res;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300985 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200986
987 platform_set_drvdata(pdev, NULL);
988
989 iopgtable_clear_entry_all(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200990
991 irq = platform_get_irq(pdev, 0);
992 free_irq(irq, obj);
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 release_mem_region(res->start, resource_size(res));
995 iounmap(obj->regbase);
996
997 clk_put(obj->clk);
998 dev_info(&pdev->dev, "%s removed\n", obj->name);
999 kfree(obj);
1000 return 0;
1001}
1002
1003static struct platform_driver omap_iommu_driver = {
1004 .probe = omap_iommu_probe,
1005 .remove = __devexit_p(omap_iommu_remove),
1006 .driver = {
1007 .name = "omap-iommu",
1008 },
1009};
1010
1011static void iopte_cachep_ctor(void *iopte)
1012{
1013 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1014}
1015
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001016static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001017 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001018{
1019 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001020 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001021 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001022 struct iotlb_entry e;
1023 int omap_pgsz;
1024 u32 ret, flags;
1025
1026 /* we only support mapping a single iommu page for now */
1027 omap_pgsz = bytes_to_iopgsz(bytes);
1028 if (omap_pgsz < 0) {
1029 dev_err(dev, "invalid size to map: %d\n", bytes);
1030 return -EINVAL;
1031 }
1032
1033 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1034
1035 flags = omap_pgsz | prot;
1036
1037 iotlb_init_entry(&e, da, pa, flags);
1038
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001039 ret = omap_iopgtable_store_entry(oiommu, &e);
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001040 if (ret)
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001041 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001042
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001043 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001044}
1045
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001046static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1047 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001048{
1049 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001050 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001051 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001052
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001053 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001054
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001055 return iopgtable_clear_entry(oiommu, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001056}
1057
1058static int
1059omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1060{
1061 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001062 struct omap_iommu *oiommu;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001063 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001064 int ret = 0;
1065
1066 spin_lock(&omap_domain->lock);
1067
1068 /* only a single device is supported per domain for now */
1069 if (omap_domain->iommu_dev) {
1070 dev_err(dev, "iommu domain is already attached\n");
1071 ret = -EBUSY;
1072 goto out;
1073 }
1074
1075 /* get a handle to and enable the omap iommu */
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001076 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001077 if (IS_ERR(oiommu)) {
1078 ret = PTR_ERR(oiommu);
1079 dev_err(dev, "can't get omap iommu: %d\n", ret);
1080 goto out;
1081 }
1082
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001083 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -04001084 oiommu->domain = domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001085
1086out:
1087 spin_unlock(&omap_domain->lock);
1088 return ret;
1089}
1090
1091static void omap_iommu_detach_dev(struct iommu_domain *domain,
1092 struct device *dev)
1093{
1094 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001095 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1096 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001097
1098 spin_lock(&omap_domain->lock);
1099
1100 /* only a single device is supported per domain for now */
1101 if (omap_domain->iommu_dev != oiommu) {
1102 dev_err(dev, "invalid iommu device\n");
1103 goto out;
1104 }
1105
1106 iopgtable_clear_entry_all(oiommu);
1107
1108 omap_iommu_detach(oiommu);
1109
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001110 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001111
1112out:
1113 spin_unlock(&omap_domain->lock);
1114}
1115
1116static int omap_iommu_domain_init(struct iommu_domain *domain)
1117{
1118 struct omap_iommu_domain *omap_domain;
1119
1120 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1121 if (!omap_domain) {
1122 pr_err("kzalloc failed\n");
1123 goto out;
1124 }
1125
1126 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1127 if (!omap_domain->pgtable) {
1128 pr_err("kzalloc failed\n");
1129 goto fail_nomem;
1130 }
1131
1132 /*
1133 * should never fail, but please keep this around to ensure
1134 * we keep the hardware happy
1135 */
1136 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1137
1138 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1139 spin_lock_init(&omap_domain->lock);
1140
1141 domain->priv = omap_domain;
1142
1143 return 0;
1144
1145fail_nomem:
1146 kfree(omap_domain);
1147out:
1148 return -ENOMEM;
1149}
1150
1151/* assume device was already detached */
1152static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1153{
1154 struct omap_iommu_domain *omap_domain = domain->priv;
1155
1156 domain->priv = NULL;
1157
1158 kfree(omap_domain->pgtable);
1159 kfree(omap_domain);
1160}
1161
1162static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1163 unsigned long da)
1164{
1165 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001166 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001167 struct device *dev = oiommu->dev;
1168 u32 *pgd, *pte;
1169 phys_addr_t ret = 0;
1170
1171 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1172
1173 if (pte) {
1174 if (iopte_is_small(*pte))
1175 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1176 else if (iopte_is_large(*pte))
1177 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1178 else
Ohad Ben-Cohen1a36ea82011-12-06 15:22:10 +02001179 dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001180 } else {
1181 if (iopgd_is_section(*pgd))
1182 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1183 else if (iopgd_is_super(*pgd))
1184 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1185 else
Ohad Ben-Cohen1a36ea82011-12-06 15:22:10 +02001186 dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001187 }
1188
1189 return ret;
1190}
1191
1192static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1193 unsigned long cap)
1194{
1195 return 0;
1196}
1197
1198static struct iommu_ops omap_iommu_ops = {
1199 .domain_init = omap_iommu_domain_init,
1200 .domain_destroy = omap_iommu_domain_destroy,
1201 .attach_dev = omap_iommu_attach_dev,
1202 .detach_dev = omap_iommu_detach_dev,
1203 .map = omap_iommu_map,
1204 .unmap = omap_iommu_unmap,
1205 .iova_to_phys = omap_iommu_iova_to_phys,
1206 .domain_has_cap = omap_iommu_domain_has_cap,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001207 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001208};
1209
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001210static int __init omap_iommu_init(void)
1211{
1212 struct kmem_cache *p;
1213 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1214 size_t align = 1 << 10; /* L2 pagetable alignement */
1215
1216 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1217 iopte_cachep_ctor);
1218 if (!p)
1219 return -ENOMEM;
1220 iopte_cachep = p;
1221
Joerg Roedela65bc642011-09-06 17:56:07 +02001222 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001223
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001224 return platform_driver_register(&omap_iommu_driver);
1225}
1226module_init(omap_iommu_init);
1227
1228static void __exit omap_iommu_exit(void)
1229{
1230 kmem_cache_destroy(iopte_cachep);
1231
1232 platform_driver_unregister(&omap_iommu_driver);
1233}
1234module_exit(omap_iommu_exit);
1235
1236MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1237MODULE_ALIAS("platform:omap-iommu");
1238MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1239MODULE_LICENSE("GPL v2");