Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 1 | /* |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 3 | * |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 9 | #include <linux/bitops.h> |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 10 | #include <linux/debugfs.h> |
Thierry Reding | bc5e6de | 2013-01-21 11:09:06 +0100 | [diff] [blame] | 11 | #include <linux/err.h> |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 12 | #include <linux/iommu.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 13 | #include <linux/kernel.h> |
Hiroshi Doyu | 0760e8f | 2012-06-25 14:23:55 +0300 | [diff] [blame] | 14 | #include <linux/of.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 15 | #include <linux/of_device.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/slab.h> |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 18 | |
| 19 | #include <soc/tegra/ahb.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 20 | #include <soc/tegra/mc.h> |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 21 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 22 | struct tegra_smmu { |
| 23 | void __iomem *regs; |
| 24 | struct device *dev; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 25 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 26 | struct tegra_mc *mc; |
| 27 | const struct tegra_smmu_soc *soc; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 28 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 29 | unsigned long pfn_mask; |
| 30 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 31 | unsigned long *asids; |
| 32 | struct mutex lock; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 33 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 34 | struct list_head list; |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 35 | |
| 36 | struct dentry *debugfs; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 37 | }; |
| 38 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 39 | struct tegra_smmu_as { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 40 | struct iommu_domain domain; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 41 | struct tegra_smmu *smmu; |
| 42 | unsigned int use_count; |
| 43 | struct page *count; |
| 44 | struct page *pd; |
| 45 | unsigned id; |
| 46 | u32 attr; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 47 | }; |
| 48 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 49 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
| 50 | { |
| 51 | return container_of(dom, struct tegra_smmu_as, domain); |
| 52 | } |
| 53 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 54 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
| 55 | unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 56 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 57 | writel(value, smmu->regs + offset); |
Joerg Roedel | fe1229b | 2013-02-04 20:40:58 +0100 | [diff] [blame] | 58 | } |
| 59 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 60 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 61 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 62 | return readl(smmu->regs + offset); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 63 | } |
| 64 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 65 | #define SMMU_CONFIG 0x010 |
| 66 | #define SMMU_CONFIG_ENABLE (1 << 0) |
| 67 | |
| 68 | #define SMMU_TLB_CONFIG 0x14 |
| 69 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) |
| 70 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) |
| 71 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) |
| 72 | |
| 73 | #define SMMU_PTC_CONFIG 0x18 |
| 74 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) |
| 75 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) |
| 76 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) |
| 77 | |
| 78 | #define SMMU_PTB_ASID 0x01c |
| 79 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) |
| 80 | |
| 81 | #define SMMU_PTB_DATA 0x020 |
| 82 | #define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr)) |
| 83 | |
| 84 | #define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr)) |
| 85 | |
| 86 | #define SMMU_TLB_FLUSH 0x030 |
| 87 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) |
| 88 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) |
| 89 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) |
| 90 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) |
| 91 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
| 92 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) |
| 93 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ |
| 94 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) |
| 95 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) |
| 96 | |
| 97 | #define SMMU_PTC_FLUSH 0x034 |
| 98 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) |
| 99 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) |
| 100 | |
| 101 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
| 102 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 |
| 103 | |
| 104 | /* per-SWGROUP SMMU_*_ASID register */ |
| 105 | #define SMMU_ASID_ENABLE (1 << 31) |
| 106 | #define SMMU_ASID_MASK 0x7f |
| 107 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) |
| 108 | |
| 109 | /* page table definitions */ |
| 110 | #define SMMU_NUM_PDE 1024 |
| 111 | #define SMMU_NUM_PTE 1024 |
| 112 | |
| 113 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
| 114 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) |
| 115 | |
| 116 | #define SMMU_PDE_SHIFT 22 |
| 117 | #define SMMU_PTE_SHIFT 12 |
| 118 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 119 | #define SMMU_PD_READABLE (1 << 31) |
| 120 | #define SMMU_PD_WRITABLE (1 << 30) |
| 121 | #define SMMU_PD_NONSECURE (1 << 29) |
| 122 | |
| 123 | #define SMMU_PDE_READABLE (1 << 31) |
| 124 | #define SMMU_PDE_WRITABLE (1 << 30) |
| 125 | #define SMMU_PDE_NONSECURE (1 << 29) |
| 126 | #define SMMU_PDE_NEXT (1 << 28) |
| 127 | |
| 128 | #define SMMU_PTE_READABLE (1 << 31) |
| 129 | #define SMMU_PTE_WRITABLE (1 << 30) |
| 130 | #define SMMU_PTE_NONSECURE (1 << 29) |
| 131 | |
| 132 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
| 133 | SMMU_PDE_NONSECURE) |
| 134 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ |
| 135 | SMMU_PTE_NONSECURE) |
| 136 | |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame^] | 137 | static unsigned int iova_pd_index(unsigned long iova) |
| 138 | { |
| 139 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); |
| 140 | } |
| 141 | |
| 142 | static unsigned int iova_pt_index(unsigned long iova) |
| 143 | { |
| 144 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); |
| 145 | } |
| 146 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 147 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, |
| 148 | unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 149 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 150 | phys_addr_t phys = page ? page_to_phys(page) : 0; |
| 151 | u32 value; |
Hiroshi Doyu | a6870e9 | 2013-01-31 10:14:10 +0200 | [diff] [blame] | 152 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 153 | if (page) { |
| 154 | offset &= ~(smmu->mc->soc->atom_size - 1); |
Hiroshi Doyu | a6870e9 | 2013-01-31 10:14:10 +0200 | [diff] [blame] | 155 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 156 | if (smmu->mc->soc->num_address_bits > 32) { |
| 157 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
| 158 | value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 159 | #else |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 160 | value = 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 161 | #endif |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 162 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
| 163 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 164 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 165 | value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
| 166 | } else { |
| 167 | value = SMMU_PTC_FLUSH_TYPE_ALL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 168 | } |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 169 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 170 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
| 171 | } |
| 172 | |
| 173 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
| 174 | { |
| 175 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
| 176 | } |
| 177 | |
| 178 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
| 179 | unsigned long asid) |
| 180 | { |
| 181 | u32 value; |
| 182 | |
| 183 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 184 | SMMU_TLB_FLUSH_VA_MATCH_ALL; |
| 185 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 186 | } |
| 187 | |
| 188 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
| 189 | unsigned long asid, |
| 190 | unsigned long iova) |
| 191 | { |
| 192 | u32 value; |
| 193 | |
| 194 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 195 | SMMU_TLB_FLUSH_VA_SECTION(iova); |
| 196 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 197 | } |
| 198 | |
| 199 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
| 200 | unsigned long asid, |
| 201 | unsigned long iova) |
| 202 | { |
| 203 | u32 value; |
| 204 | |
| 205 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 206 | SMMU_TLB_FLUSH_VA_GROUP(iova); |
| 207 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 208 | } |
| 209 | |
| 210 | static inline void smmu_flush(struct tegra_smmu *smmu) |
| 211 | { |
| 212 | smmu_readl(smmu, SMMU_CONFIG); |
| 213 | } |
| 214 | |
| 215 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
| 216 | { |
| 217 | unsigned long id; |
| 218 | |
| 219 | mutex_lock(&smmu->lock); |
| 220 | |
| 221 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
| 222 | if (id >= smmu->soc->num_asids) { |
| 223 | mutex_unlock(&smmu->lock); |
| 224 | return -ENOSPC; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 225 | } |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 226 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 227 | set_bit(id, smmu->asids); |
| 228 | *idp = id; |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 229 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 230 | mutex_unlock(&smmu->lock); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 231 | return 0; |
| 232 | } |
| 233 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 234 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 235 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 236 | mutex_lock(&smmu->lock); |
| 237 | clear_bit(id, smmu->asids); |
| 238 | mutex_unlock(&smmu->lock); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 239 | } |
| 240 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 241 | static bool tegra_smmu_capable(enum iommu_cap cap) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 242 | { |
Joerg Roedel | 7c2aa64 | 2014-09-05 10:51:37 +0200 | [diff] [blame] | 243 | return false; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 244 | } |
| 245 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 246 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 247 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 248 | struct tegra_smmu_as *as; |
| 249 | unsigned int i; |
| 250 | uint32_t *pd; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 251 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 252 | if (type != IOMMU_DOMAIN_UNMANAGED) |
| 253 | return NULL; |
| 254 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 255 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
| 256 | if (!as) |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 257 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 258 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 259 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 260 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 261 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
| 262 | if (!as->pd) { |
| 263 | kfree(as); |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 264 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 265 | } |
| 266 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 267 | as->count = alloc_page(GFP_KERNEL); |
| 268 | if (!as->count) { |
| 269 | __free_page(as->pd); |
| 270 | kfree(as); |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 271 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 272 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 273 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 274 | /* clear PDEs */ |
| 275 | pd = page_address(as->pd); |
| 276 | SetPageReserved(as->pd); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 277 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 278 | for (i = 0; i < SMMU_NUM_PDE; i++) |
| 279 | pd[i] = 0; |
Hiroshi Doyu | d2453b2 | 2012-07-30 08:39:18 +0300 | [diff] [blame] | 280 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 281 | /* clear PDE usage counters */ |
| 282 | pd = page_address(as->count); |
| 283 | SetPageReserved(as->count); |
Hiroshi Doyu | d2453b2 | 2012-07-30 08:39:18 +0300 | [diff] [blame] | 284 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 285 | for (i = 0; i < SMMU_NUM_PDE; i++) |
| 286 | pd[i] = 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 287 | |
Thierry Reding | 471d914 | 2015-03-27 11:07:25 +0100 | [diff] [blame] | 288 | /* setup aperture */ |
Joerg Roedel | 7f65ef0 | 2015-04-02 13:33:19 +0200 | [diff] [blame] | 289 | as->domain.geometry.aperture_start = 0; |
| 290 | as->domain.geometry.aperture_end = 0xffffffff; |
| 291 | as->domain.geometry.force_aperture = true; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 292 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 293 | return &as->domain; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 294 | } |
| 295 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 296 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 297 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 298 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 299 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 300 | /* TODO: free page directory and page tables */ |
| 301 | ClearPageReserved(as->pd); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 302 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 303 | kfree(as); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 304 | } |
| 305 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 306 | static const struct tegra_smmu_swgroup * |
| 307 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 308 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 309 | const struct tegra_smmu_swgroup *group = NULL; |
| 310 | unsigned int i; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 311 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 312 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
| 313 | if (smmu->soc->swgroups[i].swgroup == swgroup) { |
| 314 | group = &smmu->soc->swgroups[i]; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 315 | break; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 316 | } |
| 317 | } |
| 318 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 319 | return group; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 320 | } |
| 321 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 322 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
| 323 | unsigned int asid) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 324 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 325 | const struct tegra_smmu_swgroup *group; |
| 326 | unsigned int i; |
| 327 | u32 value; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 328 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 329 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 330 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 331 | |
| 332 | if (client->swgroup != swgroup) |
| 333 | continue; |
| 334 | |
| 335 | value = smmu_readl(smmu, client->smmu.reg); |
| 336 | value |= BIT(client->smmu.bit); |
| 337 | smmu_writel(smmu, value, client->smmu.reg); |
| 338 | } |
| 339 | |
| 340 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
| 341 | if (group) { |
| 342 | value = smmu_readl(smmu, group->reg); |
| 343 | value &= ~SMMU_ASID_MASK; |
| 344 | value |= SMMU_ASID_VALUE(asid); |
| 345 | value |= SMMU_ASID_ENABLE; |
| 346 | smmu_writel(smmu, value, group->reg); |
| 347 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 348 | } |
| 349 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 350 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
| 351 | unsigned int asid) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 352 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 353 | const struct tegra_smmu_swgroup *group; |
| 354 | unsigned int i; |
| 355 | u32 value; |
| 356 | |
| 357 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
| 358 | if (group) { |
| 359 | value = smmu_readl(smmu, group->reg); |
| 360 | value &= ~SMMU_ASID_MASK; |
| 361 | value |= SMMU_ASID_VALUE(asid); |
| 362 | value &= ~SMMU_ASID_ENABLE; |
| 363 | smmu_writel(smmu, value, group->reg); |
| 364 | } |
| 365 | |
| 366 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 367 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 368 | |
| 369 | if (client->swgroup != swgroup) |
| 370 | continue; |
| 371 | |
| 372 | value = smmu_readl(smmu, client->smmu.reg); |
| 373 | value &= ~BIT(client->smmu.bit); |
| 374 | smmu_writel(smmu, value, client->smmu.reg); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
| 379 | struct tegra_smmu_as *as) |
| 380 | { |
| 381 | u32 value; |
Hiroshi Doyu | 0760e8f | 2012-06-25 14:23:55 +0300 | [diff] [blame] | 382 | int err; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 383 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 384 | if (as->use_count > 0) { |
| 385 | as->use_count++; |
| 386 | return 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 387 | } |
| 388 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 389 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
| 390 | if (err < 0) |
Hiroshi Doyu | 0547c2f | 2012-06-25 14:23:57 +0300 | [diff] [blame] | 391 | return err; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 392 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 393 | smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD); |
| 394 | smmu_flush_ptc(smmu, as->pd, 0); |
| 395 | smmu_flush_tlb_asid(smmu, as->id); |
| 396 | |
| 397 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
| 398 | value = SMMU_PTB_DATA_VALUE(as->pd, as->attr); |
| 399 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
| 400 | smmu_flush(smmu); |
| 401 | |
| 402 | as->smmu = smmu; |
| 403 | as->use_count++; |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
| 409 | struct tegra_smmu_as *as) |
| 410 | { |
| 411 | if (--as->use_count > 0) |
| 412 | return; |
| 413 | |
| 414 | tegra_smmu_free_asid(smmu, as->id); |
| 415 | as->smmu = NULL; |
| 416 | } |
| 417 | |
| 418 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
| 419 | struct device *dev) |
| 420 | { |
| 421 | struct tegra_smmu *smmu = dev->archdata.iommu; |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 422 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 423 | struct device_node *np = dev->of_node; |
| 424 | struct of_phandle_args args; |
| 425 | unsigned int index = 0; |
| 426 | int err = 0; |
| 427 | |
| 428 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 429 | &args)) { |
| 430 | unsigned int swgroup = args.args[0]; |
| 431 | |
| 432 | if (args.np != smmu->dev->of_node) { |
| 433 | of_node_put(args.np); |
| 434 | continue; |
| 435 | } |
| 436 | |
| 437 | of_node_put(args.np); |
| 438 | |
| 439 | err = tegra_smmu_as_prepare(smmu, as); |
| 440 | if (err < 0) |
| 441 | return err; |
| 442 | |
| 443 | tegra_smmu_enable(smmu, swgroup, as->id); |
| 444 | index++; |
| 445 | } |
| 446 | |
| 447 | if (index == 0) |
| 448 | return -ENODEV; |
| 449 | |
| 450 | return 0; |
| 451 | } |
| 452 | |
| 453 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
| 454 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 455 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 456 | struct device_node *np = dev->of_node; |
| 457 | struct tegra_smmu *smmu = as->smmu; |
| 458 | struct of_phandle_args args; |
| 459 | unsigned int index = 0; |
| 460 | |
| 461 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 462 | &args)) { |
| 463 | unsigned int swgroup = args.args[0]; |
| 464 | |
| 465 | if (args.np != smmu->dev->of_node) { |
| 466 | of_node_put(args.np); |
| 467 | continue; |
| 468 | } |
| 469 | |
| 470 | of_node_put(args.np); |
| 471 | |
| 472 | tegra_smmu_disable(smmu, swgroup, as->id); |
| 473 | tegra_smmu_as_unprepare(smmu, as); |
| 474 | index++; |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
| 479 | struct page **pagep) |
| 480 | { |
| 481 | u32 *pd = page_address(as->pd), *pt, *count; |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame^] | 482 | unsigned int pde = iova_pd_index(iova); |
| 483 | unsigned int pte = iova_pt_index(iova); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 484 | struct tegra_smmu *smmu = as->smmu; |
| 485 | struct page *page; |
| 486 | unsigned int i; |
| 487 | |
| 488 | if (pd[pde] == 0) { |
| 489 | page = alloc_page(GFP_KERNEL | __GFP_DMA); |
| 490 | if (!page) |
| 491 | return NULL; |
| 492 | |
| 493 | pt = page_address(page); |
| 494 | SetPageReserved(page); |
| 495 | |
| 496 | for (i = 0; i < SMMU_NUM_PTE; i++) |
| 497 | pt[i] = 0; |
| 498 | |
| 499 | smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT); |
| 500 | |
| 501 | pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
| 502 | |
| 503 | smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4); |
| 504 | smmu_flush_ptc(smmu, as->pd, pde << 2); |
| 505 | smmu_flush_tlb_section(smmu, as->id, iova); |
| 506 | smmu_flush(smmu); |
| 507 | } else { |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 508 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 509 | pt = page_address(page); |
| 510 | } |
| 511 | |
| 512 | *pagep = page; |
| 513 | |
| 514 | /* Keep track of entries in this page table. */ |
| 515 | count = page_address(as->count); |
| 516 | if (pt[pte] == 0) |
| 517 | count[pde]++; |
| 518 | |
| 519 | return &pt[pte]; |
| 520 | } |
| 521 | |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 522 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 523 | { |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 524 | struct tegra_smmu *smmu = as->smmu; |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame^] | 525 | unsigned int pde = iova_pd_index(iova); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 526 | u32 *count = page_address(as->count); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 527 | u32 *pd = page_address(as->pd); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 528 | struct page *page; |
| 529 | |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 530 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 531 | |
| 532 | /* |
| 533 | * When no entries in this page table are used anymore, return the |
| 534 | * memory page to the system. |
| 535 | */ |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 536 | if (--count[pde] == 0) { |
| 537 | unsigned int offset = pde * sizeof(*pd); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 538 | |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 539 | /* Clear the page directory entry first */ |
| 540 | pd[pde] = 0; |
| 541 | |
| 542 | /* Flush the page directory entry */ |
| 543 | smmu->soc->ops->flush_dcache(as->pd, offset, sizeof(*pd)); |
| 544 | smmu_flush_ptc(smmu, as->pd, offset); |
| 545 | smmu_flush_tlb_section(smmu, as->id, iova); |
| 546 | smmu_flush(smmu); |
| 547 | |
| 548 | /* Finally, free the page */ |
| 549 | ClearPageReserved(page); |
| 550 | __free_page(page); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 551 | } |
| 552 | } |
| 553 | |
Russell King | 8482ee5e | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 554 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
| 555 | u32 *pte, struct page *pte_page, u32 val) |
| 556 | { |
| 557 | struct tegra_smmu *smmu = as->smmu; |
| 558 | unsigned long offset = offset_in_page(pte); |
| 559 | |
| 560 | *pte = val; |
| 561 | |
| 562 | smmu->soc->ops->flush_dcache(pte_page, offset, 4); |
| 563 | smmu_flush_ptc(smmu, pte_page, offset); |
| 564 | smmu_flush_tlb_group(smmu, as->id, iova); |
| 565 | smmu_flush(smmu); |
| 566 | } |
| 567 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 568 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
| 569 | phys_addr_t paddr, size_t size, int prot) |
| 570 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 571 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 572 | struct page *page; |
| 573 | u32 *pte; |
| 574 | |
| 575 | pte = as_get_pte(as, iova, &page); |
| 576 | if (!pte) |
Hiroshi Doyu | 0547c2f | 2012-06-25 14:23:57 +0300 | [diff] [blame] | 577 | return -ENOMEM; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 578 | |
Russell King | 8482ee5e | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 579 | tegra_smmu_set_pte(as, iova, pte, page, |
| 580 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 581 | |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 582 | return 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 583 | } |
| 584 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 585 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 586 | size_t size) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 587 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 588 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 589 | struct page *page; |
| 590 | u32 *pte; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 591 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 592 | pte = as_get_pte(as, iova, &page); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 593 | if (!pte || !*pte) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 594 | return 0; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 595 | |
Russell King | 8482ee5e | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 596 | tegra_smmu_set_pte(as, iova, pte, page, 0); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 597 | tegra_smmu_pte_put_use(as, iova); |
| 598 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 599 | return size; |
| 600 | } |
| 601 | |
| 602 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
| 603 | dma_addr_t iova) |
| 604 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 605 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 606 | struct page *page; |
| 607 | unsigned long pfn; |
| 608 | u32 *pte; |
| 609 | |
| 610 | pte = as_get_pte(as, iova, &page); |
Russell King | 9113785 | 2015-07-27 13:29:00 +0100 | [diff] [blame] | 611 | if (!pte || !*pte) |
| 612 | return 0; |
| 613 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 614 | pfn = *pte & as->smmu->pfn_mask; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 615 | |
| 616 | return PFN_PHYS(pfn); |
| 617 | } |
| 618 | |
| 619 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
| 620 | { |
| 621 | struct platform_device *pdev; |
| 622 | struct tegra_mc *mc; |
| 623 | |
| 624 | pdev = of_find_device_by_node(np); |
| 625 | if (!pdev) |
| 626 | return NULL; |
| 627 | |
| 628 | mc = platform_get_drvdata(pdev); |
| 629 | if (!mc) |
| 630 | return NULL; |
| 631 | |
| 632 | return mc->smmu; |
| 633 | } |
| 634 | |
| 635 | static int tegra_smmu_add_device(struct device *dev) |
| 636 | { |
| 637 | struct device_node *np = dev->of_node; |
| 638 | struct of_phandle_args args; |
| 639 | unsigned int index = 0; |
| 640 | |
| 641 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 642 | &args) == 0) { |
| 643 | struct tegra_smmu *smmu; |
| 644 | |
| 645 | smmu = tegra_smmu_find(args.np); |
| 646 | if (smmu) { |
| 647 | /* |
| 648 | * Only a single IOMMU master interface is currently |
| 649 | * supported by the Linux kernel, so abort after the |
| 650 | * first match. |
| 651 | */ |
| 652 | dev->archdata.iommu = smmu; |
| 653 | break; |
| 654 | } |
| 655 | |
| 656 | index++; |
| 657 | } |
| 658 | |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 659 | return 0; |
| 660 | } |
| 661 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 662 | static void tegra_smmu_remove_device(struct device *dev) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 663 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 664 | dev->archdata.iommu = NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 665 | } |
| 666 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 667 | static const struct iommu_ops tegra_smmu_ops = { |
| 668 | .capable = tegra_smmu_capable, |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 669 | .domain_alloc = tegra_smmu_domain_alloc, |
| 670 | .domain_free = tegra_smmu_domain_free, |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 671 | .attach_dev = tegra_smmu_attach_dev, |
| 672 | .detach_dev = tegra_smmu_detach_dev, |
| 673 | .add_device = tegra_smmu_add_device, |
| 674 | .remove_device = tegra_smmu_remove_device, |
| 675 | .map = tegra_smmu_map, |
| 676 | .unmap = tegra_smmu_unmap, |
| 677 | .map_sg = default_iommu_map_sg, |
| 678 | .iova_to_phys = tegra_smmu_iova_to_phys, |
| 679 | |
| 680 | .pgsize_bitmap = SZ_4K, |
| 681 | }; |
| 682 | |
| 683 | static void tegra_smmu_ahb_enable(void) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 684 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 685 | static const struct of_device_id ahb_match[] = { |
| 686 | { .compatible = "nvidia,tegra30-ahb", }, |
| 687 | { } |
| 688 | }; |
| 689 | struct device_node *ahb; |
| 690 | |
| 691 | ahb = of_find_matching_node(NULL, ahb_match); |
| 692 | if (ahb) { |
| 693 | tegra_ahb_enable_smmu(ahb); |
| 694 | of_node_put(ahb); |
| 695 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 696 | } |
| 697 | |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 698 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
| 699 | { |
| 700 | struct tegra_smmu *smmu = s->private; |
| 701 | unsigned int i; |
| 702 | u32 value; |
| 703 | |
| 704 | seq_printf(s, "swgroup enabled ASID\n"); |
| 705 | seq_printf(s, "------------------------\n"); |
| 706 | |
| 707 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
| 708 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; |
| 709 | const char *status; |
| 710 | unsigned int asid; |
| 711 | |
| 712 | value = smmu_readl(smmu, group->reg); |
| 713 | |
| 714 | if (value & SMMU_ASID_ENABLE) |
| 715 | status = "yes"; |
| 716 | else |
| 717 | status = "no"; |
| 718 | |
| 719 | asid = value & SMMU_ASID_MASK; |
| 720 | |
| 721 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, |
| 722 | asid); |
| 723 | } |
| 724 | |
| 725 | return 0; |
| 726 | } |
| 727 | |
| 728 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) |
| 729 | { |
| 730 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); |
| 731 | } |
| 732 | |
| 733 | static const struct file_operations tegra_smmu_swgroups_fops = { |
| 734 | .open = tegra_smmu_swgroups_open, |
| 735 | .read = seq_read, |
| 736 | .llseek = seq_lseek, |
| 737 | .release = single_release, |
| 738 | }; |
| 739 | |
| 740 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) |
| 741 | { |
| 742 | struct tegra_smmu *smmu = s->private; |
| 743 | unsigned int i; |
| 744 | u32 value; |
| 745 | |
| 746 | seq_printf(s, "client enabled\n"); |
| 747 | seq_printf(s, "--------------------\n"); |
| 748 | |
| 749 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 750 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 751 | const char *status; |
| 752 | |
| 753 | value = smmu_readl(smmu, client->smmu.reg); |
| 754 | |
| 755 | if (value & BIT(client->smmu.bit)) |
| 756 | status = "yes"; |
| 757 | else |
| 758 | status = "no"; |
| 759 | |
| 760 | seq_printf(s, "%-12s %s\n", client->name, status); |
| 761 | } |
| 762 | |
| 763 | return 0; |
| 764 | } |
| 765 | |
| 766 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) |
| 767 | { |
| 768 | return single_open(file, tegra_smmu_clients_show, inode->i_private); |
| 769 | } |
| 770 | |
| 771 | static const struct file_operations tegra_smmu_clients_fops = { |
| 772 | .open = tegra_smmu_clients_open, |
| 773 | .read = seq_read, |
| 774 | .llseek = seq_lseek, |
| 775 | .release = single_release, |
| 776 | }; |
| 777 | |
| 778 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) |
| 779 | { |
| 780 | smmu->debugfs = debugfs_create_dir("smmu", NULL); |
| 781 | if (!smmu->debugfs) |
| 782 | return; |
| 783 | |
| 784 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, |
| 785 | &tegra_smmu_swgroups_fops); |
| 786 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, |
| 787 | &tegra_smmu_clients_fops); |
| 788 | } |
| 789 | |
| 790 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) |
| 791 | { |
| 792 | debugfs_remove_recursive(smmu->debugfs); |
| 793 | } |
| 794 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 795 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
| 796 | const struct tegra_smmu_soc *soc, |
| 797 | struct tegra_mc *mc) |
| 798 | { |
| 799 | struct tegra_smmu *smmu; |
| 800 | size_t size; |
| 801 | u32 value; |
| 802 | int err; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 803 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 804 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
| 805 | if (!soc) |
| 806 | return NULL; |
| 807 | |
| 808 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
| 809 | if (!smmu) |
| 810 | return ERR_PTR(-ENOMEM); |
| 811 | |
| 812 | /* |
| 813 | * This is a bit of a hack. Ideally we'd want to simply return this |
| 814 | * value. However the IOMMU registration process will attempt to add |
| 815 | * all devices to the IOMMU when bus_set_iommu() is called. In order |
| 816 | * not to rely on global variables to track the IOMMU instance, we |
| 817 | * set it here so that it can be looked up from the .add_device() |
| 818 | * callback via the IOMMU device's .drvdata field. |
| 819 | */ |
| 820 | mc->smmu = smmu; |
| 821 | |
| 822 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
| 823 | |
| 824 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
| 825 | if (!smmu->asids) |
| 826 | return ERR_PTR(-ENOMEM); |
| 827 | |
| 828 | mutex_init(&smmu->lock); |
| 829 | |
| 830 | smmu->regs = mc->regs; |
| 831 | smmu->soc = soc; |
| 832 | smmu->dev = dev; |
| 833 | smmu->mc = mc; |
| 834 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 835 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
| 836 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", |
| 837 | mc->soc->num_address_bits, smmu->pfn_mask); |
| 838 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 839 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
| 840 | |
| 841 | if (soc->supports_request_limit) |
| 842 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); |
| 843 | |
| 844 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
| 845 | |
| 846 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
| 847 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); |
| 848 | |
| 849 | if (soc->supports_round_robin_arbitration) |
| 850 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; |
| 851 | |
| 852 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
| 853 | |
| 854 | smmu_flush_ptc(smmu, NULL, 0); |
| 855 | smmu_flush_tlb(smmu); |
| 856 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); |
| 857 | smmu_flush(smmu); |
| 858 | |
| 859 | tegra_smmu_ahb_enable(); |
| 860 | |
| 861 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
| 862 | if (err < 0) |
| 863 | return ERR_PTR(err); |
| 864 | |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 865 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 866 | tegra_smmu_debugfs_init(smmu); |
| 867 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 868 | return smmu; |
| 869 | } |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 870 | |
| 871 | void tegra_smmu_remove(struct tegra_smmu *smmu) |
| 872 | { |
| 873 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 874 | tegra_smmu_debugfs_exit(smmu); |
| 875 | } |