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Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02001/*
Thierry Reding89184652014-04-16 09:24:44 +02002 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02003 *
Thierry Reding89184652014-04-16 09:24:44 +02004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02007 */
8
Thierry Reding804cb542015-03-27 11:07:27 +01009#include <linux/bitops.h>
Thierry Redingd1313e72015-01-23 09:49:25 +010010#include <linux/debugfs.h>
Thierry Redingbc5e6de2013-01-21 11:09:06 +010011#include <linux/err.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020012#include <linux/iommu.h>
Thierry Reding89184652014-04-16 09:24:44 +020013#include <linux/kernel.h>
Hiroshi Doyu0760e8f2012-06-25 14:23:55 +030014#include <linux/of.h>
Thierry Reding89184652014-04-16 09:24:44 +020015#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
Thierry Reding306a7f92014-07-17 13:17:24 +020018
19#include <soc/tegra/ahb.h>
Thierry Reding89184652014-04-16 09:24:44 +020020#include <soc/tegra/mc.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020021
Thierry Reding89184652014-04-16 09:24:44 +020022struct tegra_smmu {
23 void __iomem *regs;
24 struct device *dev;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020025
Thierry Reding89184652014-04-16 09:24:44 +020026 struct tegra_mc *mc;
27 const struct tegra_smmu_soc *soc;
Stephen Warrene6bc5932012-09-04 16:36:15 -060028
Thierry Reding804cb542015-03-27 11:07:27 +010029 unsigned long pfn_mask;
30
Thierry Reding89184652014-04-16 09:24:44 +020031 unsigned long *asids;
32 struct mutex lock;
Stephen Warrene6bc5932012-09-04 16:36:15 -060033
Thierry Reding89184652014-04-16 09:24:44 +020034 struct list_head list;
Thierry Redingd1313e72015-01-23 09:49:25 +010035
36 struct dentry *debugfs;
Stephen Warrene6bc5932012-09-04 16:36:15 -060037};
38
Thierry Reding89184652014-04-16 09:24:44 +020039struct tegra_smmu_as {
Joerg Roedeld5f1a812015-03-26 13:43:12 +010040 struct iommu_domain domain;
Thierry Reding89184652014-04-16 09:24:44 +020041 struct tegra_smmu *smmu;
42 unsigned int use_count;
43 struct page *count;
44 struct page *pd;
45 unsigned id;
46 u32 attr;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +030047};
48
Joerg Roedeld5f1a812015-03-26 13:43:12 +010049static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
50{
51 return container_of(dom, struct tegra_smmu_as, domain);
52}
53
Thierry Reding89184652014-04-16 09:24:44 +020054static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
55 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020056{
Thierry Reding89184652014-04-16 09:24:44 +020057 writel(value, smmu->regs + offset);
Joerg Roedelfe1229b2013-02-04 20:40:58 +010058}
59
Thierry Reding89184652014-04-16 09:24:44 +020060static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020061{
Thierry Reding89184652014-04-16 09:24:44 +020062 return readl(smmu->regs + offset);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020063}
64
Thierry Reding89184652014-04-16 09:24:44 +020065#define SMMU_CONFIG 0x010
66#define SMMU_CONFIG_ENABLE (1 << 0)
67
68#define SMMU_TLB_CONFIG 0x14
69#define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
70#define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
71#define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f)
72
73#define SMMU_PTC_CONFIG 0x18
74#define SMMU_PTC_CONFIG_ENABLE (1 << 29)
75#define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
76#define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
77
78#define SMMU_PTB_ASID 0x01c
79#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
80
81#define SMMU_PTB_DATA 0x020
82#define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr))
83
84#define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr))
85
86#define SMMU_TLB_FLUSH 0x030
87#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
88#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
89#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
90#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24)
91#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
92 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
93#define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
94 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
95#define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
96
97#define SMMU_PTC_FLUSH 0x034
98#define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
99#define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
100
101#define SMMU_PTC_FLUSH_HI 0x9b8
102#define SMMU_PTC_FLUSH_HI_MASK 0x3
103
104/* per-SWGROUP SMMU_*_ASID register */
105#define SMMU_ASID_ENABLE (1 << 31)
106#define SMMU_ASID_MASK 0x7f
107#define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
108
109/* page table definitions */
110#define SMMU_NUM_PDE 1024
111#define SMMU_NUM_PTE 1024
112
113#define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
114#define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
115
116#define SMMU_PDE_SHIFT 22
117#define SMMU_PTE_SHIFT 12
118
Thierry Reding89184652014-04-16 09:24:44 +0200119#define SMMU_PD_READABLE (1 << 31)
120#define SMMU_PD_WRITABLE (1 << 30)
121#define SMMU_PD_NONSECURE (1 << 29)
122
123#define SMMU_PDE_READABLE (1 << 31)
124#define SMMU_PDE_WRITABLE (1 << 30)
125#define SMMU_PDE_NONSECURE (1 << 29)
126#define SMMU_PDE_NEXT (1 << 28)
127
128#define SMMU_PTE_READABLE (1 << 31)
129#define SMMU_PTE_WRITABLE (1 << 30)
130#define SMMU_PTE_NONSECURE (1 << 29)
131
132#define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
133 SMMU_PDE_NONSECURE)
134#define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
135 SMMU_PTE_NONSECURE)
136
137static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page,
138 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200139{
Thierry Reding89184652014-04-16 09:24:44 +0200140 phys_addr_t phys = page ? page_to_phys(page) : 0;
141 u32 value;
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200142
Thierry Reding89184652014-04-16 09:24:44 +0200143 if (page) {
144 offset &= ~(smmu->mc->soc->atom_size - 1);
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200145
Thierry Reding89184652014-04-16 09:24:44 +0200146 if (smmu->mc->soc->num_address_bits > 32) {
147#ifdef CONFIG_PHYS_ADDR_T_64BIT
148 value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200149#else
Thierry Reding89184652014-04-16 09:24:44 +0200150 value = 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200151#endif
Thierry Reding89184652014-04-16 09:24:44 +0200152 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
153 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200154
Thierry Reding89184652014-04-16 09:24:44 +0200155 value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
156 } else {
157 value = SMMU_PTC_FLUSH_TYPE_ALL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200158 }
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300159
Thierry Reding89184652014-04-16 09:24:44 +0200160 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
161}
162
163static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
164{
165 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
166}
167
168static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
169 unsigned long asid)
170{
171 u32 value;
172
173 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
174 SMMU_TLB_FLUSH_VA_MATCH_ALL;
175 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
176}
177
178static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
179 unsigned long asid,
180 unsigned long iova)
181{
182 u32 value;
183
184 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
185 SMMU_TLB_FLUSH_VA_SECTION(iova);
186 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
187}
188
189static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
190 unsigned long asid,
191 unsigned long iova)
192{
193 u32 value;
194
195 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
196 SMMU_TLB_FLUSH_VA_GROUP(iova);
197 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
198}
199
200static inline void smmu_flush(struct tegra_smmu *smmu)
201{
202 smmu_readl(smmu, SMMU_CONFIG);
203}
204
205static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
206{
207 unsigned long id;
208
209 mutex_lock(&smmu->lock);
210
211 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
212 if (id >= smmu->soc->num_asids) {
213 mutex_unlock(&smmu->lock);
214 return -ENOSPC;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200215 }
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300216
Thierry Reding89184652014-04-16 09:24:44 +0200217 set_bit(id, smmu->asids);
218 *idp = id;
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300219
Thierry Reding89184652014-04-16 09:24:44 +0200220 mutex_unlock(&smmu->lock);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200221 return 0;
222}
223
Thierry Reding89184652014-04-16 09:24:44 +0200224static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200225{
Thierry Reding89184652014-04-16 09:24:44 +0200226 mutex_lock(&smmu->lock);
227 clear_bit(id, smmu->asids);
228 mutex_unlock(&smmu->lock);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200229}
230
Thierry Reding89184652014-04-16 09:24:44 +0200231static bool tegra_smmu_capable(enum iommu_cap cap)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200232{
Joerg Roedel7c2aa642014-09-05 10:51:37 +0200233 return false;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200234}
235
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100236static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200237{
Thierry Reding89184652014-04-16 09:24:44 +0200238 struct tegra_smmu_as *as;
239 unsigned int i;
240 uint32_t *pd;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200241
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100242 if (type != IOMMU_DOMAIN_UNMANAGED)
243 return NULL;
244
Thierry Reding89184652014-04-16 09:24:44 +0200245 as = kzalloc(sizeof(*as), GFP_KERNEL);
246 if (!as)
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100247 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200248
Thierry Reding89184652014-04-16 09:24:44 +0200249 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200250
Thierry Reding89184652014-04-16 09:24:44 +0200251 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA);
252 if (!as->pd) {
253 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100254 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200255 }
256
Thierry Reding89184652014-04-16 09:24:44 +0200257 as->count = alloc_page(GFP_KERNEL);
258 if (!as->count) {
259 __free_page(as->pd);
260 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100261 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200262 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200263
Thierry Reding89184652014-04-16 09:24:44 +0200264 /* clear PDEs */
265 pd = page_address(as->pd);
266 SetPageReserved(as->pd);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200267
Thierry Reding89184652014-04-16 09:24:44 +0200268 for (i = 0; i < SMMU_NUM_PDE; i++)
269 pd[i] = 0;
Hiroshi Doyud2453b22012-07-30 08:39:18 +0300270
Thierry Reding89184652014-04-16 09:24:44 +0200271 /* clear PDE usage counters */
272 pd = page_address(as->count);
273 SetPageReserved(as->count);
Hiroshi Doyud2453b22012-07-30 08:39:18 +0300274
Thierry Reding89184652014-04-16 09:24:44 +0200275 for (i = 0; i < SMMU_NUM_PDE; i++)
276 pd[i] = 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200277
Thierry Reding471d9142015-03-27 11:07:25 +0100278 /* setup aperture */
Joerg Roedel7f65ef02015-04-02 13:33:19 +0200279 as->domain.geometry.aperture_start = 0;
280 as->domain.geometry.aperture_end = 0xffffffff;
281 as->domain.geometry.force_aperture = true;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200282
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100283 return &as->domain;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200284}
285
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100286static void tegra_smmu_domain_free(struct iommu_domain *domain)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200287{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100288 struct tegra_smmu_as *as = to_smmu_as(domain);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200289
Thierry Reding89184652014-04-16 09:24:44 +0200290 /* TODO: free page directory and page tables */
291 ClearPageReserved(as->pd);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200292
Thierry Reding89184652014-04-16 09:24:44 +0200293 kfree(as);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200294}
295
Thierry Reding89184652014-04-16 09:24:44 +0200296static const struct tegra_smmu_swgroup *
297tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300298{
Thierry Reding89184652014-04-16 09:24:44 +0200299 const struct tegra_smmu_swgroup *group = NULL;
300 unsigned int i;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300301
Thierry Reding89184652014-04-16 09:24:44 +0200302 for (i = 0; i < smmu->soc->num_swgroups; i++) {
303 if (smmu->soc->swgroups[i].swgroup == swgroup) {
304 group = &smmu->soc->swgroups[i];
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300305 break;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300306 }
307 }
308
Thierry Reding89184652014-04-16 09:24:44 +0200309 return group;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300310}
311
Thierry Reding89184652014-04-16 09:24:44 +0200312static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
313 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200314{
Thierry Reding89184652014-04-16 09:24:44 +0200315 const struct tegra_smmu_swgroup *group;
316 unsigned int i;
317 u32 value;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200318
Thierry Reding89184652014-04-16 09:24:44 +0200319 for (i = 0; i < smmu->soc->num_clients; i++) {
320 const struct tegra_mc_client *client = &smmu->soc->clients[i];
321
322 if (client->swgroup != swgroup)
323 continue;
324
325 value = smmu_readl(smmu, client->smmu.reg);
326 value |= BIT(client->smmu.bit);
327 smmu_writel(smmu, value, client->smmu.reg);
328 }
329
330 group = tegra_smmu_find_swgroup(smmu, swgroup);
331 if (group) {
332 value = smmu_readl(smmu, group->reg);
333 value &= ~SMMU_ASID_MASK;
334 value |= SMMU_ASID_VALUE(asid);
335 value |= SMMU_ASID_ENABLE;
336 smmu_writel(smmu, value, group->reg);
337 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200338}
339
Thierry Reding89184652014-04-16 09:24:44 +0200340static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
341 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200342{
Thierry Reding89184652014-04-16 09:24:44 +0200343 const struct tegra_smmu_swgroup *group;
344 unsigned int i;
345 u32 value;
346
347 group = tegra_smmu_find_swgroup(smmu, swgroup);
348 if (group) {
349 value = smmu_readl(smmu, group->reg);
350 value &= ~SMMU_ASID_MASK;
351 value |= SMMU_ASID_VALUE(asid);
352 value &= ~SMMU_ASID_ENABLE;
353 smmu_writel(smmu, value, group->reg);
354 }
355
356 for (i = 0; i < smmu->soc->num_clients; i++) {
357 const struct tegra_mc_client *client = &smmu->soc->clients[i];
358
359 if (client->swgroup != swgroup)
360 continue;
361
362 value = smmu_readl(smmu, client->smmu.reg);
363 value &= ~BIT(client->smmu.bit);
364 smmu_writel(smmu, value, client->smmu.reg);
365 }
366}
367
368static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
369 struct tegra_smmu_as *as)
370{
371 u32 value;
Hiroshi Doyu0760e8f2012-06-25 14:23:55 +0300372 int err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200373
Thierry Reding89184652014-04-16 09:24:44 +0200374 if (as->use_count > 0) {
375 as->use_count++;
376 return 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200377 }
378
Thierry Reding89184652014-04-16 09:24:44 +0200379 err = tegra_smmu_alloc_asid(smmu, &as->id);
380 if (err < 0)
Hiroshi Doyu0547c2f2012-06-25 14:23:57 +0300381 return err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200382
Thierry Reding89184652014-04-16 09:24:44 +0200383 smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD);
384 smmu_flush_ptc(smmu, as->pd, 0);
385 smmu_flush_tlb_asid(smmu, as->id);
386
387 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
388 value = SMMU_PTB_DATA_VALUE(as->pd, as->attr);
389 smmu_writel(smmu, value, SMMU_PTB_DATA);
390 smmu_flush(smmu);
391
392 as->smmu = smmu;
393 as->use_count++;
394
395 return 0;
396}
397
398static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
399 struct tegra_smmu_as *as)
400{
401 if (--as->use_count > 0)
402 return;
403
404 tegra_smmu_free_asid(smmu, as->id);
405 as->smmu = NULL;
406}
407
408static int tegra_smmu_attach_dev(struct iommu_domain *domain,
409 struct device *dev)
410{
411 struct tegra_smmu *smmu = dev->archdata.iommu;
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100412 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200413 struct device_node *np = dev->of_node;
414 struct of_phandle_args args;
415 unsigned int index = 0;
416 int err = 0;
417
418 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
419 &args)) {
420 unsigned int swgroup = args.args[0];
421
422 if (args.np != smmu->dev->of_node) {
423 of_node_put(args.np);
424 continue;
425 }
426
427 of_node_put(args.np);
428
429 err = tegra_smmu_as_prepare(smmu, as);
430 if (err < 0)
431 return err;
432
433 tegra_smmu_enable(smmu, swgroup, as->id);
434 index++;
435 }
436
437 if (index == 0)
438 return -ENODEV;
439
440 return 0;
441}
442
443static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
444{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100445 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200446 struct device_node *np = dev->of_node;
447 struct tegra_smmu *smmu = as->smmu;
448 struct of_phandle_args args;
449 unsigned int index = 0;
450
451 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
452 &args)) {
453 unsigned int swgroup = args.args[0];
454
455 if (args.np != smmu->dev->of_node) {
456 of_node_put(args.np);
457 continue;
458 }
459
460 of_node_put(args.np);
461
462 tegra_smmu_disable(smmu, swgroup, as->id);
463 tegra_smmu_as_unprepare(smmu, as);
464 index++;
465 }
466}
467
468static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
469 struct page **pagep)
470{
471 u32 *pd = page_address(as->pd), *pt, *count;
472 u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff;
473 u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff;
474 struct tegra_smmu *smmu = as->smmu;
475 struct page *page;
476 unsigned int i;
477
478 if (pd[pde] == 0) {
479 page = alloc_page(GFP_KERNEL | __GFP_DMA);
480 if (!page)
481 return NULL;
482
483 pt = page_address(page);
484 SetPageReserved(page);
485
486 for (i = 0; i < SMMU_NUM_PTE; i++)
487 pt[i] = 0;
488
489 smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT);
490
491 pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT);
492
493 smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4);
494 smmu_flush_ptc(smmu, as->pd, pde << 2);
495 smmu_flush_tlb_section(smmu, as->id, iova);
496 smmu_flush(smmu);
497 } else {
Thierry Reding804cb542015-03-27 11:07:27 +0100498 page = pfn_to_page(pd[pde] & smmu->pfn_mask);
Thierry Reding89184652014-04-16 09:24:44 +0200499 pt = page_address(page);
500 }
501
502 *pagep = page;
503
504 /* Keep track of entries in this page table. */
505 count = page_address(as->count);
506 if (pt[pte] == 0)
507 count[pde]++;
508
509 return &pt[pte];
510}
511
512static void as_put_pte(struct tegra_smmu_as *as, dma_addr_t iova)
513{
514 u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff;
515 u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff;
516 u32 *count = page_address(as->count);
517 u32 *pd = page_address(as->pd), *pt;
518 struct page *page;
519
Thierry Reding804cb542015-03-27 11:07:27 +0100520 page = pfn_to_page(pd[pde] & as->smmu->pfn_mask);
Thierry Reding89184652014-04-16 09:24:44 +0200521 pt = page_address(page);
522
523 /*
524 * When no entries in this page table are used anymore, return the
525 * memory page to the system.
526 */
527 if (pt[pte] != 0) {
528 if (--count[pde] == 0) {
529 ClearPageReserved(page);
530 __free_page(page);
531 pd[pde] = 0;
532 }
533
534 pt[pte] = 0;
535 }
536}
537
538static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
539 phys_addr_t paddr, size_t size, int prot)
540{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100541 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200542 struct tegra_smmu *smmu = as->smmu;
543 unsigned long offset;
544 struct page *page;
545 u32 *pte;
546
547 pte = as_get_pte(as, iova, &page);
548 if (!pte)
Hiroshi Doyu0547c2f2012-06-25 14:23:57 +0300549 return -ENOMEM;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200550
Thierry Reding89184652014-04-16 09:24:44 +0200551 *pte = __phys_to_pfn(paddr) | SMMU_PTE_ATTR;
552 offset = offset_in_page(pte);
553
554 smmu->soc->ops->flush_dcache(page, offset, 4);
555 smmu_flush_ptc(smmu, page, offset);
556 smmu_flush_tlb_group(smmu, as->id, iova);
557 smmu_flush(smmu);
558
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200559 return 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200560}
561
Thierry Reding89184652014-04-16 09:24:44 +0200562static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
563 size_t size)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200564{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100565 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200566 struct tegra_smmu *smmu = as->smmu;
567 unsigned long offset;
568 struct page *page;
569 u32 *pte;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200570
Thierry Reding89184652014-04-16 09:24:44 +0200571 pte = as_get_pte(as, iova, &page);
572 if (!pte)
573 return 0;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300574
Thierry Reding89184652014-04-16 09:24:44 +0200575 offset = offset_in_page(pte);
576 as_put_pte(as, iova);
577
578 smmu->soc->ops->flush_dcache(page, offset, 4);
579 smmu_flush_ptc(smmu, page, offset);
580 smmu_flush_tlb_group(smmu, as->id, iova);
581 smmu_flush(smmu);
582
583 return size;
584}
585
586static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
587 dma_addr_t iova)
588{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100589 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200590 struct page *page;
591 unsigned long pfn;
592 u32 *pte;
593
594 pte = as_get_pte(as, iova, &page);
Thierry Reding804cb542015-03-27 11:07:27 +0100595 pfn = *pte & as->smmu->pfn_mask;
Thierry Reding89184652014-04-16 09:24:44 +0200596
597 return PFN_PHYS(pfn);
598}
599
600static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
601{
602 struct platform_device *pdev;
603 struct tegra_mc *mc;
604
605 pdev = of_find_device_by_node(np);
606 if (!pdev)
607 return NULL;
608
609 mc = platform_get_drvdata(pdev);
610 if (!mc)
611 return NULL;
612
613 return mc->smmu;
614}
615
616static int tegra_smmu_add_device(struct device *dev)
617{
618 struct device_node *np = dev->of_node;
619 struct of_phandle_args args;
620 unsigned int index = 0;
621
622 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
623 &args) == 0) {
624 struct tegra_smmu *smmu;
625
626 smmu = tegra_smmu_find(args.np);
627 if (smmu) {
628 /*
629 * Only a single IOMMU master interface is currently
630 * supported by the Linux kernel, so abort after the
631 * first match.
632 */
633 dev->archdata.iommu = smmu;
634 break;
635 }
636
637 index++;
638 }
639
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200640 return 0;
641}
642
Thierry Reding89184652014-04-16 09:24:44 +0200643static void tegra_smmu_remove_device(struct device *dev)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200644{
Thierry Reding89184652014-04-16 09:24:44 +0200645 dev->archdata.iommu = NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200646}
647
Thierry Reding89184652014-04-16 09:24:44 +0200648static const struct iommu_ops tegra_smmu_ops = {
649 .capable = tegra_smmu_capable,
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100650 .domain_alloc = tegra_smmu_domain_alloc,
651 .domain_free = tegra_smmu_domain_free,
Thierry Reding89184652014-04-16 09:24:44 +0200652 .attach_dev = tegra_smmu_attach_dev,
653 .detach_dev = tegra_smmu_detach_dev,
654 .add_device = tegra_smmu_add_device,
655 .remove_device = tegra_smmu_remove_device,
656 .map = tegra_smmu_map,
657 .unmap = tegra_smmu_unmap,
658 .map_sg = default_iommu_map_sg,
659 .iova_to_phys = tegra_smmu_iova_to_phys,
660
661 .pgsize_bitmap = SZ_4K,
662};
663
664static void tegra_smmu_ahb_enable(void)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200665{
Thierry Reding89184652014-04-16 09:24:44 +0200666 static const struct of_device_id ahb_match[] = {
667 { .compatible = "nvidia,tegra30-ahb", },
668 { }
669 };
670 struct device_node *ahb;
671
672 ahb = of_find_matching_node(NULL, ahb_match);
673 if (ahb) {
674 tegra_ahb_enable_smmu(ahb);
675 of_node_put(ahb);
676 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200677}
678
Thierry Redingd1313e72015-01-23 09:49:25 +0100679static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
680{
681 struct tegra_smmu *smmu = s->private;
682 unsigned int i;
683 u32 value;
684
685 seq_printf(s, "swgroup enabled ASID\n");
686 seq_printf(s, "------------------------\n");
687
688 for (i = 0; i < smmu->soc->num_swgroups; i++) {
689 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
690 const char *status;
691 unsigned int asid;
692
693 value = smmu_readl(smmu, group->reg);
694
695 if (value & SMMU_ASID_ENABLE)
696 status = "yes";
697 else
698 status = "no";
699
700 asid = value & SMMU_ASID_MASK;
701
702 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
703 asid);
704 }
705
706 return 0;
707}
708
709static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file)
710{
711 return single_open(file, tegra_smmu_swgroups_show, inode->i_private);
712}
713
714static const struct file_operations tegra_smmu_swgroups_fops = {
715 .open = tegra_smmu_swgroups_open,
716 .read = seq_read,
717 .llseek = seq_lseek,
718 .release = single_release,
719};
720
721static int tegra_smmu_clients_show(struct seq_file *s, void *data)
722{
723 struct tegra_smmu *smmu = s->private;
724 unsigned int i;
725 u32 value;
726
727 seq_printf(s, "client enabled\n");
728 seq_printf(s, "--------------------\n");
729
730 for (i = 0; i < smmu->soc->num_clients; i++) {
731 const struct tegra_mc_client *client = &smmu->soc->clients[i];
732 const char *status;
733
734 value = smmu_readl(smmu, client->smmu.reg);
735
736 if (value & BIT(client->smmu.bit))
737 status = "yes";
738 else
739 status = "no";
740
741 seq_printf(s, "%-12s %s\n", client->name, status);
742 }
743
744 return 0;
745}
746
747static int tegra_smmu_clients_open(struct inode *inode, struct file *file)
748{
749 return single_open(file, tegra_smmu_clients_show, inode->i_private);
750}
751
752static const struct file_operations tegra_smmu_clients_fops = {
753 .open = tegra_smmu_clients_open,
754 .read = seq_read,
755 .llseek = seq_lseek,
756 .release = single_release,
757};
758
759static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
760{
761 smmu->debugfs = debugfs_create_dir("smmu", NULL);
762 if (!smmu->debugfs)
763 return;
764
765 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
766 &tegra_smmu_swgroups_fops);
767 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
768 &tegra_smmu_clients_fops);
769}
770
771static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
772{
773 debugfs_remove_recursive(smmu->debugfs);
774}
775
Thierry Reding89184652014-04-16 09:24:44 +0200776struct tegra_smmu *tegra_smmu_probe(struct device *dev,
777 const struct tegra_smmu_soc *soc,
778 struct tegra_mc *mc)
779{
780 struct tegra_smmu *smmu;
781 size_t size;
782 u32 value;
783 int err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200784
Thierry Reding89184652014-04-16 09:24:44 +0200785 /* This can happen on Tegra20 which doesn't have an SMMU */
786 if (!soc)
787 return NULL;
788
789 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
790 if (!smmu)
791 return ERR_PTR(-ENOMEM);
792
793 /*
794 * This is a bit of a hack. Ideally we'd want to simply return this
795 * value. However the IOMMU registration process will attempt to add
796 * all devices to the IOMMU when bus_set_iommu() is called. In order
797 * not to rely on global variables to track the IOMMU instance, we
798 * set it here so that it can be looked up from the .add_device()
799 * callback via the IOMMU device's .drvdata field.
800 */
801 mc->smmu = smmu;
802
803 size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
804
805 smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
806 if (!smmu->asids)
807 return ERR_PTR(-ENOMEM);
808
809 mutex_init(&smmu->lock);
810
811 smmu->regs = mc->regs;
812 smmu->soc = soc;
813 smmu->dev = dev;
814 smmu->mc = mc;
815
Thierry Reding804cb542015-03-27 11:07:27 +0100816 smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
817 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
818 mc->soc->num_address_bits, smmu->pfn_mask);
819
Thierry Reding89184652014-04-16 09:24:44 +0200820 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
821
822 if (soc->supports_request_limit)
823 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
824
825 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
826
827 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
828 SMMU_TLB_CONFIG_ACTIVE_LINES(0x20);
829
830 if (soc->supports_round_robin_arbitration)
831 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
832
833 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
834
835 smmu_flush_ptc(smmu, NULL, 0);
836 smmu_flush_tlb(smmu);
837 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
838 smmu_flush(smmu);
839
840 tegra_smmu_ahb_enable();
841
842 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
843 if (err < 0)
844 return ERR_PTR(err);
845
Thierry Redingd1313e72015-01-23 09:49:25 +0100846 if (IS_ENABLED(CONFIG_DEBUG_FS))
847 tegra_smmu_debugfs_init(smmu);
848
Thierry Reding89184652014-04-16 09:24:44 +0200849 return smmu;
850}
Thierry Redingd1313e72015-01-23 09:49:25 +0100851
852void tegra_smmu_remove(struct tegra_smmu *smmu)
853{
854 if (IS_ENABLED(CONFIG_DEBUG_FS))
855 tegra_smmu_debugfs_exit(smmu);
856}