sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 1 | /* |
Sricharan R | c10d5c9 | 2014-04-11 13:09:36 -0500 | [diff] [blame] | 2 | * OMAP L3 Interconnect error handling driver header |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 3 | * |
Nishanth Menon | c5f2aea | 2014-04-11 13:15:43 -0500 | [diff] [blame] | 4 | * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 6 | * sricharan <r.sricharan@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
Nishanth Menon | c5f2aea | 2014-04-11 13:15:43 -0500 | [diff] [blame] | 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 11 | * |
Nishanth Menon | c5f2aea | 2014-04-11 13:15:43 -0500 | [diff] [blame] | 12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 13 | * kind, whether express or implied; without even the implied warranty |
| 14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 15 | * GNU General Public License for more details. |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 16 | */ |
Sricharan R | c10d5c9 | 2014-04-11 13:09:36 -0500 | [diff] [blame] | 17 | #ifndef __OMAP_L3_NOC_H |
| 18 | #define __OMAP_L3_NOC_H |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 19 | |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 20 | #define L3_MODULES 3 |
| 21 | #define CLEAR_STDERR_LOG (1 << 31) |
| 22 | #define CUSTOM_ERROR 0x2 |
| 23 | #define STANDARD_ERROR 0x0 |
| 24 | #define INBAND_ERROR 0x0 |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 25 | #define L3_APPLICATION_ERROR 0x0 |
| 26 | #define L3_DEBUG_ERROR 0x1 |
| 27 | |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 28 | /* L3 TARG register offsets */ |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 29 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
| 30 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
sricharan | 551a9fa | 2011-09-07 17:25:16 +0530 | [diff] [blame] | 31 | #define L3_TARG_STDERRLOG_MSTADDR 0x68 |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 32 | #define L3_FLAGMUX_REGERR0 0xc |
Rajendra Nayak | 3340d73 | 2014-04-10 11:31:33 -0500 | [diff] [blame^] | 33 | #define L3_FLAGMUX_MASK0 0x8 |
| 34 | |
| 35 | #define L3_TARGET_NOT_SUPPORTED NULL |
| 36 | |
| 37 | #define MAX_CLKDM_TARGETS 31 |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 38 | |
sricharan | 551a9fa | 2011-09-07 17:25:16 +0530 | [diff] [blame] | 39 | #define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0])) |
| 40 | |
Nishanth Menon | f0a6e65 | 2014-04-11 10:11:59 -0500 | [diff] [blame] | 41 | /** |
| 42 | * struct l3_masters_data - L3 Master information |
| 43 | * @id: ID of the L3 Master |
| 44 | * @name: master name |
| 45 | */ |
| 46 | struct l3_masters_data { |
| 47 | u32 id; |
| 48 | char *name; |
| 49 | }; |
| 50 | |
Nishanth Menon | 3ae9af7 | 2014-04-11 11:38:10 -0500 | [diff] [blame] | 51 | /** |
| 52 | * struct l3_target_data - L3 Target information |
| 53 | * @offset: Offset from base for L3 Target |
| 54 | * @name: Target name |
| 55 | * |
| 56 | * Target information is organized indexed by bit field definitions. |
| 57 | */ |
| 58 | struct l3_target_data { |
| 59 | u32 offset; |
| 60 | char *name; |
| 61 | }; |
| 62 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame] | 63 | static u32 l3_flagmux[L3_MODULES] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 64 | 0x500, |
| 65 | 0x1000, |
| 66 | 0X0200 |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 67 | }; |
| 68 | |
Rajendra Nayak | 3340d73 | 2014-04-10 11:31:33 -0500 | [diff] [blame^] | 69 | static struct l3_target_data l3_target_inst_data_clk1[MAX_CLKDM_TARGETS] = { |
Nishanth Menon | 3ae9af7 | 2014-04-11 11:38:10 -0500 | [diff] [blame] | 70 | {0x100, "DMM1",}, |
| 71 | {0x200, "DMM2",}, |
| 72 | {0x300, "ABE",}, |
| 73 | {0x400, "L4CFG",}, |
| 74 | {0x600, "CLK2PWRDISC",}, |
| 75 | {0x0, "HOSTCLK1",}, |
| 76 | {0x900, "L4WAKEUP",}, |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 77 | }; |
| 78 | |
Rajendra Nayak | 3340d73 | 2014-04-10 11:31:33 -0500 | [diff] [blame^] | 79 | static struct l3_target_data l3_target_inst_data_clk2[MAX_CLKDM_TARGETS] = { |
Nishanth Menon | 3ae9af7 | 2014-04-11 11:38:10 -0500 | [diff] [blame] | 80 | {0x500, "CORTEXM3",}, |
| 81 | {0x300, "DSS",}, |
| 82 | {0x100, "GPMC",}, |
| 83 | {0x400, "ISS",}, |
| 84 | {0x700, "IVAHD",}, |
| 85 | {0xD00, "AES1",}, |
| 86 | {0x900, "L4PER0",}, |
| 87 | {0x200, "OCMRAM",}, |
| 88 | {0x100, "GPMCsERROR",}, |
| 89 | {0x600, "SGX",}, |
| 90 | {0x800, "SL2",}, |
| 91 | {0x1600, "C2C",}, |
| 92 | {0x1100, "PWRDISCCLK1",}, |
| 93 | {0xF00, "SHA1",}, |
| 94 | {0xE00, "AES2",}, |
| 95 | {0xC00, "L4PER3",}, |
| 96 | {0xA00, "L4PER1",}, |
| 97 | {0xB00, "L4PER2",}, |
| 98 | {0x0, "HOSTCLK2",}, |
| 99 | {0x1800, "CAL",}, |
| 100 | {0x1700, "LLI",}, |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 101 | }; |
| 102 | |
Rajendra Nayak | 3340d73 | 2014-04-10 11:31:33 -0500 | [diff] [blame^] | 103 | static struct l3_target_data l3_target_inst_data_clk3[MAX_CLKDM_TARGETS] = { |
Nishanth Menon | 3ae9af7 | 2014-04-11 11:38:10 -0500 | [diff] [blame] | 104 | {0x0100, "EMUSS",}, |
| 105 | {0x0300, "DEBUG SOURCE",}, |
| 106 | {0x0, "HOST CLK3",}, |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 107 | }; |
| 108 | |
Nishanth Menon | f0a6e65 | 2014-04-11 10:11:59 -0500 | [diff] [blame] | 109 | static struct l3_masters_data l3_masters[] = { |
sricharan | 551a9fa | 2011-09-07 17:25:16 +0530 | [diff] [blame] | 110 | { 0x0 , "MPU"}, |
| 111 | { 0x10, "CS_ADP"}, |
| 112 | { 0x14, "xxx"}, |
| 113 | { 0x20, "DSP"}, |
| 114 | { 0x30, "IVAHD"}, |
| 115 | { 0x40, "ISS"}, |
| 116 | { 0x44, "DucatiM3"}, |
| 117 | { 0x48, "FaceDetect"}, |
| 118 | { 0x50, "SDMA_Rd"}, |
| 119 | { 0x54, "SDMA_Wr"}, |
| 120 | { 0x58, "xxx"}, |
| 121 | { 0x5C, "xxx"}, |
| 122 | { 0x60, "SGX"}, |
| 123 | { 0x70, "DSS"}, |
| 124 | { 0x80, "C2C"}, |
| 125 | { 0x88, "xxx"}, |
| 126 | { 0x8C, "xxx"}, |
| 127 | { 0x90, "HSI"}, |
| 128 | { 0xA0, "MMC1"}, |
| 129 | { 0xA4, "MMC2"}, |
| 130 | { 0xA8, "MMC6"}, |
| 131 | { 0xB0, "UNIPRO1"}, |
| 132 | { 0xC0, "USBHOSTHS"}, |
| 133 | { 0xC4, "USBOTGHS"}, |
| 134 | { 0xC8, "USBHOSTFS"} |
| 135 | }; |
| 136 | |
Nishanth Menon | 3ae9af7 | 2014-04-11 11:38:10 -0500 | [diff] [blame] | 137 | static struct l3_target_data *l3_targ[L3_MODULES] = { |
| 138 | l3_target_inst_data_clk1, |
| 139 | l3_target_inst_data_clk2, |
| 140 | l3_target_inst_data_clk3, |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 141 | }; |
| 142 | |
Sricharan R | c10d5c9 | 2014-04-11 13:09:36 -0500 | [diff] [blame] | 143 | struct omap_l3 { |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 144 | struct device *dev; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 145 | |
| 146 | /* memory base */ |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 147 | void __iomem *l3_base[L3_MODULES]; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 148 | |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 149 | int debug_irq; |
| 150 | int app_irq; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 151 | }; |
Sricharan R | c10d5c9 | 2014-04-11 13:09:36 -0500 | [diff] [blame] | 152 | |
| 153 | #endif /* __OMAP_L3_NOC_H */ |