Gitiles
Code Review Sign In
android-review.linaro.org / kernel / hikey-linaro / c10d5c9e1200e2b8c23329173f279caa86c6af45 / . / drivers / bus / omap_l3_noc.h
blob: b3c81f2fe7a295c13bfdfd1cd6c6539413c4335b [file] [log] [blame]
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]1/*
Sricharan Rc10d5c92014-04-11 13:09:36 -0500[diff] [blame^]2 * OMAP L3 Interconnect error handling driver header
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]3 *
Nishanth Menonc5f2aea2014-04-11 13:15:43 -0500[diff] [blame]4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
Nishanth Menonc5f2aea2014-04-11 13:15:43 -0500[diff] [blame]9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]11 *
Nishanth Menonc5f2aea2014-04-11 13:15:43 -0500[diff] [blame]12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]15 * GNU General Public License for more details.
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]16 */
Sricharan Rc10d5c92014-04-11 13:09:36 -0500[diff] [blame^]17#ifndef __OMAP_L3_NOC_H
18#define __OMAP_L3_NOC_H
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]19
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]20#define L3_MODULES 3
21#define CLEAR_STDERR_LOG (1 << 31)
22#define CUSTOM_ERROR 0x2
23#define STANDARD_ERROR 0x0
24#define INBAND_ERROR 0x0
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]25#define L3_APPLICATION_ERROR 0x0
26#define L3_DEBUG_ERROR 0x1
27
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]28/* L3 TARG register offsets */
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]29#define L3_TARG_STDERRLOG_MAIN 0x48
30#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
sricharan551a9fa2011-09-07 17:25:16 +0530[diff] [blame]31#define L3_TARG_STDERRLOG_MSTADDR 0x68
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]32#define L3_FLAGMUX_REGERR0 0xc
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]33
sricharan551a9fa2011-09-07 17:25:16 +0530[diff] [blame]34#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
35
sricharan6616aac2011-08-23 12:58:48 +0530[diff] [blame]36static u32 l3_flagmux[L3_MODULES] = {
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]37 0x500,
38 0x1000,
39 0X0200
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]40};
41
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]42/* L3 Target standard Error register offsets */
sricharan6616aac2011-08-23 12:58:48 +0530[diff] [blame]43static u32 l3_targ_inst_clk1[] = {
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]44 0x100, /* DMM1 */
45 0x200, /* DMM2 */
46 0x300, /* ABE */
47 0x400, /* L4CFG */
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]48 0x600, /* CLK2 PWR DISC */
49 0x0, /* Host CLK1 */
50 0x900 /* L4 Wakeup */
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]51};
52
sricharan6616aac2011-08-23 12:58:48 +0530[diff] [blame]53static u32 l3_targ_inst_clk2[] = {
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]54 0x500, /* CORTEX M3 */
55 0x300, /* DSS */
56 0x100, /* GPMC */
57 0x400, /* ISS */
58 0x700, /* IVAHD */
59 0xD00, /* missing in TRM corresponds to AES1*/
60 0x900, /* L4 PER0*/
61 0x200, /* OCMRAM */
62 0x100, /* missing in TRM corresponds to GPMC sERROR*/
63 0x600, /* SGX */
64 0x800, /* SL2 */
65 0x1600, /* C2C */
66 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
67 0xF00, /* missing in TRM corrsponds to SHA1*/
68 0xE00, /* missing in TRM corresponds to AES2*/
69 0xC00, /* L4 PER3 */
70 0xA00, /* L4 PER1*/
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]71 0xB00, /* L4 PER2*/
72 0x0, /* HOST CLK2 */
73 0x1800, /* CAL */
74 0x1700 /* LLI */
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]75};
76
sricharan6616aac2011-08-23 12:58:48 +0530[diff] [blame]77static u32 l3_targ_inst_clk3[] = {
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]78 0x0100 /* EMUSS */,
79 0x0300, /* DEBUGSS_CT_TBR */
80 0x0 /* HOST CLK3 */
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]81};
82
sricharan551a9fa2011-09-07 17:25:16 +0530[diff] [blame]83static struct l3_masters_data {
84 u32 id;
85 char name[10];
86} l3_masters[] = {
87 { 0x0 , "MPU"},
88 { 0x10, "CS_ADP"},
89 { 0x14, "xxx"},
90 { 0x20, "DSP"},
91 { 0x30, "IVAHD"},
92 { 0x40, "ISS"},
93 { 0x44, "DucatiM3"},
94 { 0x48, "FaceDetect"},
95 { 0x50, "SDMA_Rd"},
96 { 0x54, "SDMA_Wr"},
97 { 0x58, "xxx"},
98 { 0x5C, "xxx"},
99 { 0x60, "SGX"},
100 { 0x70, "DSS"},
101 { 0x80, "C2C"},
102 { 0x88, "xxx"},
103 { 0x8C, "xxx"},
104 { 0x90, "HSI"},
105 { 0xA0, "MMC1"},
106 { 0xA4, "MMC2"},
107 { 0xA8, "MMC6"},
108 { 0xB0, "UNIPRO1"},
109 { 0xC0, "USBHOSTHS"},
110 { 0xC4, "USBOTGHS"},
111 { 0xC8, "USBHOSTFS"}
112};
113
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]114static char *l3_targ_inst_name[L3_MODULES][21] = {
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]115 {
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]116 "DMM1",
117 "DMM2",
118 "ABE",
119 "L4CFG",
120 "CLK2 PWR DISC",
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]121 "HOST CLK1",
122 "L4 WAKEUP"
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]123 },
124 {
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]125 "CORTEX M3" ,
126 "DSS ",
127 "GPMC ",
128 "ISS ",
129 "IVAHD ",
130 "AES1",
131 "L4 PER0",
132 "OCMRAM ",
133 "GPMC sERROR",
134 "SGX ",
135 "SL2 ",
136 "C2C ",
137 "PWR DISC CLK1",
138 "SHA1",
139 "AES2",
140 "L4 PER3",
141 "L4 PER1",
142 "L4 PER2",
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]143 "HOST CLK2",
144 "CAL",
145 "LLI"
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]146 },
147 {
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]148 "EMUSS",
R Sricharane17933c2011-11-04 15:52:59 +0530[diff] [blame]149 "DEBUG SOURCE",
150 "HOST CLK3"
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]151 },
152};
153
sricharan6616aac2011-08-23 12:58:48 +0530[diff] [blame]154static u32 *l3_targ[L3_MODULES] = {
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]155 l3_targ_inst_clk1,
156 l3_targ_inst_clk2,
157 l3_targ_inst_clk3,
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]158};
159
Sricharan Rc10d5c92014-04-11 13:09:36 -0500[diff] [blame^]160struct omap_l3 {
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]161 struct device *dev;
162 struct clk *ick;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]163
164 /* memory base */
Todd Poynor342fd142011-08-24 19:11:39 +0530[diff] [blame]165 void __iomem *l3_base[L3_MODULES];
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]166
sricharaned0e3522011-08-24 20:07:45 +0530[diff] [blame]167 int debug_irq;
168 int app_irq;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530[diff] [blame]169};
Sricharan Rc10d5c92014-04-11 13:09:36 -0500[diff] [blame^]170
171#endif /* __OMAP_L3_NOC_H */