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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08002 * MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08008 * This file contains the interface independent core functions.
9 *
Chen-Yu Tsaie7402352016-02-12 10:02:41 +080010 * Copyright (C) 2014 Carlo Caione
11 *
Carlo Caionecfb61a42014-05-01 14:29:27 +020012 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020020#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020025#include <linux/regulator/consumer.h>
26#include <linux/mfd/axp20x.h>
27#include <linux/mfd/core.h>
28#include <linux/of_device.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070029#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020030
31#define AXP20X_OFF 0x80
32
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010033static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020034 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070035 "AXP202",
36 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080037 "AXP221",
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080038 "AXP223",
Jacob Panaf7e9062014-10-06 21:17:14 -070039 "AXP288",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080040 "AXP809",
Jacob Panaf7e9062014-10-06 21:17:14 -070041};
42
Michal Suchanekd8d79f82015-07-11 14:59:56 +020043static const struct regmap_range axp152_writeable_ranges[] = {
44 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
45 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
46};
47
48static const struct regmap_range axp152_volatile_ranges[] = {
49 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
50 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
51 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
52};
53
54static const struct regmap_access_table axp152_writeable_table = {
55 .yes_ranges = axp152_writeable_ranges,
56 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
57};
58
59static const struct regmap_access_table axp152_volatile_table = {
60 .yes_ranges = axp152_volatile_ranges,
61 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
62};
63
Carlo Caionecfb61a42014-05-01 14:29:27 +020064static const struct regmap_range axp20x_writeable_ranges[] = {
65 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
66 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020067 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
Carlo Caionecfb61a42014-05-01 14:29:27 +020068};
69
70static const struct regmap_range axp20x_volatile_ranges[] = {
Bruno Prémont553ed4b2015-08-08 17:58:40 +020071 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
72 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020073 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020074 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
75 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
76 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
Carlo Caionecfb61a42014-05-01 14:29:27 +020077};
78
79static const struct regmap_access_table axp20x_writeable_table = {
80 .yes_ranges = axp20x_writeable_ranges,
81 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
82};
83
84static const struct regmap_access_table axp20x_volatile_table = {
85 .yes_ranges = axp20x_volatile_ranges,
86 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
87};
88
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080089/* AXP22x ranges are shared with the AXP809, as they cover the same range */
Boris BREZILLONf05be582015-04-10 12:09:01 +080090static const struct regmap_range axp22x_writeable_ranges[] = {
91 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
92 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
93};
94
95static const struct regmap_range axp22x_volatile_ranges[] = {
Hans de Goede15093252016-05-14 19:51:28 +020096 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
Boris BREZILLONf05be582015-04-10 12:09:01 +080097 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Hans de Goede15093252016-05-14 19:51:28 +020098 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
99 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800100};
101
102static const struct regmap_access_table axp22x_writeable_table = {
103 .yes_ranges = axp22x_writeable_ranges,
104 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
105};
106
107static const struct regmap_access_table axp22x_volatile_table = {
108 .yes_ranges = axp22x_volatile_ranges,
109 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
110};
111
Jacob Panaf7e9062014-10-06 21:17:14 -0700112static const struct regmap_range axp288_writeable_ranges[] = {
113 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
114 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
115};
116
117static const struct regmap_range axp288_volatile_ranges[] = {
118 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
119};
120
121static const struct regmap_access_table axp288_writeable_table = {
122 .yes_ranges = axp288_writeable_ranges,
123 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
124};
125
126static const struct regmap_access_table axp288_volatile_table = {
127 .yes_ranges = axp288_volatile_ranges,
128 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
129};
130
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200131static struct resource axp152_pek_resources[] = {
132 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
133 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
134};
135
Michael Haascd7cf272016-05-06 07:19:49 +0200136static struct resource axp20x_ac_power_supply_resources[] = {
137 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
138 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
139 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
140};
141
Carlo Caionecfb61a42014-05-01 14:29:27 +0200142static struct resource axp20x_pek_resources[] = {
143 {
144 .name = "PEK_DBR",
145 .start = AXP20X_IRQ_PEK_RIS_EDGE,
146 .end = AXP20X_IRQ_PEK_RIS_EDGE,
147 .flags = IORESOURCE_IRQ,
148 }, {
149 .name = "PEK_DBF",
150 .start = AXP20X_IRQ_PEK_FAL_EDGE,
151 .end = AXP20X_IRQ_PEK_FAL_EDGE,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
Hans de Goede8de4efd2015-08-08 17:58:41 +0200156static struct resource axp20x_usb_power_supply_resources[] = {
157 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
158 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
159 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
160 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
161};
162
Boris BREZILLONf05be582015-04-10 12:09:01 +0800163static struct resource axp22x_pek_resources[] = {
164 {
165 .name = "PEK_DBR",
166 .start = AXP22X_IRQ_PEK_RIS_EDGE,
167 .end = AXP22X_IRQ_PEK_RIS_EDGE,
168 .flags = IORESOURCE_IRQ,
169 }, {
170 .name = "PEK_DBF",
171 .start = AXP22X_IRQ_PEK_FAL_EDGE,
172 .end = AXP22X_IRQ_PEK_FAL_EDGE,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
Borun Fue56e5ad2015-10-14 16:16:26 +0800177static struct resource axp288_power_button_resources[] = {
178 {
179 .name = "PEK_DBR",
180 .start = AXP288_IRQ_POKN,
181 .end = AXP288_IRQ_POKN,
182 .flags = IORESOURCE_IRQ,
183 },
184 {
185 .name = "PEK_DBF",
186 .start = AXP288_IRQ_POKP,
187 .end = AXP288_IRQ_POKP,
188 .flags = IORESOURCE_IRQ,
189 },
190};
191
Todd Brandtd63878742015-02-02 15:41:41 -0800192static struct resource axp288_fuel_gauge_resources[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700193 {
194 .start = AXP288_IRQ_QWBTU,
195 .end = AXP288_IRQ_QWBTU,
196 .flags = IORESOURCE_IRQ,
197 },
198 {
199 .start = AXP288_IRQ_WBTU,
200 .end = AXP288_IRQ_WBTU,
201 .flags = IORESOURCE_IRQ,
202 },
203 {
204 .start = AXP288_IRQ_QWBTO,
205 .end = AXP288_IRQ_QWBTO,
206 .flags = IORESOURCE_IRQ,
207 },
208 {
209 .start = AXP288_IRQ_WBTO,
210 .end = AXP288_IRQ_WBTO,
211 .flags = IORESOURCE_IRQ,
212 },
213 {
214 .start = AXP288_IRQ_WL2,
215 .end = AXP288_IRQ_WL2,
216 .flags = IORESOURCE_IRQ,
217 },
218 {
219 .start = AXP288_IRQ_WL1,
220 .end = AXP288_IRQ_WL1,
221 .flags = IORESOURCE_IRQ,
222 },
223};
224
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800225static struct resource axp809_pek_resources[] = {
226 {
227 .name = "PEK_DBR",
228 .start = AXP809_IRQ_PEK_RIS_EDGE,
229 .end = AXP809_IRQ_PEK_RIS_EDGE,
230 .flags = IORESOURCE_IRQ,
231 }, {
232 .name = "PEK_DBF",
233 .start = AXP809_IRQ_PEK_FAL_EDGE,
234 .end = AXP809_IRQ_PEK_FAL_EDGE,
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200239static const struct regmap_config axp152_regmap_config = {
240 .reg_bits = 8,
241 .val_bits = 8,
242 .wr_table = &axp152_writeable_table,
243 .volatile_table = &axp152_volatile_table,
244 .max_register = AXP152_PWM1_DUTY_CYCLE,
245 .cache_type = REGCACHE_RBTREE,
246};
247
Carlo Caionecfb61a42014-05-01 14:29:27 +0200248static const struct regmap_config axp20x_regmap_config = {
249 .reg_bits = 8,
250 .val_bits = 8,
251 .wr_table = &axp20x_writeable_table,
252 .volatile_table = &axp20x_volatile_table,
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200253 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200254 .cache_type = REGCACHE_RBTREE,
255};
256
Boris BREZILLONf05be582015-04-10 12:09:01 +0800257static const struct regmap_config axp22x_regmap_config = {
258 .reg_bits = 8,
259 .val_bits = 8,
260 .wr_table = &axp22x_writeable_table,
261 .volatile_table = &axp22x_volatile_table,
262 .max_register = AXP22X_BATLOW_THRES1,
263 .cache_type = REGCACHE_RBTREE,
264};
265
Jacob Panaf7e9062014-10-06 21:17:14 -0700266static const struct regmap_config axp288_regmap_config = {
267 .reg_bits = 8,
268 .val_bits = 8,
269 .wr_table = &axp288_writeable_table,
270 .volatile_table = &axp288_volatile_table,
271 .max_register = AXP288_FG_TUNE5,
272 .cache_type = REGCACHE_RBTREE,
273};
274
275#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
276 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200277
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200278static const struct regmap_irq axp152_regmap_irqs[] = {
279 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
280 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
281 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
282 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
283 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
284 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
285 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
286 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
287 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
288 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
289 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
290 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
291 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
292 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
293 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
294 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
295 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
296};
297
Carlo Caionecfb61a42014-05-01 14:29:27 +0200298static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700299 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
300 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
301 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
302 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
303 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
304 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
305 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
306 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
307 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
308 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
309 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
310 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
311 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
312 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
313 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
314 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
315 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
316 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
317 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
318 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
319 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
320 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
321 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
322 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
323 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
324 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
325 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
326 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
327 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
328 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
329 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
330 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
331 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
332 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
333 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
334 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
335 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
336};
337
Boris BREZILLONf05be582015-04-10 12:09:01 +0800338static const struct regmap_irq axp22x_regmap_irqs[] = {
339 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
340 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
341 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
342 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
343 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
344 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
345 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
346 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
347 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
348 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
349 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
350 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
351 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
352 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
353 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
354 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
355 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
356 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
357 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
358 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
359 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
360 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
361 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
362 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
363 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
364};
365
Jacob Panaf7e9062014-10-06 21:17:14 -0700366/* some IRQs are compatible with axp20x models */
367static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800368 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
369 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
370 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Jacob Panaf7e9062014-10-06 21:17:14 -0700371
Jacob Panff3bbc52014-11-11 11:30:09 -0800372 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
373 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700374 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
375 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800376 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
377 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700378
379 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
380 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
381 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800382 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700383 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
384 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
385 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
386 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
387
388 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
389 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
390 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
391 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
392
393 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
394 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
395 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
396 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
397 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
398 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
399 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800400 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700401
402 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
403 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200404};
405
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800406static const struct regmap_irq axp809_regmap_irqs[] = {
407 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
408 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
409 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
410 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
411 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
412 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
413 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
414 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
415 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
416 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
417 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
418 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
419 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
420 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
421 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
422 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
423 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
424 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
425 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
426 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
427 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
428 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
429 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
430 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
431 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
432 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
433 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
434 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
435 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
436 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
437 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
438 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
439};
440
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200441static const struct regmap_irq_chip axp152_regmap_irq_chip = {
442 .name = "axp152_irq_chip",
443 .status_base = AXP152_IRQ1_STATE,
444 .ack_base = AXP152_IRQ1_STATE,
445 .mask_base = AXP152_IRQ1_EN,
446 .mask_invert = true,
447 .init_ack_masked = true,
448 .irqs = axp152_regmap_irqs,
449 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
450 .num_regs = 3,
451};
452
Carlo Caionecfb61a42014-05-01 14:29:27 +0200453static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
454 .name = "axp20x_irq_chip",
455 .status_base = AXP20X_IRQ1_STATE,
456 .ack_base = AXP20X_IRQ1_STATE,
457 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200458 .mask_invert = true,
459 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700460 .irqs = axp20x_regmap_irqs,
461 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
462 .num_regs = 5,
463
464};
465
Boris BREZILLONf05be582015-04-10 12:09:01 +0800466static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
467 .name = "axp22x_irq_chip",
468 .status_base = AXP20X_IRQ1_STATE,
469 .ack_base = AXP20X_IRQ1_STATE,
470 .mask_base = AXP20X_IRQ1_EN,
471 .mask_invert = true,
472 .init_ack_masked = true,
473 .irqs = axp22x_regmap_irqs,
474 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
475 .num_regs = 5,
476};
477
Jacob Panaf7e9062014-10-06 21:17:14 -0700478static const struct regmap_irq_chip axp288_regmap_irq_chip = {
479 .name = "axp288_irq_chip",
480 .status_base = AXP20X_IRQ1_STATE,
481 .ack_base = AXP20X_IRQ1_STATE,
482 .mask_base = AXP20X_IRQ1_EN,
483 .mask_invert = true,
484 .init_ack_masked = true,
485 .irqs = axp288_regmap_irqs,
486 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
487 .num_regs = 6,
488
Carlo Caionecfb61a42014-05-01 14:29:27 +0200489};
490
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800491static const struct regmap_irq_chip axp809_regmap_irq_chip = {
492 .name = "axp809",
493 .status_base = AXP20X_IRQ1_STATE,
494 .ack_base = AXP20X_IRQ1_STATE,
495 .mask_base = AXP20X_IRQ1_EN,
496 .mask_invert = true,
497 .init_ack_masked = true,
498 .irqs = axp809_regmap_irqs,
499 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
500 .num_regs = 5,
501};
502
Carlo Caionecfb61a42014-05-01 14:29:27 +0200503static struct mfd_cell axp20x_cells[] = {
504 {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200505 .name = "axp20x-pek",
506 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
507 .resources = axp20x_pek_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200508 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200509 .name = "axp20x-regulator",
510 }, {
Michael Haascd7cf272016-05-06 07:19:49 +0200511 .name = "axp20x-ac-power-supply",
512 .of_compatible = "x-powers,axp202-ac-power-supply",
513 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
514 .resources = axp20x_ac_power_supply_resources,
515 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200516 .name = "axp20x-usb-power-supply",
517 .of_compatible = "x-powers,axp202-usb-power-supply",
518 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
519 .resources = axp20x_usb_power_supply_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200520 },
521};
522
Boris BREZILLONf05be582015-04-10 12:09:01 +0800523static struct mfd_cell axp22x_cells[] = {
524 {
525 .name = "axp20x-pek",
526 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
527 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800528 }, {
529 .name = "axp20x-regulator",
Boris BREZILLONf05be582015-04-10 12:09:01 +0800530 },
531};
532
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200533static struct mfd_cell axp152_cells[] = {
534 {
535 .name = "axp20x-pek",
536 .num_resources = ARRAY_SIZE(axp152_pek_resources),
537 .resources = axp152_pek_resources,
538 },
539};
540
Jacob Panaf7e9062014-10-06 21:17:14 -0700541static struct resource axp288_adc_resources[] = {
542 {
543 .name = "GPADC",
544 .start = AXP288_IRQ_GPADC,
545 .end = AXP288_IRQ_GPADC,
546 .flags = IORESOURCE_IRQ,
547 },
548};
549
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530550static struct resource axp288_extcon_resources[] = {
551 {
552 .start = AXP288_IRQ_VBUS_FALL,
553 .end = AXP288_IRQ_VBUS_FALL,
554 .flags = IORESOURCE_IRQ,
555 },
556 {
557 .start = AXP288_IRQ_VBUS_RISE,
558 .end = AXP288_IRQ_VBUS_RISE,
559 .flags = IORESOURCE_IRQ,
560 },
561 {
562 .start = AXP288_IRQ_MV_CHNG,
563 .end = AXP288_IRQ_MV_CHNG,
564 .flags = IORESOURCE_IRQ,
565 },
566 {
567 .start = AXP288_IRQ_BC_USB_CHNG,
568 .end = AXP288_IRQ_BC_USB_CHNG,
569 .flags = IORESOURCE_IRQ,
570 },
571};
572
Jacob Panaf7e9062014-10-06 21:17:14 -0700573static struct resource axp288_charger_resources[] = {
574 {
575 .start = AXP288_IRQ_OV,
576 .end = AXP288_IRQ_OV,
577 .flags = IORESOURCE_IRQ,
578 },
579 {
580 .start = AXP288_IRQ_DONE,
581 .end = AXP288_IRQ_DONE,
582 .flags = IORESOURCE_IRQ,
583 },
584 {
585 .start = AXP288_IRQ_CHARGING,
586 .end = AXP288_IRQ_CHARGING,
587 .flags = IORESOURCE_IRQ,
588 },
589 {
590 .start = AXP288_IRQ_SAFE_QUIT,
591 .end = AXP288_IRQ_SAFE_QUIT,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = AXP288_IRQ_SAFE_ENTER,
596 .end = AXP288_IRQ_SAFE_ENTER,
597 .flags = IORESOURCE_IRQ,
598 },
599 {
600 .start = AXP288_IRQ_QCBTU,
601 .end = AXP288_IRQ_QCBTU,
602 .flags = IORESOURCE_IRQ,
603 },
604 {
605 .start = AXP288_IRQ_CBTU,
606 .end = AXP288_IRQ_CBTU,
607 .flags = IORESOURCE_IRQ,
608 },
609 {
610 .start = AXP288_IRQ_QCBTO,
611 .end = AXP288_IRQ_QCBTO,
612 .flags = IORESOURCE_IRQ,
613 },
614 {
615 .start = AXP288_IRQ_CBTO,
616 .end = AXP288_IRQ_CBTO,
617 .flags = IORESOURCE_IRQ,
618 },
619};
620
621static struct mfd_cell axp288_cells[] = {
622 {
623 .name = "axp288_adc",
624 .num_resources = ARRAY_SIZE(axp288_adc_resources),
625 .resources = axp288_adc_resources,
626 },
627 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530628 .name = "axp288_extcon",
629 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
630 .resources = axp288_extcon_resources,
631 },
632 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700633 .name = "axp288_charger",
634 .num_resources = ARRAY_SIZE(axp288_charger_resources),
635 .resources = axp288_charger_resources,
636 },
637 {
Todd Brandtd63878742015-02-02 15:41:41 -0800638 .name = "axp288_fuel_gauge",
639 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
640 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700641 },
Aaron Lud8139f62014-11-24 17:24:47 +0800642 {
Borun Fue56e5ad2015-10-14 16:16:26 +0800643 .name = "axp20x-pek",
644 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
645 .resources = axp288_power_button_resources,
646 },
647 {
Aaron Lud8139f62014-11-24 17:24:47 +0800648 .name = "axp288_pmic_acpi",
649 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700650};
651
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800652static struct mfd_cell axp809_cells[] = {
653 {
654 .name = "axp20x-pek",
655 .num_resources = ARRAY_SIZE(axp809_pek_resources),
656 .resources = axp809_pek_resources,
657 }, {
658 .name = "axp20x-regulator",
659 },
660};
661
Carlo Caionecfb61a42014-05-01 14:29:27 +0200662static struct axp20x_dev *axp20x_pm_power_off;
663static void axp20x_power_off(void)
664{
Jacob Panaf7e9062014-10-06 21:17:14 -0700665 if (axp20x_pm_power_off->variant == AXP288_ID)
666 return;
667
Carlo Caionecfb61a42014-05-01 14:29:27 +0200668 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
669 AXP20X_OFF);
670}
671
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800672int axp20x_match_device(struct axp20x_dev *axp20x)
Jacob Panaf7e9062014-10-06 21:17:14 -0700673{
Chen-Yu Tsaie47a3cf2016-02-12 10:02:39 +0800674 struct device *dev = axp20x->dev;
Jacob Panaf7e9062014-10-06 21:17:14 -0700675 const struct acpi_device_id *acpi_id;
676 const struct of_device_id *of_id;
677
678 if (dev->of_node) {
Chen-Yu Tsaiaf7acc32016-02-12 10:02:40 +0800679 of_id = of_match_device(dev->driver->of_match_table, dev);
Jacob Panaf7e9062014-10-06 21:17:14 -0700680 if (!of_id) {
681 dev_err(dev, "Unable to match OF ID\n");
682 return -ENODEV;
683 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800684 axp20x->variant = (long)of_id->data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700685 } else {
686 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
687 if (!acpi_id || !acpi_id->driver_data) {
688 dev_err(dev, "Unable to match ACPI ID and data\n");
689 return -ENODEV;
690 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800691 axp20x->variant = (long)acpi_id->driver_data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700692 }
693
694 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200695 case AXP152_ID:
696 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
697 axp20x->cells = axp152_cells;
698 axp20x->regmap_cfg = &axp152_regmap_config;
699 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
700 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700701 case AXP202_ID:
702 case AXP209_ID:
703 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
704 axp20x->cells = axp20x_cells;
705 axp20x->regmap_cfg = &axp20x_regmap_config;
706 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
707 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800708 case AXP221_ID:
Chen-Yu Tsai02071f02016-02-12 10:02:44 +0800709 case AXP223_ID:
Boris BREZILLONf05be582015-04-10 12:09:01 +0800710 axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
711 axp20x->cells = axp22x_cells;
712 axp20x->regmap_cfg = &axp22x_regmap_config;
713 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
714 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700715 case AXP288_ID:
716 axp20x->cells = axp288_cells;
717 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
718 axp20x->regmap_cfg = &axp288_regmap_config;
719 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
720 break;
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800721 case AXP809_ID:
722 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
723 axp20x->cells = axp809_cells;
724 axp20x->regmap_cfg = &axp22x_regmap_config;
725 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
726 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700727 default:
728 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
729 return -EINVAL;
730 }
731 dev_info(dev, "AXP20x variant %s found\n",
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800732 axp20x_model_names[axp20x->variant]);
Jacob Panaf7e9062014-10-06 21:17:14 -0700733
734 return 0;
735}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800736EXPORT_SYMBOL(axp20x_match_device);
Jacob Panaf7e9062014-10-06 21:17:14 -0700737
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800738int axp20x_device_probe(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200739{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200740 int ret;
741
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800742 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200743 IRQF_ONESHOT | IRQF_SHARED, -1,
Jacob Panaf7e9062014-10-06 21:17:14 -0700744 axp20x->regmap_irq_chip,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200745 &axp20x->regmap_irqc);
746 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800747 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200748 return ret;
749 }
750
Jacob Panaf7e9062014-10-06 21:17:14 -0700751 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800752 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200753
754 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800755 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
756 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200757 return ret;
758 }
759
760 if (!pm_power_off) {
761 axp20x_pm_power_off = axp20x;
762 pm_power_off = axp20x_power_off;
763 }
764
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800765 dev_info(axp20x->dev, "AXP20X driver loaded\n");
Carlo Caionecfb61a42014-05-01 14:29:27 +0200766
767 return 0;
768}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800769EXPORT_SYMBOL(axp20x_device_probe);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200770
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800771int axp20x_device_remove(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200772{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200773 if (axp20x == axp20x_pm_power_off) {
774 axp20x_pm_power_off = NULL;
775 pm_power_off = NULL;
776 }
777
778 mfd_remove_devices(axp20x->dev);
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800779 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200780
781 return 0;
782}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800783EXPORT_SYMBOL(axp20x_device_remove);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200784
785MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
786MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
787MODULE_LICENSE("GPL");