Yi Kong | b551264 | 2019-04-18 17:31:16 -0700 | [diff] [blame^] | 1 | //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | /// \file This file declares the API for the register bank info. |
| 10 | /// This API is responsible for handling the register banks. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H |
| 15 | #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H |
| 16 | |
| 17 | #include "llvm/ADT/DenseMap.h" |
| 18 | #include "llvm/ADT/Hashing.h" |
| 19 | #include "llvm/ADT/SmallVector.h" |
| 20 | #include "llvm/ADT/iterator_range.h" |
| 21 | #include "llvm/Support/ErrorHandling.h" |
| 22 | #include <cassert> |
| 23 | #include <initializer_list> |
| 24 | #include <memory> |
| 25 | |
| 26 | namespace llvm { |
| 27 | |
| 28 | class MachineInstr; |
| 29 | class MachineRegisterInfo; |
| 30 | class raw_ostream; |
| 31 | class RegisterBank; |
| 32 | class TargetInstrInfo; |
| 33 | class TargetRegisterClass; |
| 34 | class TargetRegisterInfo; |
| 35 | |
| 36 | /// Holds all the information related to register banks. |
| 37 | class RegisterBankInfo { |
| 38 | public: |
| 39 | /// Helper struct that represents how a value is partially mapped |
| 40 | /// into a register. |
| 41 | /// The StartIdx and Length represent what region of the orginal |
| 42 | /// value this partial mapping covers. |
| 43 | /// This can be represented as a Mask of contiguous bit starting |
| 44 | /// at StartIdx bit and spanning Length bits. |
| 45 | /// StartIdx is the number of bits from the less significant bits. |
| 46 | struct PartialMapping { |
| 47 | /// Number of bits at which this partial mapping starts in the |
| 48 | /// original value. The bits are counted from less significant |
| 49 | /// bits to most significant bits. |
| 50 | unsigned StartIdx; |
| 51 | |
| 52 | /// Length of this mapping in bits. This is how many bits this |
| 53 | /// partial mapping covers in the original value: |
| 54 | /// from StartIdx to StartIdx + Length -1. |
| 55 | unsigned Length; |
| 56 | |
| 57 | /// Register bank where the partial value lives. |
| 58 | const RegisterBank *RegBank; |
| 59 | |
| 60 | PartialMapping() = default; |
| 61 | |
| 62 | /// Provide a shortcut for quickly building PartialMapping. |
| 63 | PartialMapping(unsigned StartIdx, unsigned Length, |
| 64 | const RegisterBank &RegBank) |
| 65 | : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} |
| 66 | |
| 67 | /// \return the index of in the original value of the most |
| 68 | /// significant bit that this partial mapping covers. |
| 69 | unsigned getHighBitIdx() const { return StartIdx + Length - 1; } |
| 70 | |
| 71 | /// Print this partial mapping on dbgs() stream. |
| 72 | void dump() const; |
| 73 | |
| 74 | /// Print this partial mapping on \p OS; |
| 75 | void print(raw_ostream &OS) const; |
| 76 | |
| 77 | /// Check that the Mask is compatible with the RegBank. |
| 78 | /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask, |
| 79 | /// there is no way this mapping is valid. |
| 80 | /// |
| 81 | /// \note This method does not check anything when assertions are disabled. |
| 82 | /// |
| 83 | /// \return True is the check was successful. |
| 84 | bool verify() const; |
| 85 | }; |
| 86 | |
| 87 | /// Helper struct that represents how a value is mapped through |
| 88 | /// different register banks. |
| 89 | /// |
| 90 | /// \note: So far we do not have any users of the complex mappings |
| 91 | /// (mappings with more than one partial mapping), but when we do, |
| 92 | /// we would have needed to duplicate partial mappings. |
| 93 | /// The alternative could be to use an array of pointers of partial |
| 94 | /// mapping (i.e., PartialMapping **BreakDown) and duplicate the |
| 95 | /// pointers instead. |
| 96 | /// |
| 97 | /// E.g., |
| 98 | /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We |
| 99 | /// can expand the |
| 100 | /// <2 x 32-bit> add into 2 x 32-bit add. |
| 101 | /// |
| 102 | /// Currently the TableGen-like file would look like: |
| 103 | /// \code |
| 104 | /// PartialMapping[] = { |
| 105 | /// /*32-bit add*/ {0, 32, GPR}, // Scalar entry repeated for first vec elt. |
| 106 | /// /*2x32-bit add*/ {0, 32, GPR}, {32, 32, GPR}, |
| 107 | /// /*<2x32-bit> vadd {0, 64, VPR} |
| 108 | /// }; // PartialMapping duplicated. |
| 109 | /// |
| 110 | /// ValueMapping[] { |
| 111 | /// /*plain 32-bit add*/ {&PartialMapping[0], 1}, |
| 112 | /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2}, |
| 113 | /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1} |
| 114 | /// }; |
| 115 | /// \endcode |
| 116 | /// |
| 117 | /// With the array of pointer, we would have: |
| 118 | /// \code |
| 119 | /// PartialMapping[] = { |
| 120 | /// /*32-bit add lower */ {0, 32, GPR}, |
| 121 | /// /*32-bit add upper */ {32, 32, GPR}, |
| 122 | /// /*<2x32-bit> vadd {0, 64, VPR} |
| 123 | /// }; // No more duplication. |
| 124 | /// |
| 125 | /// BreakDowns[] = { |
| 126 | /// /*AddBreakDown*/ &PartialMapping[0], |
| 127 | /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1], |
| 128 | /// /*VAddBreakDown*/ &PartialMapping[2] |
| 129 | /// }; // Addresses of PartialMapping duplicated (smaller). |
| 130 | /// |
| 131 | /// ValueMapping[] { |
| 132 | /// /*plain 32-bit add*/ {&BreakDowns[0], 1}, |
| 133 | /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2}, |
| 134 | /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1} |
| 135 | /// }; |
| 136 | /// \endcode |
| 137 | /// |
| 138 | /// Given that a PartialMapping is actually small, the code size |
| 139 | /// impact is actually a degradation. Moreover the compile time will |
| 140 | /// be hit by the additional indirection. |
| 141 | /// If PartialMapping gets bigger we may reconsider. |
| 142 | struct ValueMapping { |
| 143 | /// How the value is broken down between the different register banks. |
| 144 | const PartialMapping *BreakDown; |
| 145 | |
| 146 | /// Number of partial mapping to break down this value. |
| 147 | unsigned NumBreakDowns; |
| 148 | |
| 149 | /// The default constructor creates an invalid (isValid() == false) |
| 150 | /// instance. |
| 151 | ValueMapping() : ValueMapping(nullptr, 0) {} |
| 152 | |
| 153 | /// Initialize a ValueMapping with the given parameter. |
| 154 | /// \p BreakDown needs to have a life time at least as long |
| 155 | /// as this instance. |
| 156 | ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) |
| 157 | : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {} |
| 158 | |
| 159 | /// Iterators through the PartialMappings. |
| 160 | const PartialMapping *begin() const { return BreakDown; } |
| 161 | const PartialMapping *end() const { return BreakDown + NumBreakDowns; } |
| 162 | |
| 163 | /// \return true if all partial mappings are the same size and register |
| 164 | /// bank. |
| 165 | bool partsAllUniform() const; |
| 166 | |
| 167 | /// Check if this ValueMapping is valid. |
| 168 | bool isValid() const { return BreakDown && NumBreakDowns; } |
| 169 | |
| 170 | /// Verify that this mapping makes sense for a value of |
| 171 | /// \p MeaningfulBitWidth. |
| 172 | /// \note This method does not check anything when assertions are disabled. |
| 173 | /// |
| 174 | /// \return True is the check was successful. |
| 175 | bool verify(unsigned MeaningfulBitWidth) const; |
| 176 | |
| 177 | /// Print this on dbgs() stream. |
| 178 | void dump() const; |
| 179 | |
| 180 | /// Print this on \p OS; |
| 181 | void print(raw_ostream &OS) const; |
| 182 | }; |
| 183 | |
| 184 | /// Helper class that represents how the value of an instruction may be |
| 185 | /// mapped and what is the related cost of such mapping. |
| 186 | class InstructionMapping { |
| 187 | /// Identifier of the mapping. |
| 188 | /// This is used to communicate between the target and the optimizers |
| 189 | /// which mapping should be realized. |
| 190 | unsigned ID = InvalidMappingID; |
| 191 | |
| 192 | /// Cost of this mapping. |
| 193 | unsigned Cost = 0; |
| 194 | |
| 195 | /// Mapping of all the operands. |
| 196 | const ValueMapping *OperandsMapping; |
| 197 | |
| 198 | /// Number of operands. |
| 199 | unsigned NumOperands = 0; |
| 200 | |
| 201 | const ValueMapping &getOperandMapping(unsigned i) { |
| 202 | assert(i < getNumOperands() && "Out of bound operand"); |
| 203 | return OperandsMapping[i]; |
| 204 | } |
| 205 | |
| 206 | public: |
| 207 | /// Constructor for the mapping of an instruction. |
| 208 | /// \p NumOperands must be equal to number of all the operands of |
| 209 | /// the related instruction. |
| 210 | /// The rationale is that it is more efficient for the optimizers |
| 211 | /// to be able to assume that the mapping of the ith operand is |
| 212 | /// at the index i. |
| 213 | /// |
| 214 | /// \pre ID != InvalidMappingID |
| 215 | InstructionMapping(unsigned ID, unsigned Cost, |
| 216 | const ValueMapping *OperandsMapping, |
| 217 | unsigned NumOperands) |
| 218 | : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping), |
| 219 | NumOperands(NumOperands) { |
| 220 | assert(getID() != InvalidMappingID && |
| 221 | "Use the default constructor for invalid mapping"); |
| 222 | } |
| 223 | |
| 224 | /// Default constructor. |
| 225 | /// Use this constructor to express that the mapping is invalid. |
| 226 | InstructionMapping() = default; |
| 227 | |
| 228 | /// Get the cost. |
| 229 | unsigned getCost() const { return Cost; } |
| 230 | |
| 231 | /// Get the ID. |
| 232 | unsigned getID() const { return ID; } |
| 233 | |
| 234 | /// Get the number of operands. |
| 235 | unsigned getNumOperands() const { return NumOperands; } |
| 236 | |
| 237 | /// Get the value mapping of the ith operand. |
| 238 | /// \pre The mapping for the ith operand has been set. |
| 239 | /// \pre The ith operand is a register. |
| 240 | const ValueMapping &getOperandMapping(unsigned i) const { |
| 241 | const ValueMapping &ValMapping = |
| 242 | const_cast<InstructionMapping *>(this)->getOperandMapping(i); |
| 243 | return ValMapping; |
| 244 | } |
| 245 | |
| 246 | /// Set the mapping for all the operands. |
| 247 | /// In other words, OpdsMapping should hold at least getNumOperands |
| 248 | /// ValueMapping. |
| 249 | void setOperandsMapping(const ValueMapping *OpdsMapping) { |
| 250 | OperandsMapping = OpdsMapping; |
| 251 | } |
| 252 | |
| 253 | /// Check whether this object is valid. |
| 254 | /// This is a lightweight check for obvious wrong instance. |
| 255 | bool isValid() const { |
| 256 | return getID() != InvalidMappingID && OperandsMapping; |
| 257 | } |
| 258 | |
| 259 | /// Verifiy that this mapping makes sense for \p MI. |
| 260 | /// \pre \p MI must be connected to a MachineFunction. |
| 261 | /// |
| 262 | /// \note This method does not check anything when assertions are disabled. |
| 263 | /// |
| 264 | /// \return True is the check was successful. |
| 265 | bool verify(const MachineInstr &MI) const; |
| 266 | |
| 267 | /// Print this on dbgs() stream. |
| 268 | void dump() const; |
| 269 | |
| 270 | /// Print this on \p OS; |
| 271 | void print(raw_ostream &OS) const; |
| 272 | }; |
| 273 | |
| 274 | /// Convenient type to represent the alternatives for mapping an |
| 275 | /// instruction. |
| 276 | /// \todo When we move to TableGen this should be an array ref. |
| 277 | using InstructionMappings = SmallVector<const InstructionMapping *, 4>; |
| 278 | |
| 279 | /// Helper class used to get/create the virtual registers that will be used |
| 280 | /// to replace the MachineOperand when applying a mapping. |
| 281 | class OperandsMapper { |
| 282 | /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the |
| 283 | /// OpIdx-th operand starts. -1 means we do not have such mapping yet. |
| 284 | /// Note: We use a SmallVector to avoid heap allocation for most cases. |
| 285 | SmallVector<int, 8> OpToNewVRegIdx; |
| 286 | |
| 287 | /// Hold the registers that will be used to map MI with InstrMapping. |
| 288 | SmallVector<unsigned, 8> NewVRegs; |
| 289 | |
| 290 | /// Current MachineRegisterInfo, used to create new virtual registers. |
| 291 | MachineRegisterInfo &MRI; |
| 292 | |
| 293 | /// Instruction being remapped. |
| 294 | MachineInstr &MI; |
| 295 | |
| 296 | /// New mapping of the instruction. |
| 297 | const InstructionMapping &InstrMapping; |
| 298 | |
| 299 | /// Constant value identifying that the index in OpToNewVRegIdx |
| 300 | /// for an operand has not been set yet. |
| 301 | static const int DontKnowIdx; |
| 302 | |
| 303 | /// Get the range in NewVRegs to store all the partial |
| 304 | /// values for the \p OpIdx-th operand. |
| 305 | /// |
| 306 | /// \return The iterator range for the space created. |
| 307 | // |
| 308 | /// \pre getMI().getOperand(OpIdx).isReg() |
| 309 | iterator_range<SmallVectorImpl<unsigned>::iterator> |
| 310 | getVRegsMem(unsigned OpIdx); |
| 311 | |
| 312 | /// Get the end iterator for a range starting at \p StartIdx and |
| 313 | /// spannig \p NumVal in NewVRegs. |
| 314 | /// \pre StartIdx + NumVal <= NewVRegs.size() |
| 315 | SmallVectorImpl<unsigned>::const_iterator |
| 316 | getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const; |
| 317 | SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx, |
| 318 | unsigned NumVal); |
| 319 | |
| 320 | public: |
| 321 | /// Create an OperandsMapper that will hold the information to apply \p |
| 322 | /// InstrMapping to \p MI. |
| 323 | /// \pre InstrMapping.verify(MI) |
| 324 | OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, |
| 325 | MachineRegisterInfo &MRI); |
| 326 | |
| 327 | /// \name Getters. |
| 328 | /// @{ |
| 329 | /// The MachineInstr being remapped. |
| 330 | MachineInstr &getMI() const { return MI; } |
| 331 | |
| 332 | /// The final mapping of the instruction. |
| 333 | const InstructionMapping &getInstrMapping() const { return InstrMapping; } |
| 334 | |
| 335 | /// The MachineRegisterInfo we used to realize the mapping. |
| 336 | MachineRegisterInfo &getMRI() const { return MRI; } |
| 337 | /// @} |
| 338 | |
| 339 | /// Create as many new virtual registers as needed for the mapping of the \p |
| 340 | /// OpIdx-th operand. |
| 341 | /// The number of registers is determined by the number of breakdown for the |
| 342 | /// related operand in the instruction mapping. |
| 343 | /// The type of the new registers is a plain scalar of the right size. |
| 344 | /// The proper type is expected to be set when the mapping is applied to |
| 345 | /// the instruction(s) that realizes the mapping. |
| 346 | /// |
| 347 | /// \pre getMI().getOperand(OpIdx).isReg() |
| 348 | /// |
| 349 | /// \post All the partial mapping of the \p OpIdx-th operand have been |
| 350 | /// assigned a new virtual register. |
| 351 | void createVRegs(unsigned OpIdx); |
| 352 | |
| 353 | /// Set the virtual register of the \p PartialMapIdx-th partial mapping of |
| 354 | /// the OpIdx-th operand to \p NewVReg. |
| 355 | /// |
| 356 | /// \pre getMI().getOperand(OpIdx).isReg() |
| 357 | /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() > |
| 358 | /// PartialMapIdx |
| 359 | /// \pre NewReg != 0 |
| 360 | /// |
| 361 | /// \post the \p PartialMapIdx-th register of the value mapping of the \p |
| 362 | /// OpIdx-th operand has been set. |
| 363 | void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg); |
| 364 | |
| 365 | /// Get all the virtual registers required to map the \p OpIdx-th operand of |
| 366 | /// the instruction. |
| 367 | /// |
| 368 | /// This return an empty range when createVRegs or setVRegs has not been |
| 369 | /// called. |
| 370 | /// The iterator may be invalidated by a call to setVRegs or createVRegs. |
| 371 | /// |
| 372 | /// When \p ForDebug is true, we will not check that the list of new virtual |
| 373 | /// registers does not contain uninitialized values. |
| 374 | /// |
| 375 | /// \pre getMI().getOperand(OpIdx).isReg() |
| 376 | /// \pre ForDebug || All partial mappings have been set a register |
| 377 | iterator_range<SmallVectorImpl<unsigned>::const_iterator> |
| 378 | getVRegs(unsigned OpIdx, bool ForDebug = false) const; |
| 379 | |
| 380 | /// Print this operands mapper on dbgs() stream. |
| 381 | void dump() const; |
| 382 | |
| 383 | /// Print this operands mapper on \p OS stream. |
| 384 | void print(raw_ostream &OS, bool ForDebug = false) const; |
| 385 | }; |
| 386 | |
| 387 | protected: |
| 388 | /// Hold the set of supported register banks. |
| 389 | RegisterBank **RegBanks; |
| 390 | |
| 391 | /// Total number of register banks. |
| 392 | unsigned NumRegBanks; |
| 393 | |
| 394 | /// Keep dynamically allocated PartialMapping in a separate map. |
| 395 | /// This shouldn't be needed when everything gets TableGen'ed. |
| 396 | mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>> |
| 397 | MapOfPartialMappings; |
| 398 | |
| 399 | /// Keep dynamically allocated ValueMapping in a separate map. |
| 400 | /// This shouldn't be needed when everything gets TableGen'ed. |
| 401 | mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>> |
| 402 | MapOfValueMappings; |
| 403 | |
| 404 | /// Keep dynamically allocated array of ValueMapping in a separate map. |
| 405 | /// This shouldn't be needed when everything gets TableGen'ed. |
| 406 | mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>> |
| 407 | MapOfOperandsMappings; |
| 408 | |
| 409 | /// Keep dynamically allocated InstructionMapping in a separate map. |
| 410 | /// This shouldn't be needed when everything gets TableGen'ed. |
| 411 | mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>> |
| 412 | MapOfInstructionMappings; |
| 413 | |
| 414 | /// Getting the minimal register class of a physreg is expensive. |
| 415 | /// Cache this information as we get it. |
| 416 | mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs; |
| 417 | |
| 418 | /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks |
| 419 | /// RegisterBank instances. |
| 420 | RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); |
| 421 | |
| 422 | /// This constructor is meaningless. |
| 423 | /// It just provides a default constructor that can be used at link time |
| 424 | /// when GlobalISel is not built. |
| 425 | /// That way, targets can still inherit from this class without doing |
| 426 | /// crazy gymnastic to avoid link time failures. |
| 427 | /// \note That works because the constructor is inlined. |
| 428 | RegisterBankInfo() { |
| 429 | llvm_unreachable("This constructor should not be executed"); |
| 430 | } |
| 431 | |
| 432 | /// Get the register bank identified by \p ID. |
| 433 | RegisterBank &getRegBank(unsigned ID) { |
| 434 | assert(ID < getNumRegBanks() && "Accessing an unknown register bank"); |
| 435 | return *RegBanks[ID]; |
| 436 | } |
| 437 | |
| 438 | /// Get the MinimalPhysRegClass for Reg. |
| 439 | /// \pre Reg is a physical register. |
| 440 | const TargetRegisterClass & |
| 441 | getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const; |
| 442 | |
| 443 | /// Try to get the mapping of \p MI. |
| 444 | /// See getInstrMapping for more details on what a mapping represents. |
| 445 | /// |
| 446 | /// Unlike getInstrMapping the returned InstructionMapping may be invalid |
| 447 | /// (isValid() == false). |
| 448 | /// This means that the target independent code is not smart enough |
| 449 | /// to get the mapping of \p MI and thus, the target has to provide the |
| 450 | /// information for \p MI. |
| 451 | /// |
| 452 | /// This implementation is able to get the mapping of: |
| 453 | /// - Target specific instructions by looking at the encoding constraints. |
| 454 | /// - Any instruction if all the register operands have already been assigned |
| 455 | /// a register, a register class, or a register bank. |
| 456 | /// - Copies and phis if at least one of the operands has been assigned a |
| 457 | /// register, a register class, or a register bank. |
| 458 | /// In other words, this method will likely fail to find a mapping for |
| 459 | /// any generic opcode that has not been lowered by target specific code. |
| 460 | const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const; |
| 461 | |
| 462 | /// Get the uniquely generated PartialMapping for the |
| 463 | /// given arguments. |
| 464 | const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length, |
| 465 | const RegisterBank &RegBank) const; |
| 466 | |
| 467 | /// \name Methods to get a uniquely generated ValueMapping. |
| 468 | /// @{ |
| 469 | |
| 470 | /// The most common ValueMapping consists of a single PartialMapping. |
| 471 | /// Feature a method for that. |
| 472 | const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length, |
| 473 | const RegisterBank &RegBank) const; |
| 474 | |
| 475 | /// Get the ValueMapping for the given arguments. |
| 476 | const ValueMapping &getValueMapping(const PartialMapping *BreakDown, |
| 477 | unsigned NumBreakDowns) const; |
| 478 | /// @} |
| 479 | |
| 480 | /// \name Methods to get a uniquely generated array of ValueMapping. |
| 481 | /// @{ |
| 482 | |
| 483 | /// Get the uniquely generated array of ValueMapping for the |
| 484 | /// elements of between \p Begin and \p End. |
| 485 | /// |
| 486 | /// Elements that are nullptr will be replaced by |
| 487 | /// invalid ValueMapping (ValueMapping::isValid == false). |
| 488 | /// |
| 489 | /// \pre The pointers on ValueMapping between \p Begin and \p End |
| 490 | /// must uniquely identify a ValueMapping. Otherwise, there is no |
| 491 | /// guarantee that the return instance will be unique, i.e., another |
| 492 | /// OperandsMapping could have the same content. |
| 493 | template <typename Iterator> |
| 494 | const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const; |
| 495 | |
| 496 | /// Get the uniquely generated array of ValueMapping for the |
| 497 | /// elements of \p OpdsMapping. |
| 498 | /// |
| 499 | /// Elements of \p OpdsMapping that are nullptr will be replaced by |
| 500 | /// invalid ValueMapping (ValueMapping::isValid == false). |
| 501 | const ValueMapping *getOperandsMapping( |
| 502 | const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const; |
| 503 | |
| 504 | /// Get the uniquely generated array of ValueMapping for the |
| 505 | /// given arguments. |
| 506 | /// |
| 507 | /// Arguments that are nullptr will be replaced by invalid |
| 508 | /// ValueMapping (ValueMapping::isValid == false). |
| 509 | const ValueMapping *getOperandsMapping( |
| 510 | std::initializer_list<const ValueMapping *> OpdsMapping) const; |
| 511 | /// @} |
| 512 | |
| 513 | /// \name Methods to get a uniquely generated InstructionMapping. |
| 514 | /// @{ |
| 515 | |
| 516 | private: |
| 517 | /// Method to get a uniquely generated InstructionMapping. |
| 518 | const InstructionMapping & |
| 519 | getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID, |
| 520 | unsigned Cost = 0, |
| 521 | const ValueMapping *OperandsMapping = nullptr, |
| 522 | unsigned NumOperands = 0) const; |
| 523 | |
| 524 | public: |
| 525 | /// Method to get a uniquely generated InstructionMapping. |
| 526 | const InstructionMapping & |
| 527 | getInstructionMapping(unsigned ID, unsigned Cost, |
| 528 | const ValueMapping *OperandsMapping, |
| 529 | unsigned NumOperands) const { |
| 530 | return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost, |
| 531 | OperandsMapping, NumOperands); |
| 532 | } |
| 533 | |
| 534 | /// Method to get a uniquely generated invalid InstructionMapping. |
| 535 | const InstructionMapping &getInvalidInstructionMapping() const { |
| 536 | return getInstructionMappingImpl(/*IsInvalid*/ true); |
| 537 | } |
| 538 | /// @} |
| 539 | |
| 540 | /// Get the register bank for the \p OpIdx-th operand of \p MI form |
| 541 | /// the encoding constraints, if any. |
| 542 | /// |
| 543 | /// \return A register bank that covers the register class of the |
| 544 | /// related encoding constraints or nullptr if \p MI did not provide |
| 545 | /// enough information to deduce it. |
| 546 | const RegisterBank * |
| 547 | getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, |
| 548 | const TargetInstrInfo &TII, |
| 549 | const TargetRegisterInfo &TRI) const; |
| 550 | |
| 551 | /// Helper method to apply something that is like the default mapping. |
| 552 | /// Basically, that means that \p OpdMapper.getMI() is left untouched |
| 553 | /// aside from the reassignment of the register operand that have been |
| 554 | /// remapped. |
| 555 | /// |
| 556 | /// The type of all the new registers that have been created by the |
| 557 | /// mapper are properly remapped to the type of the original registers |
| 558 | /// they replace. In other words, the semantic of the instruction does |
| 559 | /// not change, only the register banks. |
| 560 | /// |
| 561 | /// If the mapping of one of the operand spans several registers, this |
| 562 | /// method will abort as this is not like a default mapping anymore. |
| 563 | /// |
| 564 | /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands()) |
| 565 | /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1. |
| 566 | static void applyDefaultMapping(const OperandsMapper &OpdMapper); |
| 567 | |
| 568 | /// See ::applyMapping. |
| 569 | virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const { |
| 570 | llvm_unreachable("The target has to implement that part"); |
| 571 | } |
| 572 | |
| 573 | public: |
| 574 | virtual ~RegisterBankInfo() = default; |
| 575 | |
| 576 | /// Get the register bank identified by \p ID. |
| 577 | const RegisterBank &getRegBank(unsigned ID) const { |
| 578 | return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); |
| 579 | } |
| 580 | |
| 581 | /// Get the register bank of \p Reg. |
| 582 | /// If Reg has not been assigned a register, a register class, |
| 583 | /// or a register bank, then this returns nullptr. |
| 584 | /// |
| 585 | /// \pre Reg != 0 (NoRegister) |
| 586 | const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, |
| 587 | const TargetRegisterInfo &TRI) const; |
| 588 | |
| 589 | /// Get the total number of register banks. |
| 590 | unsigned getNumRegBanks() const { return NumRegBanks; } |
| 591 | |
| 592 | /// Get a register bank that covers \p RC. |
| 593 | /// |
| 594 | /// \pre \p RC is a user-defined register class (as opposed as one |
| 595 | /// generated by TableGen). |
| 596 | /// |
| 597 | /// \note The mapping RC -> RegBank could be built while adding the |
| 598 | /// coverage for the register banks. However, we do not do it, because, |
| 599 | /// at least for now, we only need this information for register classes |
| 600 | /// that are used in the description of instruction. In other words, |
| 601 | /// there are just a handful of them and we do not want to waste space. |
| 602 | /// |
| 603 | /// \todo This should be TableGen'ed. |
| 604 | virtual const RegisterBank & |
| 605 | getRegBankFromRegClass(const TargetRegisterClass &RC) const { |
| 606 | llvm_unreachable("The target must override this method"); |
| 607 | } |
| 608 | |
| 609 | /// Get the cost of a copy from \p B to \p A, or put differently, |
| 610 | /// get the cost of A = COPY B. Since register banks may cover |
| 611 | /// different size, \p Size specifies what will be the size in bits |
| 612 | /// that will be copied around. |
| 613 | /// |
| 614 | /// \note Since this is a copy, both registers have the same size. |
| 615 | virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, |
| 616 | unsigned Size) const { |
| 617 | // Optimistically assume that copies are coalesced. I.e., when |
| 618 | // they are on the same bank, they are free. |
| 619 | // Otherwise assume a non-zero cost of 1. The targets are supposed |
| 620 | // to override that properly anyway if they care. |
| 621 | return &A != &B; |
| 622 | } |
| 623 | |
| 624 | /// Get the cost of using \p ValMapping to decompose a register. This is |
| 625 | /// similar to ::copyCost, except for cases where multiple copy-like |
| 626 | /// operations need to be inserted. If the register is used as a source |
| 627 | /// operand and already has a bank assigned, \p CurBank is non-null. |
| 628 | virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, |
| 629 | const RegisterBank *CurBank = nullptr) const { |
| 630 | return std::numeric_limits<unsigned>::max(); |
| 631 | } |
| 632 | |
| 633 | /// Constrain the (possibly generic) virtual register \p Reg to \p RC. |
| 634 | /// |
| 635 | /// \pre \p Reg is a virtual register that either has a bank or a class. |
| 636 | /// \returns The constrained register class, or nullptr if there is none. |
| 637 | /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass |
| 638 | /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel |
| 639 | /// purpose, including non-select passes of GlobalISel |
| 640 | static const TargetRegisterClass * |
| 641 | constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, |
| 642 | MachineRegisterInfo &MRI); |
| 643 | |
| 644 | /// Identifier used when the related instruction mapping instance |
| 645 | /// is generated by target independent code. |
| 646 | /// Make sure not to use that identifier to avoid possible collision. |
| 647 | static const unsigned DefaultMappingID; |
| 648 | |
| 649 | /// Identifier used when the related instruction mapping instance |
| 650 | /// is generated by the default constructor. |
| 651 | /// Make sure not to use that identifier. |
| 652 | static const unsigned InvalidMappingID; |
| 653 | |
| 654 | /// Get the mapping of the different operands of \p MI |
| 655 | /// on the register bank. |
| 656 | /// This mapping should be the direct translation of \p MI. |
| 657 | /// In other words, when \p MI is mapped with the returned mapping, |
| 658 | /// only the register banks of the operands of \p MI need to be updated. |
| 659 | /// In particular, neither the opcode nor the type of \p MI needs to be |
| 660 | /// updated for this direct mapping. |
| 661 | /// |
| 662 | /// The target independent implementation gives a mapping based on |
| 663 | /// the register classes for the target specific opcode. |
| 664 | /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. |
| 665 | /// Make sure you do not use that ID for the alternative mapping |
| 666 | /// for MI. See getInstrAlternativeMappings for the alternative |
| 667 | /// mappings. |
| 668 | /// |
| 669 | /// For instance, if \p MI is a vector add, the mapping should |
| 670 | /// not be a scalarization of the add. |
| 671 | /// |
| 672 | /// \post returnedVal.verify(MI). |
| 673 | /// |
| 674 | /// \note If returnedVal does not verify MI, this would probably mean |
| 675 | /// that the target does not support that instruction. |
| 676 | virtual const InstructionMapping & |
| 677 | getInstrMapping(const MachineInstr &MI) const; |
| 678 | |
| 679 | /// Get the alternative mappings for \p MI. |
| 680 | /// Alternative in the sense different from getInstrMapping. |
| 681 | virtual InstructionMappings |
| 682 | getInstrAlternativeMappings(const MachineInstr &MI) const; |
| 683 | |
| 684 | /// Get the possible mapping for \p MI. |
| 685 | /// A mapping defines where the different operands may live and at what cost. |
| 686 | /// For instance, let us consider: |
| 687 | /// v0(16) = G_ADD <2 x i8> v1, v2 |
| 688 | /// The possible mapping could be: |
| 689 | /// |
| 690 | /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)}, |
| 691 | /// /*v2*/{(0xFFFF, VPR)}} |
| 692 | /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)}, |
| 693 | /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)}, |
| 694 | /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}} |
| 695 | /// |
| 696 | /// \note The first alternative of the returned mapping should be the |
| 697 | /// direct translation of \p MI current form. |
| 698 | /// |
| 699 | /// \post !returnedVal.empty(). |
| 700 | InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const; |
| 701 | |
| 702 | /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI(). |
| 703 | /// After this call \p OpdMapper.getMI() may not be valid anymore. |
| 704 | /// \p OpdMapper.getInstrMapping().getID() carries the information of |
| 705 | /// what has been chosen to map \p OpdMapper.getMI(). This ID is set |
| 706 | /// by the various getInstrXXXMapping method. |
| 707 | /// |
| 708 | /// Therefore, getting the mapping and applying it should be kept in |
| 709 | /// sync. |
| 710 | void applyMapping(const OperandsMapper &OpdMapper) const { |
| 711 | // The only mapping we know how to handle is the default mapping. |
| 712 | if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) |
| 713 | return applyDefaultMapping(OpdMapper); |
| 714 | // For other mapping, the target needs to do the right thing. |
| 715 | // If that means calling applyDefaultMapping, fine, but this |
| 716 | // must be explicitly stated. |
| 717 | applyMappingImpl(OpdMapper); |
| 718 | } |
| 719 | |
| 720 | /// Get the size in bits of \p Reg. |
| 721 | /// Utility method to get the size of any registers. Unlike |
| 722 | /// MachineRegisterInfo::getSize, the register does not need to be a |
| 723 | /// virtual register. |
| 724 | /// |
| 725 | /// \pre \p Reg != 0 (NoRegister). |
| 726 | unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, |
| 727 | const TargetRegisterInfo &TRI) const; |
| 728 | |
| 729 | /// Check that information hold by this instance make sense for the |
| 730 | /// given \p TRI. |
| 731 | /// |
| 732 | /// \note This method does not check anything when assertions are disabled. |
| 733 | /// |
| 734 | /// \return True is the check was successful. |
| 735 | bool verify(const TargetRegisterInfo &TRI) const; |
| 736 | }; |
| 737 | |
| 738 | inline raw_ostream & |
| 739 | operator<<(raw_ostream &OS, |
| 740 | const RegisterBankInfo::PartialMapping &PartMapping) { |
| 741 | PartMapping.print(OS); |
| 742 | return OS; |
| 743 | } |
| 744 | |
| 745 | inline raw_ostream & |
| 746 | operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) { |
| 747 | ValMapping.print(OS); |
| 748 | return OS; |
| 749 | } |
| 750 | |
| 751 | inline raw_ostream & |
| 752 | operator<<(raw_ostream &OS, |
| 753 | const RegisterBankInfo::InstructionMapping &InstrMapping) { |
| 754 | InstrMapping.print(OS); |
| 755 | return OS; |
| 756 | } |
| 757 | |
| 758 | inline raw_ostream & |
| 759 | operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) { |
| 760 | OpdMapper.print(OS, /*ForDebug*/ false); |
| 761 | return OS; |
| 762 | } |
| 763 | |
| 764 | /// Hashing function for PartialMapping. |
| 765 | /// It is required for the hashing of ValueMapping. |
| 766 | hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping); |
| 767 | |
| 768 | } // end namespace llvm |
| 769 | |
| 770 | #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H |