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Logan Chien2833ffb2018-10-09 10:03:24 +08001/*===---- cpuid.h - X86 cpu model detection --------------------------------===
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
19 * THE SOFTWARE.
20 *
21 *===-----------------------------------------------------------------------===
22 */
23
24#if !(__x86_64__ || __i386__)
25#error this header is for x86 only
26#endif
27
28/* Responses identification request with %eax 0 */
29/* AMD: "AuthenticAMD" */
30#define signature_AMD_ebx 0x68747541
31#define signature_AMD_edx 0x69746e65
32#define signature_AMD_ecx 0x444d4163
33/* CENTAUR: "CentaurHauls" */
34#define signature_CENTAUR_ebx 0x746e6543
35#define signature_CENTAUR_edx 0x48727561
36#define signature_CENTAUR_ecx 0x736c7561
37/* CYRIX: "CyrixInstead" */
38#define signature_CYRIX_ebx 0x69727943
39#define signature_CYRIX_edx 0x736e4978
40#define signature_CYRIX_ecx 0x64616574
41/* INTEL: "GenuineIntel" */
42#define signature_INTEL_ebx 0x756e6547
43#define signature_INTEL_edx 0x49656e69
44#define signature_INTEL_ecx 0x6c65746e
45/* TM1: "TransmetaCPU" */
46#define signature_TM1_ebx 0x6e617254
47#define signature_TM1_edx 0x74656d73
48#define signature_TM1_ecx 0x55504361
49/* TM2: "GenuineTMx86" */
50#define signature_TM2_ebx 0x756e6547
51#define signature_TM2_edx 0x54656e69
52#define signature_TM2_ecx 0x3638784d
53/* NSC: "Geode by NSC" */
54#define signature_NSC_ebx 0x646f6547
55#define signature_NSC_edx 0x43534e20
56#define signature_NSC_ecx 0x79622065
57/* NEXGEN: "NexGenDriven" */
58#define signature_NEXGEN_ebx 0x4778654e
59#define signature_NEXGEN_edx 0x72446e65
60#define signature_NEXGEN_ecx 0x6e657669
61/* RISE: "RiseRiseRise" */
62#define signature_RISE_ebx 0x65736952
63#define signature_RISE_edx 0x65736952
64#define signature_RISE_ecx 0x65736952
65/* SIS: "SiS SiS SiS " */
66#define signature_SIS_ebx 0x20536953
67#define signature_SIS_edx 0x20536953
68#define signature_SIS_ecx 0x20536953
69/* UMC: "UMC UMC UMC " */
70#define signature_UMC_ebx 0x20434d55
71#define signature_UMC_edx 0x20434d55
72#define signature_UMC_ecx 0x20434d55
73/* VIA: "VIA VIA VIA " */
74#define signature_VIA_ebx 0x20414956
75#define signature_VIA_edx 0x20414956
76#define signature_VIA_ecx 0x20414956
77/* VORTEX: "Vortex86 SoC" */
78#define signature_VORTEX_ebx 0x74726f56
79#define signature_VORTEX_edx 0x36387865
80#define signature_VORTEX_ecx 0x436f5320
81
Logan Chien55afb0a2018-10-15 10:42:14 +080082/* Features in %ecx for leaf 1 */
Logan Chien2833ffb2018-10-09 10:03:24 +080083#define bit_SSE3 0x00000001
84#define bit_PCLMULQDQ 0x00000002
Logan Chien55afb0a2018-10-15 10:42:14 +080085#define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +080086#define bit_DTES64 0x00000004
87#define bit_MONITOR 0x00000008
88#define bit_DSCPL 0x00000010
89#define bit_VMX 0x00000020
90#define bit_SMX 0x00000040
91#define bit_EIST 0x00000080
92#define bit_TM2 0x00000100
93#define bit_SSSE3 0x00000200
94#define bit_CNXTID 0x00000400
95#define bit_FMA 0x00001000
96#define bit_CMPXCHG16B 0x00002000
97#define bit_xTPR 0x00004000
98#define bit_PDCM 0x00008000
99#define bit_PCID 0x00020000
100#define bit_DCA 0x00040000
101#define bit_SSE41 0x00080000
Logan Chien55afb0a2018-10-15 10:42:14 +0800102#define bit_SSE4_1 bit_SSE41 /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +0800103#define bit_SSE42 0x00100000
Logan Chien55afb0a2018-10-15 10:42:14 +0800104#define bit_SSE4_2 bit_SSE42 /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +0800105#define bit_x2APIC 0x00200000
106#define bit_MOVBE 0x00400000
107#define bit_POPCNT 0x00800000
108#define bit_TSCDeadline 0x01000000
109#define bit_AESNI 0x02000000
Logan Chien55afb0a2018-10-15 10:42:14 +0800110#define bit_AES bit_AESNI /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +0800111#define bit_XSAVE 0x04000000
112#define bit_OSXSAVE 0x08000000
113#define bit_AVX 0x10000000
Logan Chien55afb0a2018-10-15 10:42:14 +0800114#define bit_F16C 0x20000000
Logan Chien2833ffb2018-10-09 10:03:24 +0800115#define bit_RDRND 0x40000000
116
Logan Chien55afb0a2018-10-15 10:42:14 +0800117/* Features in %edx for leaf 1 */
Logan Chien2833ffb2018-10-09 10:03:24 +0800118#define bit_FPU 0x00000001
119#define bit_VME 0x00000002
120#define bit_DE 0x00000004
121#define bit_PSE 0x00000008
122#define bit_TSC 0x00000010
123#define bit_MSR 0x00000020
124#define bit_PAE 0x00000040
125#define bit_MCE 0x00000080
126#define bit_CX8 0x00000100
Logan Chien55afb0a2018-10-15 10:42:14 +0800127#define bit_CMPXCHG8B bit_CX8 /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +0800128#define bit_APIC 0x00000200
129#define bit_SEP 0x00000800
130#define bit_MTRR 0x00001000
131#define bit_PGE 0x00002000
132#define bit_MCA 0x00004000
133#define bit_CMOV 0x00008000
134#define bit_PAT 0x00010000
135#define bit_PSE36 0x00020000
136#define bit_PSN 0x00040000
137#define bit_CLFSH 0x00080000
138#define bit_DS 0x00200000
139#define bit_ACPI 0x00400000
140#define bit_MMX 0x00800000
141#define bit_FXSR 0x01000000
Logan Chien55afb0a2018-10-15 10:42:14 +0800142#define bit_FXSAVE bit_FXSR /* for gcc compat */
Logan Chien2833ffb2018-10-09 10:03:24 +0800143#define bit_SSE 0x02000000
144#define bit_SSE2 0x04000000
145#define bit_SS 0x08000000
146#define bit_HTT 0x10000000
147#define bit_TM 0x20000000
148#define bit_PBE 0x80000000
149
Logan Chien55afb0a2018-10-15 10:42:14 +0800150/* Features in %ebx for leaf 7 sub-leaf 0 */
Logan Chien2833ffb2018-10-09 10:03:24 +0800151#define bit_FSGSBASE 0x00000001
Logan Chien55afb0a2018-10-15 10:42:14 +0800152#define bit_SGX 0x00000004
153#define bit_BMI 0x00000008
154#define bit_HLE 0x00000010
155#define bit_AVX2 0x00000020
Logan Chien2833ffb2018-10-09 10:03:24 +0800156#define bit_SMEP 0x00000080
Logan Chien55afb0a2018-10-15 10:42:14 +0800157#define bit_BMI2 0x00000100
Logan Chien2833ffb2018-10-09 10:03:24 +0800158#define bit_ENH_MOVSB 0x00000200
Logan Chien55afb0a2018-10-15 10:42:14 +0800159#define bit_INVPCID 0x00000400
160#define bit_RTM 0x00000800
161#define bit_MPX 0x00004000
162#define bit_AVX512F 0x00010000
163#define bit_AVX512DQ 0x00020000
164#define bit_RDSEED 0x00040000
165#define bit_ADX 0x00080000
166#define bit_AVX512IFMA 0x00200000
167#define bit_CLFLUSHOPT 0x00800000
168#define bit_CLWB 0x01000000
169#define bit_AVX512PF 0x04000000
170#define bit_AVX512ER 0x08000000
171#define bit_AVX512CD 0x10000000
172#define bit_SHA 0x20000000
173#define bit_AVX512BW 0x40000000
174#define bit_AVX512VL 0x80000000
175
176/* Features in %ecx for leaf 7 sub-leaf 0 */
177#define bit_PREFTCHWT1 0x00000001
178#define bit_AVX512VBMI 0x00000002
179#define bit_PKU 0x00000004
180#define bit_OSPKE 0x00000010
181#define bit_WAITPKG 0x00000020
182#define bit_AVX512VBMI2 0x00000040
183#define bit_SHSTK 0x00000080
184#define bit_GFNI 0x00000100
185#define bit_VAES 0x00000200
186#define bit_VPCLMULQDQ 0x00000400
187#define bit_AVX512VNNI 0x00000800
188#define bit_AVX512BITALG 0x00001000
189#define bit_AVX512VPOPCNTDQ 0x00004000
190#define bit_RDPID 0x00400000
191#define bit_CLDEMOTE 0x02000000
192#define bit_MOVDIRI 0x08000000
193#define bit_MOVDIR64B 0x10000000
194
195/* Features in %edx for leaf 7 sub-leaf 0 */
196#define bit_AVX5124VNNIW 0x00000004
197#define bit_AVX5124FMAPS 0x00000008
198#define bit_PCONFIG 0x00040000
199#define bit_IBT 0x00100000
200
201/* Features in %eax for leaf 13 sub-leaf 1 */
202#define bit_XSAVEOPT 0x00000001
203#define bit_XSAVEC 0x00000002
204#define bit_XSAVES 0x00000008
205
206/* Features in %eax for leaf 0x14 sub-leaf 0 */
207#define bit_PTWRITE 0x00000010
208
209/* Features in %ecx for leaf 0x80000001 */
210#define bit_LAHF_LM 0x00000001
211#define bit_ABM 0x00000020
212#define bit_LZCNT bit_ABM /* for gcc compat */
213#define bit_SSE4a 0x00000040
214#define bit_PRFCHW 0x00000100
215#define bit_XOP 0x00000800
216#define bit_LWP 0x00008000
217#define bit_FMA4 0x00010000
218#define bit_TBM 0x00200000
219#define bit_MWAITX 0x20000000
220
221/* Features in %edx for leaf 0x80000001 */
222#define bit_MMXEXT 0x00400000
223#define bit_LM 0x20000000
224#define bit_3DNOWP 0x40000000
225#define bit_3DNOW 0x80000000
226
227/* Features in %ebx for leaf 0x80000008 */
228#define bit_CLZERO 0x00000001
229#define bit_WBNOINVD 0x00000200
230
Logan Chien2833ffb2018-10-09 10:03:24 +0800231
232#if __i386__
Logan Chien55afb0a2018-10-15 10:42:14 +0800233#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \
Logan Chien2833ffb2018-10-09 10:03:24 +0800234 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
Logan Chien55afb0a2018-10-15 10:42:14 +0800235 : "0"(__leaf))
Logan Chien2833ffb2018-10-09 10:03:24 +0800236
Logan Chien55afb0a2018-10-15 10:42:14 +0800237#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \
Logan Chien2833ffb2018-10-09 10:03:24 +0800238 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
Logan Chien55afb0a2018-10-15 10:42:14 +0800239 : "0"(__leaf), "2"(__count))
Logan Chien2833ffb2018-10-09 10:03:24 +0800240#else
241/* x86-64 uses %rbx as the base register, so preserve it. */
Logan Chien55afb0a2018-10-15 10:42:14 +0800242#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \
Logan Chien2833ffb2018-10-09 10:03:24 +0800243 __asm(" xchgq %%rbx,%q1\n" \
244 " cpuid\n" \
245 " xchgq %%rbx,%q1" \
246 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
Logan Chien55afb0a2018-10-15 10:42:14 +0800247 : "0"(__leaf))
Logan Chien2833ffb2018-10-09 10:03:24 +0800248
Logan Chien55afb0a2018-10-15 10:42:14 +0800249#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx) \
Logan Chien2833ffb2018-10-09 10:03:24 +0800250 __asm(" xchgq %%rbx,%q1\n" \
251 " cpuid\n" \
252 " xchgq %%rbx,%q1" \
253 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
Logan Chien55afb0a2018-10-15 10:42:14 +0800254 : "0"(__leaf), "2"(__count))
Logan Chien2833ffb2018-10-09 10:03:24 +0800255#endif
256
Logan Chien55afb0a2018-10-15 10:42:14 +0800257static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig)
Logan Chien2833ffb2018-10-09 10:03:24 +0800258{
259 unsigned int __eax, __ebx, __ecx, __edx;
260#if __i386__
261 int __cpuid_supported;
262
263 __asm(" pushfl\n"
264 " popl %%eax\n"
265 " movl %%eax,%%ecx\n"
266 " xorl $0x00200000,%%eax\n"
267 " pushl %%eax\n"
268 " popfl\n"
269 " pushfl\n"
270 " popl %%eax\n"
271 " movl $0,%0\n"
272 " cmpl %%eax,%%ecx\n"
273 " je 1f\n"
274 " movl $1,%0\n"
275 "1:"
276 : "=r" (__cpuid_supported) : : "eax", "ecx");
277 if (!__cpuid_supported)
278 return 0;
279#endif
280
Logan Chien55afb0a2018-10-15 10:42:14 +0800281 __cpuid(__leaf, __eax, __ebx, __ecx, __edx);
Logan Chien2833ffb2018-10-09 10:03:24 +0800282 if (__sig)
283 *__sig = __ebx;
284 return __eax;
285}
Logan Chien55afb0a2018-10-15 10:42:14 +0800286
287static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax,
288 unsigned int *__ebx, unsigned int *__ecx,
289 unsigned int *__edx)
290{
291 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
292
293 if (__max_leaf == 0 || __max_leaf < __leaf)
294 return 0;
295
296 __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx);
297 return 1;
298}
299
300static __inline int __get_cpuid_count (unsigned int __leaf,
301 unsigned int __subleaf,
302 unsigned int *__eax, unsigned int *__ebx,
303 unsigned int *__ecx, unsigned int *__edx)
304{
305 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
306
307 if (__max_leaf == 0 || __max_leaf < __leaf)
308 return 0;
309
310 __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
311 return 1;
312}