bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * internal execution defines for qemu |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
| 22 | #define DEBUG_DISAS |
| 23 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 24 | #ifndef glue |
| 25 | #define xglue(x, y) x ## y |
| 26 | #define glue(x, y) xglue(x, y) |
| 27 | #define stringify(s) tostring(s) |
| 28 | #define tostring(s) #s |
| 29 | #endif |
| 30 | |
| 31 | #if GCC_MAJOR < 3 |
| 32 | #define __builtin_expect(x, n) (x) |
| 33 | #endif |
| 34 | |
bellard | e2222c3 | 2003-08-10 23:39:03 +0000 | [diff] [blame] | 35 | #ifdef __i386__ |
| 36 | #define REGPARM(n) __attribute((regparm(n))) |
| 37 | #else |
| 38 | #define REGPARM(n) |
| 39 | #endif |
| 40 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 41 | /* is_jmp field values */ |
| 42 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
| 43 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
| 44 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
| 45 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
| 46 | |
| 47 | struct TranslationBlock; |
| 48 | |
| 49 | /* XXX: make safe guess about sizes */ |
| 50 | #define MAX_OP_PER_INSTR 32 |
| 51 | #define OPC_BUF_SIZE 512 |
| 52 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
| 53 | |
| 54 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
| 55 | |
| 56 | extern uint16_t gen_opc_buf[OPC_BUF_SIZE]; |
| 57 | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; |
| 58 | extern uint32_t gen_opc_pc[OPC_BUF_SIZE]; |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 59 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 60 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
| 61 | |
bellard | 9886cc1 | 2004-01-04 23:53:54 +0000 | [diff] [blame] | 62 | typedef void (GenOpFunc)(void); |
| 63 | typedef void (GenOpFunc1)(long); |
| 64 | typedef void (GenOpFunc2)(long, long); |
| 65 | typedef void (GenOpFunc3)(long, long, long); |
| 66 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 67 | #if defined(TARGET_I386) |
| 68 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 69 | void optimize_flags_init(void); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 70 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 71 | #endif |
| 72 | |
| 73 | extern FILE *logfile; |
| 74 | extern int loglevel; |
| 75 | |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 76 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
| 77 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 78 | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 79 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 80 | int max_code_size, int *gen_code_size_ptr); |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 81 | int cpu_restore_state(struct TranslationBlock *tb, |
| 82 | CPUState *env, unsigned long searched_pc); |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 83 | void cpu_exec_init(void); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 84 | int page_unprotect(unsigned long address); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 85 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 86 | void tlb_flush_page(CPUState *env, uint32_t addr); |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 87 | void tlb_flush_page_write(CPUState *env, uint32_t addr); |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame^] | 88 | void tlb_flush(CPUState *env, int flush_global); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 89 | int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, |
| 90 | int is_user, int is_softmmu); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 91 | |
| 92 | #define CODE_GEN_MAX_SIZE 65536 |
| 93 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
| 94 | |
| 95 | #define CODE_GEN_HASH_BITS 15 |
| 96 | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
| 97 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 98 | #define CODE_GEN_PHYS_HASH_BITS 15 |
| 99 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
| 100 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 101 | /* maximum total translate dcode allocated */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 102 | |
| 103 | /* NOTE: the translated code area cannot be too big because on some |
bellard | c4c7e3e | 2004-01-18 21:50:28 +0000 | [diff] [blame] | 104 | archs the range of "fast" function calls is limited. Here is a |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 105 | summary of the ranges: |
| 106 | |
| 107 | i386 : signed 32 bits |
| 108 | arm : signed 26 bits |
| 109 | ppc : signed 24 bits |
| 110 | sparc : signed 32 bits |
| 111 | alpha : signed 23 bits |
| 112 | */ |
| 113 | |
| 114 | #if defined(__alpha__) |
| 115 | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
| 116 | #elif defined(__powerpc__) |
bellard | c4c7e3e | 2004-01-18 21:50:28 +0000 | [diff] [blame] | 117 | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 118 | #else |
| 119 | #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) |
| 120 | #endif |
| 121 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 122 | //#define CODE_GEN_BUFFER_SIZE (128 * 1024) |
| 123 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 124 | /* estimated block size for TB allocation */ |
| 125 | /* XXX: use a per code average code fragment size and modulate it |
| 126 | according to the host CPU */ |
| 127 | #if defined(CONFIG_SOFTMMU) |
| 128 | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
| 129 | #else |
| 130 | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
| 131 | #endif |
| 132 | |
| 133 | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) |
| 134 | |
| 135 | #if defined(__powerpc__) |
| 136 | #define USE_DIRECT_JUMP |
| 137 | #endif |
| 138 | #if defined(__i386__) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 139 | #define USE_DIRECT_JUMP |
| 140 | #endif |
| 141 | |
| 142 | typedef struct TranslationBlock { |
| 143 | unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
| 144 | unsigned long cs_base; /* CS base for this block */ |
| 145 | unsigned int flags; /* flags defining in which context the code was generated */ |
| 146 | uint16_t size; /* size of target code for this block (1 <= |
| 147 | size <= TARGET_PAGE_SIZE) */ |
| 148 | uint8_t *tc_ptr; /* pointer to the translated code */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 149 | struct TranslationBlock *hash_next; /* next matching tb for virtual address */ |
| 150 | /* next matching tb for physical address. */ |
| 151 | struct TranslationBlock *phys_hash_next; |
| 152 | /* first and second physical page containing code. The lower bit |
| 153 | of the pointer tells the index in page_next[] */ |
| 154 | struct TranslationBlock *page_next[2]; |
| 155 | target_ulong page_addr[2]; |
| 156 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 157 | /* the following data are used to directly call another TB from |
| 158 | the code of this one. */ |
| 159 | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
| 160 | #ifdef USE_DIRECT_JUMP |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 161 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 162 | #else |
bellard | 95f7652 | 2003-06-05 00:54:44 +0000 | [diff] [blame] | 163 | uint32_t tb_next[2]; /* address of jump generated code */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 164 | #endif |
| 165 | /* list of TBs jumping to this one. This is a circular list using |
| 166 | the two least significant bits of the pointers to tell what is |
| 167 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = |
| 168 | jmp_first */ |
| 169 | struct TranslationBlock *jmp_next[2]; |
| 170 | struct TranslationBlock *jmp_first; |
| 171 | } TranslationBlock; |
| 172 | |
| 173 | static inline unsigned int tb_hash_func(unsigned long pc) |
| 174 | { |
| 175 | return pc & (CODE_GEN_HASH_SIZE - 1); |
| 176 | } |
| 177 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 178 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
| 179 | { |
| 180 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
| 181 | } |
| 182 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 183 | TranslationBlock *tb_alloc(unsigned long pc); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 184 | void tb_flush(CPUState *env); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 185 | void tb_link(TranslationBlock *tb); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 186 | void tb_link_phys(TranslationBlock *tb, |
| 187 | target_ulong phys_pc, target_ulong phys_page2); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 188 | |
| 189 | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 190 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 191 | |
| 192 | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; |
| 193 | extern uint8_t *code_gen_ptr; |
| 194 | |
| 195 | /* find a translation block in the translation cache. If not found, |
| 196 | return NULL and the pointer to the last element of the list in pptb */ |
| 197 | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
| 198 | unsigned long pc, |
| 199 | unsigned long cs_base, |
| 200 | unsigned int flags) |
| 201 | { |
| 202 | TranslationBlock **ptb, *tb; |
| 203 | unsigned int h; |
| 204 | |
| 205 | h = tb_hash_func(pc); |
| 206 | ptb = &tb_hash[h]; |
| 207 | for(;;) { |
| 208 | tb = *ptb; |
| 209 | if (!tb) |
| 210 | break; |
| 211 | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) |
| 212 | return tb; |
| 213 | ptb = &tb->hash_next; |
| 214 | } |
| 215 | *pptb = ptb; |
| 216 | return NULL; |
| 217 | } |
| 218 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 219 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 220 | #if defined(USE_DIRECT_JUMP) |
| 221 | |
| 222 | #if defined(__powerpc__) |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 223 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 224 | { |
| 225 | uint32_t val, *ptr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 226 | |
| 227 | /* patch the branch destination */ |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 228 | ptr = (uint32_t *)jmp_addr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 229 | val = *ptr; |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 230 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 231 | *ptr = val; |
| 232 | /* flush icache */ |
| 233 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
| 234 | asm volatile ("sync" : : : "memory"); |
| 235 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
| 236 | asm volatile ("sync" : : : "memory"); |
| 237 | asm volatile ("isync" : : : "memory"); |
| 238 | } |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 239 | #elif defined(__i386__) |
| 240 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
| 241 | { |
| 242 | /* patch the branch destination */ |
| 243 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); |
| 244 | /* no need to flush icache explicitely */ |
| 245 | } |
| 246 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 247 | |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 248 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
| 249 | int n, unsigned long addr) |
| 250 | { |
| 251 | unsigned long offset; |
| 252 | |
| 253 | offset = tb->tb_jmp_offset[n]; |
| 254 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
| 255 | offset = tb->tb_jmp_offset[n + 2]; |
| 256 | if (offset != 0xffff) |
| 257 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
| 258 | } |
| 259 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 260 | #else |
| 261 | |
| 262 | /* set the jump target */ |
| 263 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
| 264 | int n, unsigned long addr) |
| 265 | { |
bellard | 95f7652 | 2003-06-05 00:54:44 +0000 | [diff] [blame] | 266 | tb->tb_next[n] = addr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | #endif |
| 270 | |
| 271 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
| 272 | TranslationBlock *tb_next) |
| 273 | { |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 274 | /* NOTE: this test is only needed for thread safety */ |
| 275 | if (!tb->jmp_next[n]) { |
| 276 | /* patch the native jump address */ |
| 277 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
| 278 | |
| 279 | /* add in TB jmp circular list */ |
| 280 | tb->jmp_next[n] = tb_next->jmp_first; |
| 281 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); |
| 282 | } |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 283 | } |
| 284 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 285 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
| 286 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 287 | #ifndef offsetof |
| 288 | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
| 289 | #endif |
| 290 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 291 | #if defined(__powerpc__) |
| 292 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 293 | /* we patch the jump instruction directly */ |
bellard | 9257a9e | 2003-08-11 22:21:18 +0000 | [diff] [blame] | 294 | #define JUMP_TB(opname, tbparam, n, eip)\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 295 | do {\ |
bellard | 9257a9e | 2003-08-11 22:21:18 +0000 | [diff] [blame] | 296 | asm volatile (".section \".data\"\n"\ |
| 297 | "__op_label" #n "." stringify(opname) ":\n"\ |
| 298 | ".long 1f\n"\ |
| 299 | ".previous\n"\ |
| 300 | "b __op_jmp" #n "\n"\ |
| 301 | "1:\n");\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 302 | T0 = (long)(tbparam) + (n);\ |
| 303 | EIP = eip;\ |
bellard | 31e8f3c | 2003-08-10 22:52:34 +0000 | [diff] [blame] | 304 | EXIT_TB();\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 305 | } while (0) |
| 306 | |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 307 | #define JUMP_TB2(opname, tbparam, n)\ |
| 308 | do {\ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 309 | asm volatile ("b __op_jmp" #n "\n");\ |
| 310 | } while (0) |
| 311 | |
| 312 | #elif defined(__i386__) && defined(USE_DIRECT_JUMP) |
| 313 | |
| 314 | /* we patch the jump instruction directly */ |
| 315 | #define JUMP_TB(opname, tbparam, n, eip)\ |
| 316 | do {\ |
| 317 | asm volatile (".section \".data\"\n"\ |
| 318 | "__op_label" #n "." stringify(opname) ":\n"\ |
| 319 | ".long 1f\n"\ |
| 320 | ".previous\n"\ |
| 321 | "jmp __op_jmp" #n "\n"\ |
| 322 | "1:\n");\ |
| 323 | T0 = (long)(tbparam) + (n);\ |
| 324 | EIP = eip;\ |
| 325 | EXIT_TB();\ |
| 326 | } while (0) |
| 327 | |
| 328 | #define JUMP_TB2(opname, tbparam, n)\ |
| 329 | do {\ |
| 330 | asm volatile ("jmp __op_jmp" #n "\n");\ |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 331 | } while (0) |
| 332 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 333 | #else |
| 334 | |
| 335 | /* jump to next block operations (more portable code, does not need |
| 336 | cache flushing, but slower because of indirect jump) */ |
bellard | 9257a9e | 2003-08-11 22:21:18 +0000 | [diff] [blame] | 337 | #define JUMP_TB(opname, tbparam, n, eip)\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 338 | do {\ |
| 339 | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
bellard | 2f62b39 | 2003-06-30 23:18:59 +0000 | [diff] [blame] | 340 | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 341 | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
| 342 | label ## n:\ |
| 343 | T0 = (long)(tbparam) + (n);\ |
| 344 | EIP = eip;\ |
bellard | 2f62b39 | 2003-06-30 23:18:59 +0000 | [diff] [blame] | 345 | dummy_label ## n:\ |
bellard | 9621339 | 2003-07-11 15:17:41 +0000 | [diff] [blame] | 346 | EXIT_TB();\ |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 347 | } while (0) |
| 348 | |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 349 | /* second jump to same destination 'n' */ |
| 350 | #define JUMP_TB2(opname, tbparam, n)\ |
| 351 | do {\ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 352 | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\ |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 353 | } while (0) |
| 354 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 355 | #endif |
| 356 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 357 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 358 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
| 359 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 360 | #ifdef __powerpc__ |
| 361 | static inline int testandset (int *p) |
| 362 | { |
| 363 | int ret; |
| 364 | __asm__ __volatile__ ( |
| 365 | "0: lwarx %0,0,%1 ;" |
| 366 | " xor. %0,%3,%0;" |
| 367 | " bne 1f;" |
| 368 | " stwcx. %2,0,%1;" |
| 369 | " bne- 0b;" |
| 370 | "1: " |
| 371 | : "=&r" (ret) |
| 372 | : "r" (p), "r" (1), "r" (0) |
| 373 | : "cr0", "memory"); |
| 374 | return ret; |
| 375 | } |
| 376 | #endif |
| 377 | |
| 378 | #ifdef __i386__ |
| 379 | static inline int testandset (int *p) |
| 380 | { |
| 381 | char ret; |
| 382 | long int readval; |
| 383 | |
| 384 | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0" |
| 385 | : "=q" (ret), "=m" (*p), "=a" (readval) |
| 386 | : "r" (1), "m" (*p), "a" (0) |
| 387 | : "memory"); |
| 388 | return ret; |
| 389 | } |
| 390 | #endif |
| 391 | |
| 392 | #ifdef __s390__ |
| 393 | static inline int testandset (int *p) |
| 394 | { |
| 395 | int ret; |
| 396 | |
| 397 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" |
| 398 | " jl 0b" |
| 399 | : "=&d" (ret) |
| 400 | : "r" (1), "a" (p), "0" (*p) |
| 401 | : "cc", "memory" ); |
| 402 | return ret; |
| 403 | } |
| 404 | #endif |
| 405 | |
| 406 | #ifdef __alpha__ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 407 | static inline int testandset (int *p) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 408 | { |
| 409 | int ret; |
| 410 | unsigned long one; |
| 411 | |
| 412 | __asm__ __volatile__ ("0: mov 1,%2\n" |
| 413 | " ldl_l %0,%1\n" |
| 414 | " stl_c %2,%1\n" |
| 415 | " beq %2,1f\n" |
| 416 | ".subsection 2\n" |
| 417 | "1: br 0b\n" |
| 418 | ".previous" |
| 419 | : "=r" (ret), "=m" (*p), "=r" (one) |
| 420 | : "m" (*p)); |
| 421 | return ret; |
| 422 | } |
| 423 | #endif |
| 424 | |
| 425 | #ifdef __sparc__ |
| 426 | static inline int testandset (int *p) |
| 427 | { |
| 428 | int ret; |
| 429 | |
| 430 | __asm__ __volatile__("ldstub [%1], %0" |
| 431 | : "=r" (ret) |
| 432 | : "r" (p) |
| 433 | : "memory"); |
| 434 | |
| 435 | return (ret ? 1 : 0); |
| 436 | } |
| 437 | #endif |
| 438 | |
bellard | a95c679 | 2003-06-09 15:29:55 +0000 | [diff] [blame] | 439 | #ifdef __arm__ |
| 440 | static inline int testandset (int *spinlock) |
| 441 | { |
| 442 | register unsigned int ret; |
| 443 | __asm__ __volatile__("swp %0, %1, [%2]" |
| 444 | : "=r"(ret) |
| 445 | : "0"(1), "r"(spinlock)); |
| 446 | |
| 447 | return ret; |
| 448 | } |
| 449 | #endif |
| 450 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 451 | #ifdef __mc68000 |
| 452 | static inline int testandset (int *p) |
| 453 | { |
| 454 | char ret; |
| 455 | __asm__ __volatile__("tas %1; sne %0" |
| 456 | : "=r" (ret) |
| 457 | : "m" (p) |
| 458 | : "cc","memory"); |
| 459 | return ret == 0; |
| 460 | } |
| 461 | #endif |
| 462 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 463 | typedef int spinlock_t; |
| 464 | |
| 465 | #define SPIN_LOCK_UNLOCKED 0 |
| 466 | |
bellard | aebcb60 | 2003-10-30 01:08:17 +0000 | [diff] [blame] | 467 | #if defined(CONFIG_USER_ONLY) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 468 | static inline void spin_lock(spinlock_t *lock) |
| 469 | { |
| 470 | while (testandset(lock)); |
| 471 | } |
| 472 | |
| 473 | static inline void spin_unlock(spinlock_t *lock) |
| 474 | { |
| 475 | *lock = 0; |
| 476 | } |
| 477 | |
| 478 | static inline int spin_trylock(spinlock_t *lock) |
| 479 | { |
| 480 | return !testandset(lock); |
| 481 | } |
bellard | 3c1cf9f | 2003-07-07 11:30:47 +0000 | [diff] [blame] | 482 | #else |
| 483 | static inline void spin_lock(spinlock_t *lock) |
| 484 | { |
| 485 | } |
| 486 | |
| 487 | static inline void spin_unlock(spinlock_t *lock) |
| 488 | { |
| 489 | } |
| 490 | |
| 491 | static inline int spin_trylock(spinlock_t *lock) |
| 492 | { |
| 493 | return 1; |
| 494 | } |
| 495 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 496 | |
| 497 | extern spinlock_t tb_lock; |
| 498 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 499 | extern int tb_invalidated_flag; |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 500 | |
bellard | 9886cc1 | 2004-01-04 23:53:54 +0000 | [diff] [blame] | 501 | #if (defined(TARGET_I386) || defined(TARGET_PPC)) && \ |
| 502 | !defined(CONFIG_USER_ONLY) |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 503 | |
| 504 | void tlb_fill(unsigned long addr, int is_write, int is_user, |
| 505 | void *retaddr); |
| 506 | |
| 507 | #define ACCESS_TYPE 3 |
| 508 | #define MEMSUFFIX _code |
| 509 | #define env cpu_single_env |
| 510 | |
| 511 | #define DATA_SIZE 1 |
| 512 | #include "softmmu_header.h" |
| 513 | |
| 514 | #define DATA_SIZE 2 |
| 515 | #include "softmmu_header.h" |
| 516 | |
| 517 | #define DATA_SIZE 4 |
| 518 | #include "softmmu_header.h" |
| 519 | |
| 520 | #undef ACCESS_TYPE |
| 521 | #undef MEMSUFFIX |
| 522 | #undef env |
| 523 | |
| 524 | #endif |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 525 | |
| 526 | #if defined(CONFIG_USER_ONLY) |
| 527 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 528 | { |
| 529 | return addr; |
| 530 | } |
| 531 | #else |
| 532 | /* NOTE: this function can trigger an exception */ |
| 533 | /* XXX: i386 target specific */ |
| 534 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 535 | { |
| 536 | int is_user, index; |
| 537 | |
| 538 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 539 | #if defined(TARGET_I386) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 540 | is_user = ((env->hflags & HF_CPL_MASK) == 3); |
bellard | 3f5dcc3 | 2004-01-18 22:44:01 +0000 | [diff] [blame] | 541 | #elif defined (TARGET_PPC) |
| 542 | is_user = msr_pr; |
| 543 | #else |
| 544 | #error "Unimplemented !" |
| 545 | #endif |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 546 | if (__builtin_expect(env->tlb_read[is_user][index].address != |
| 547 | (addr & TARGET_PAGE_MASK), 0)) { |
| 548 | ldub_code((void *)addr); |
| 549 | } |
| 550 | return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base; |
| 551 | } |
| 552 | #endif |
| 553 | |