Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Samsung exynos4210 SoC emulation |
| 3 | * |
| 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. |
| 5 | * Maksim Kozlov <m.kozlov@samsung.com> |
| 6 | * Evgeny Voevodin <e.voevodin@samsung.com> |
| 7 | * Igor Mitsyanko <i.mitsyanko@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 17 | * for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | * |
| 22 | */ |
| 23 | |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 24 | #include "hw/boards.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 25 | #include "sysemu/sysemu.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 26 | #include "hw/sysbus.h" |
Peter Maydell | bd2be15 | 2013-04-09 15:26:55 +0100 | [diff] [blame] | 27 | #include "hw/arm/arm.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 28 | #include "hw/loader.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 29 | #include "hw/arm/exynos4210.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 30 | #include "hw/usb/hcd-ehci.h" |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 31 | |
| 32 | #define EXYNOS4210_CHIPID_ADDR 0x10000000 |
| 33 | |
Evgeny Voevodin | 62db8bf | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 34 | /* PWM */ |
| 35 | #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 |
| 36 | |
Oleg Ogurtsov | 7bdf43a | 2012-07-04 10:43:32 +0000 | [diff] [blame] | 37 | /* RTC */ |
| 38 | #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 |
| 39 | |
Evgeny Voevodin | 12c775d | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 40 | /* MCT */ |
| 41 | #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 |
| 42 | |
Mitsyanko Igor | ffbbe7d | 2012-07-18 08:18:34 +0000 | [diff] [blame] | 43 | /* I2C */ |
| 44 | #define EXYNOS4210_I2C_SHIFT 0x00010000 |
| 45 | #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 |
| 46 | /* Interrupt Group of External Interrupt Combiner for I2C */ |
| 47 | #define EXYNOS4210_I2C_INTG 27 |
| 48 | #define EXYNOS4210_HDMI_INTG 16 |
| 49 | |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 50 | /* UART's definitions */ |
| 51 | #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 |
| 52 | #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 |
| 53 | #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 |
| 54 | #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 |
| 55 | #define EXYNOS4210_UART0_FIFO_SIZE 256 |
| 56 | #define EXYNOS4210_UART1_FIFO_SIZE 64 |
| 57 | #define EXYNOS4210_UART2_FIFO_SIZE 16 |
| 58 | #define EXYNOS4210_UART3_FIFO_SIZE 16 |
| 59 | /* Interrupt Group of External Interrupt Combiner for UART */ |
| 60 | #define EXYNOS4210_UART_INT_GRP 26 |
| 61 | |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 62 | /* External GIC */ |
| 63 | #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 |
| 64 | #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 |
| 65 | |
| 66 | /* Combiner */ |
| 67 | #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 |
| 68 | #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 |
| 69 | |
Maksim Kozlov | df91b48 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 70 | /* PMU SFR base address */ |
| 71 | #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 |
| 72 | |
Mitsyanko Igor | 30628cb | 2012-02-16 09:56:06 +0000 | [diff] [blame] | 73 | /* Display controllers (FIMD) */ |
| 74 | #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 |
| 75 | |
Liming Wang | 358d615 | 2012-12-16 04:49:46 +0100 | [diff] [blame] | 76 | /* EHCI */ |
| 77 | #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 |
| 78 | |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 79 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
| 80 | 0x09, 0x00, 0x00, 0x00 }; |
| 81 | |
Igor Mitsyanko | 11a5e48 | 2013-06-03 17:17:46 +0100 | [diff] [blame] | 82 | static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, |
| 83 | unsigned size) |
| 84 | { |
| 85 | assert(offset < sizeof(chipid_and_omr)); |
| 86 | return chipid_and_omr[offset]; |
| 87 | } |
| 88 | |
| 89 | static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, |
| 90 | uint64_t value, unsigned size) |
| 91 | { |
| 92 | return; |
| 93 | } |
| 94 | |
| 95 | static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { |
| 96 | .read = exynos4210_chipid_and_omr_read, |
| 97 | .write = exynos4210_chipid_and_omr_write, |
| 98 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 99 | .impl = { |
| 100 | .max_access_size = 1, |
| 101 | } |
| 102 | }; |
| 103 | |
Andreas Färber | 9543b0c | 2012-05-14 00:08:10 +0200 | [diff] [blame] | 104 | void exynos4210_write_secondary(ARMCPU *cpu, |
Evgeny Voevodin | 3f088e3 | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 105 | const struct arm_boot_info *info) |
| 106 | { |
| 107 | int n; |
| 108 | uint32_t smpboot[] = { |
Peter Maydell | bf471f7 | 2012-12-11 11:30:37 +0000 | [diff] [blame] | 109 | 0xe59f3034, /* ldr r3, External gic_cpu_if */ |
| 110 | 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ |
| 111 | 0xe59f0034, /* ldr r0, startaddr */ |
Evgeny Voevodin | 3f088e3 | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 112 | 0xe3a01001, /* mov r1, #1 */ |
| 113 | 0xe5821000, /* str r1, [r2] */ |
| 114 | 0xe5831000, /* str r1, [r3] */ |
Peter Maydell | bf471f7 | 2012-12-11 11:30:37 +0000 | [diff] [blame] | 115 | 0xe3a010ff, /* mov r1, #0xff */ |
| 116 | 0xe5821004, /* str r1, [r2, #4] */ |
| 117 | 0xe5831004, /* str r1, [r3, #4] */ |
| 118 | 0xf57ff04f, /* dsb */ |
Evgeny Voevodin | 3f088e3 | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 119 | 0xe320f003, /* wfi */ |
| 120 | 0xe5901000, /* ldr r1, [r0] */ |
| 121 | 0xe1110001, /* tst r1, r1 */ |
| 122 | 0x0afffffb, /* beq <wfi> */ |
| 123 | 0xe12fff11, /* bx r1 */ |
| 124 | EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, |
| 125 | 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ |
| 126 | 0 /* bootreg: Boot register address is held here */ |
| 127 | }; |
| 128 | smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; |
| 129 | smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; |
| 130 | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
| 131 | smpboot[n] = tswap32(smpboot[n]); |
| 132 | } |
| 133 | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), |
| 134 | info->smp_loader_start); |
| 135 | } |
| 136 | |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 137 | Exynos4210State *exynos4210_init(MemoryRegion *system_mem, |
| 138 | unsigned long ram_size) |
| 139 | { |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 140 | qemu_irq cpu_irq[EXYNOS4210_NCPUS]; |
| 141 | int i, n; |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 142 | Exynos4210State *s = g_new(Exynos4210State, 1); |
| 143 | qemu_irq *irqp; |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 144 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 145 | unsigned long mem_size; |
| 146 | DeviceState *dev; |
| 147 | SysBusDevice *busdev; |
| 148 | |
| 149 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
Andreas Färber | ef6cbcc | 2012-05-14 04:09:55 +0200 | [diff] [blame] | 150 | s->cpu[n] = cpu_arm_init("cortex-a9"); |
| 151 | if (!s->cpu[n]) { |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 152 | fprintf(stderr, "Unable to find CPU %d definition\n", n); |
| 153 | exit(1); |
| 154 | } |
Andreas Färber | 4bd7466 | 2012-05-14 04:21:52 +0200 | [diff] [blame] | 155 | |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 156 | /* Create PIC controller for each processor instance */ |
Andreas Färber | 4bd7466 | 2012-05-14 04:21:52 +0200 | [diff] [blame] | 157 | irqp = arm_pic_init_cpu(s->cpu[n]); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 158 | |
| 159 | /* |
| 160 | * Get GICs gpio_in cpu_irq to connect a combiner to them later. |
| 161 | * Use only IRQ for a while. |
| 162 | */ |
| 163 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
| 164 | } |
| 165 | |
| 166 | /*** IRQs ***/ |
| 167 | |
| 168 | s->irq_table = exynos4210_init_irq(&s->irqs); |
| 169 | |
| 170 | /* IRQ Gate */ |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 171 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { |
| 172 | dev = qdev_create(NULL, "exynos4210.irq_gate"); |
| 173 | qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); |
| 174 | qdev_init_nofail(dev); |
| 175 | /* Get IRQ Gate input in gate_irq */ |
| 176 | for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { |
| 177 | gate_irq[i][n] = qdev_get_gpio_in(dev, n); |
| 178 | } |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 179 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 180 | |
| 181 | /* Connect IRQ Gate output to cpu_irq */ |
| 182 | sysbus_connect_irq(busdev, 0, cpu_irq[i]); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | /* Private memory region and Internal GIC */ |
| 186 | dev = qdev_create(NULL, "a9mpcore_priv"); |
| 187 | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); |
| 188 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 189 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 190 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); |
| 191 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 192 | sysbus_connect_irq(busdev, n, gate_irq[n][0]); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 193 | } |
| 194 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { |
| 195 | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); |
| 196 | } |
| 197 | |
| 198 | /* Cache controller */ |
| 199 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); |
| 200 | |
| 201 | /* External GIC */ |
| 202 | dev = qdev_create(NULL, "exynos4210.gic"); |
| 203 | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); |
| 204 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 205 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 206 | /* Map CPU interface */ |
| 207 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); |
| 208 | /* Map Distributer interface */ |
| 209 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); |
| 210 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
Evgeny Voevodin | 61558e7 | 2012-05-28 04:11:49 +0000 | [diff] [blame] | 211 | sysbus_connect_irq(busdev, n, gate_irq[n][1]); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 212 | } |
| 213 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { |
| 214 | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); |
| 215 | } |
| 216 | |
| 217 | /* Internal Interrupt Combiner */ |
| 218 | dev = qdev_create(NULL, "exynos4210.combiner"); |
| 219 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 220 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 221 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
| 222 | sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); |
| 223 | } |
| 224 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); |
| 225 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); |
| 226 | |
| 227 | /* External Interrupt Combiner */ |
| 228 | dev = qdev_create(NULL, "exynos4210.combiner"); |
| 229 | qdev_prop_set_uint32(dev, "external", 1); |
| 230 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 231 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 232 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
| 233 | sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); |
| 234 | } |
| 235 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); |
| 236 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); |
| 237 | |
| 238 | /* Initialize board IRQs. */ |
| 239 | exynos4210_init_board_irqs(&s->irqs); |
| 240 | |
| 241 | /*** Memory ***/ |
| 242 | |
| 243 | /* Chip-ID and OMR */ |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 244 | memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, |
Igor Mitsyanko | 11a5e48 | 2013-06-03 17:17:46 +0100 | [diff] [blame] | 245 | NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 246 | memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, |
| 247 | &s->chipid_mem); |
| 248 | |
| 249 | /* Internal ROM */ |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 250 | memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 251 | EXYNOS4210_IROM_SIZE); |
Igor Mitsyanko | 6539ed2 | 2013-06-03 17:17:46 +0100 | [diff] [blame] | 252 | vmstate_register_ram_global(&s->irom_mem); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 253 | memory_region_set_readonly(&s->irom_mem, true); |
| 254 | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, |
| 255 | &s->irom_mem); |
| 256 | /* mirror of iROM */ |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 257 | memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 258 | &s->irom_mem, |
Evgeny Voevodin | 7892df0 | 2012-07-04 10:43:32 +0000 | [diff] [blame] | 259 | 0, |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 260 | EXYNOS4210_IROM_SIZE); |
| 261 | memory_region_set_readonly(&s->irom_alias_mem, true); |
| 262 | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, |
| 263 | &s->irom_alias_mem); |
| 264 | |
| 265 | /* Internal RAM */ |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 266 | memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 267 | EXYNOS4210_IRAM_SIZE); |
| 268 | vmstate_register_ram_global(&s->iram_mem); |
| 269 | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, |
| 270 | &s->iram_mem); |
| 271 | |
| 272 | /* DRAM */ |
| 273 | mem_size = ram_size; |
| 274 | if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 275 | memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 276 | mem_size - EXYNOS4210_DRAM_MAX_SIZE); |
| 277 | vmstate_register_ram_global(&s->dram1_mem); |
| 278 | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, |
| 279 | &s->dram1_mem); |
| 280 | mem_size = EXYNOS4210_DRAM_MAX_SIZE; |
| 281 | } |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 282 | memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size); |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 283 | vmstate_register_ram_global(&s->dram0_mem); |
| 284 | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, |
| 285 | &s->dram0_mem); |
| 286 | |
Maksim Kozlov | df91b48 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 287 | /* PMU. |
| 288 | * The only reason of existence at the moment is that secondary CPU boot |
| 289 | * loader uses PMU INFORM5 register as a holding pen. |
| 290 | */ |
| 291 | sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); |
| 292 | |
Evgeny Voevodin | 62db8bf | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 293 | /* PWM */ |
| 294 | sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, |
| 295 | s->irq_table[exynos4210_get_irq(22, 0)], |
| 296 | s->irq_table[exynos4210_get_irq(22, 1)], |
| 297 | s->irq_table[exynos4210_get_irq(22, 2)], |
| 298 | s->irq_table[exynos4210_get_irq(22, 3)], |
| 299 | s->irq_table[exynos4210_get_irq(22, 4)], |
| 300 | NULL); |
Oleg Ogurtsov | 7bdf43a | 2012-07-04 10:43:32 +0000 | [diff] [blame] | 301 | /* RTC */ |
| 302 | sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, |
| 303 | s->irq_table[exynos4210_get_irq(23, 0)], |
| 304 | s->irq_table[exynos4210_get_irq(23, 1)], |
| 305 | NULL); |
Evgeny Voevodin | 62db8bf | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 306 | |
Evgeny Voevodin | 12c775d | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 307 | /* Multi Core Timer */ |
| 308 | dev = qdev_create(NULL, "exynos4210.mct"); |
| 309 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 310 | busdev = SYS_BUS_DEVICE(dev); |
Evgeny Voevodin | 12c775d | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 311 | for (n = 0; n < 4; n++) { |
| 312 | /* Connect global timer interrupts to Combiner gpio_in */ |
| 313 | sysbus_connect_irq(busdev, n, |
| 314 | s->irq_table[exynos4210_get_irq(1, 4 + n)]); |
| 315 | } |
| 316 | /* Connect local timer interrupts to Combiner gpio_in */ |
| 317 | sysbus_connect_irq(busdev, 4, |
| 318 | s->irq_table[exynos4210_get_irq(51, 0)]); |
| 319 | sysbus_connect_irq(busdev, 5, |
| 320 | s->irq_table[exynos4210_get_irq(35, 3)]); |
| 321 | sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); |
| 322 | |
Mitsyanko Igor | ffbbe7d | 2012-07-18 08:18:34 +0000 | [diff] [blame] | 323 | /*** I2C ***/ |
| 324 | for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { |
| 325 | uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; |
| 326 | qemu_irq i2c_irq; |
| 327 | |
| 328 | if (n < 8) { |
| 329 | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; |
| 330 | } else { |
| 331 | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; |
| 332 | } |
| 333 | |
| 334 | dev = qdev_create(NULL, "exynos4210.i2c"); |
| 335 | qdev_init_nofail(dev); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 336 | busdev = SYS_BUS_DEVICE(dev); |
Mitsyanko Igor | ffbbe7d | 2012-07-18 08:18:34 +0000 | [diff] [blame] | 337 | sysbus_connect_irq(busdev, 0, i2c_irq); |
| 338 | sysbus_mmio_map(busdev, 0, addr); |
| 339 | s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); |
| 340 | } |
| 341 | |
| 342 | |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 343 | /*** UARTs ***/ |
| 344 | exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, |
| 345 | EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, |
| 346 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); |
| 347 | |
| 348 | exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, |
| 349 | EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, |
| 350 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); |
| 351 | |
| 352 | exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, |
| 353 | EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, |
| 354 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); |
| 355 | |
| 356 | exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, |
| 357 | EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, |
| 358 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); |
| 359 | |
Mitsyanko Igor | 30628cb | 2012-02-16 09:56:06 +0000 | [diff] [blame] | 360 | /*** Display controller (FIMD) ***/ |
| 361 | sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, |
| 362 | s->irq_table[exynos4210_get_irq(11, 0)], |
| 363 | s->irq_table[exynos4210_get_irq(11, 1)], |
| 364 | s->irq_table[exynos4210_get_irq(11, 2)], |
| 365 | NULL); |
| 366 | |
Liming Wang | 358d615 | 2012-12-16 04:49:46 +0100 | [diff] [blame] | 367 | sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, |
| 368 | s->irq_table[exynos4210_get_irq(28, 3)]); |
| 369 | |
Evgeny Voevodin | 0caa711 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 370 | return s; |
| 371 | } |