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bellardb92e5a22003-08-08 23:58:05 +00001/*
2 * Software MMU support
ths5fafdf22007-09-16 21:08:06 +00003 *
Blue Swirlefbf29b2011-09-21 20:00:18 +00004 * Generate inline load/store functions for one MMU mode and data
5 * size.
6 *
7 * Generate a store function as well as signed and unsigned loads. For
8 * 32 and 64 bit cases, also generate floating point functions with
9 * the same size.
10 *
11 * Not used directly but included from softmmu_exec.h and exec-all.h.
12 *
bellardb92e5a22003-08-08 23:58:05 +000013 * Copyright (c) 2003 Fabrice Bellard
14 *
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2 of the License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
24 *
25 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000026 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardb92e5a22003-08-08 23:58:05 +000027 */
28#if DATA_SIZE == 8
29#define SUFFIX q
bellard61382a52003-10-27 21:22:23 +000030#define USUFFIX q
bellardb92e5a22003-08-08 23:58:05 +000031#define DATA_TYPE uint64_t
32#elif DATA_SIZE == 4
33#define SUFFIX l
bellard61382a52003-10-27 21:22:23 +000034#define USUFFIX l
bellardb92e5a22003-08-08 23:58:05 +000035#define DATA_TYPE uint32_t
36#elif DATA_SIZE == 2
37#define SUFFIX w
bellard61382a52003-10-27 21:22:23 +000038#define USUFFIX uw
bellardb92e5a22003-08-08 23:58:05 +000039#define DATA_TYPE uint16_t
40#define DATA_STYPE int16_t
41#elif DATA_SIZE == 1
42#define SUFFIX b
bellard61382a52003-10-27 21:22:23 +000043#define USUFFIX ub
bellardb92e5a22003-08-08 23:58:05 +000044#define DATA_TYPE uint8_t
45#define DATA_STYPE int8_t
46#else
47#error unsupported data size
48#endif
49
j_mayer6ebbf392007-10-14 07:07:08 +000050#if ACCESS_TYPE < (NB_MMU_MODES)
bellard61382a52003-10-27 21:22:23 +000051
j_mayer6ebbf392007-10-14 07:07:08 +000052#define CPU_MMU_INDEX ACCESS_TYPE
bellard61382a52003-10-27 21:22:23 +000053#define MMUSUFFIX _mmu
54
j_mayer6ebbf392007-10-14 07:07:08 +000055#elif ACCESS_TYPE == (NB_MMU_MODES)
bellard61382a52003-10-27 21:22:23 +000056
j_mayer6ebbf392007-10-14 07:07:08 +000057#define CPU_MMU_INDEX (cpu_mmu_index(env))
bellard61382a52003-10-27 21:22:23 +000058#define MMUSUFFIX _mmu
59
j_mayer6ebbf392007-10-14 07:07:08 +000060#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
bellard61382a52003-10-27 21:22:23 +000061
j_mayer6ebbf392007-10-14 07:07:08 +000062#define CPU_MMU_INDEX (cpu_mmu_index(env))
bellard61382a52003-10-27 21:22:23 +000063#define MMUSUFFIX _cmmu
64
bellardb92e5a22003-08-08 23:58:05 +000065#else
bellard61382a52003-10-27 21:22:23 +000066#error invalid ACCESS_TYPE
bellardb92e5a22003-08-08 23:58:05 +000067#endif
68
69#if DATA_SIZE == 8
70#define RES_TYPE uint64_t
71#else
Igor V. Kovalenkoc086b782010-06-02 00:12:32 +040072#define RES_TYPE uint32_t
bellardb92e5a22003-08-08 23:58:05 +000073#endif
74
j_mayer6ebbf392007-10-14 07:07:08 +000075#if ACCESS_TYPE == (NB_MMU_MODES + 1)
bellard84b7b8e2005-11-28 21:19:04 +000076#define ADDR_READ addr_code
77#else
78#define ADDR_READ addr_read
79#endif
bellardb92e5a22003-08-08 23:58:05 +000080
bellarde16c53f2004-01-04 18:15:29 +000081/* generic load/store macros */
82
Blue Swirle141ab52011-09-18 14:55:46 +000083static inline RES_TYPE
Blue Swirl89c33332012-09-02 15:28:56 +000084glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
bellardb92e5a22003-08-08 23:58:05 +000085{
blueswir14d7a0882008-05-10 10:14:22 +000086 int page_index;
bellardb92e5a22003-08-08 23:58:05 +000087 RES_TYPE res;
bellardc27004e2005-01-03 23:35:10 +000088 target_ulong addr;
j_mayer6ebbf392007-10-14 07:07:08 +000089 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +000090
bellardc27004e2005-01-03 23:35:10 +000091 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +000092 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +000093 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +000094 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
95 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
Blue Swirl89c33332012-09-02 15:28:56 +000096 res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +000097 } else {
Stefan Weil23ddbf02012-04-15 21:02:09 +020098 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
Stefan Weilb0659272012-04-12 14:14:51 +020099 res = glue(glue(ld, USUFFIX), _raw)(hostaddr);
bellardb92e5a22003-08-08 23:58:05 +0000100 }
101 return res;
102}
103
104#if DATA_SIZE <= 2
Blue Swirle141ab52011-09-18 14:55:46 +0000105static inline int
Blue Swirl89c33332012-09-02 15:28:56 +0000106glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
bellardb92e5a22003-08-08 23:58:05 +0000107{
blueswir14d7a0882008-05-10 10:14:22 +0000108 int res, page_index;
bellardc27004e2005-01-03 23:35:10 +0000109 target_ulong addr;
j_mayer6ebbf392007-10-14 07:07:08 +0000110 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +0000111
bellardc27004e2005-01-03 23:35:10 +0000112 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +0000113 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +0000114 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +0000115 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
116 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
Blue Swirl89c33332012-09-02 15:28:56 +0000117 res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),
118 MMUSUFFIX)(env, addr, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +0000119 } else {
Stefan Weil23ddbf02012-04-15 21:02:09 +0200120 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
Stefan Weilb0659272012-04-12 14:14:51 +0200121 res = glue(glue(lds, SUFFIX), _raw)(hostaddr);
bellardb92e5a22003-08-08 23:58:05 +0000122 }
123 return res;
124}
125#endif
126
j_mayer6ebbf392007-10-14 07:07:08 +0000127#if ACCESS_TYPE != (NB_MMU_MODES + 1)
bellard84b7b8e2005-11-28 21:19:04 +0000128
bellarde16c53f2004-01-04 18:15:29 +0000129/* generic store macro */
130
Blue Swirle141ab52011-09-18 14:55:46 +0000131static inline void
Blue Swirl89c33332012-09-02 15:28:56 +0000132glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
133 RES_TYPE v)
bellardb92e5a22003-08-08 23:58:05 +0000134{
blueswir14d7a0882008-05-10 10:14:22 +0000135 int page_index;
bellardc27004e2005-01-03 23:35:10 +0000136 target_ulong addr;
j_mayer6ebbf392007-10-14 07:07:08 +0000137 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +0000138
bellardc27004e2005-01-03 23:35:10 +0000139 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +0000140 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +0000141 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +0000142 if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
143 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
Blue Swirl89c33332012-09-02 15:28:56 +0000144 glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +0000145 } else {
Stefan Weil23ddbf02012-04-15 21:02:09 +0200146 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
Stefan Weilb0659272012-04-12 14:14:51 +0200147 glue(glue(st, SUFFIX), _raw)(hostaddr, v);
bellardb92e5a22003-08-08 23:58:05 +0000148 }
149}
150
j_mayer6ebbf392007-10-14 07:07:08 +0000151#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
bellard84b7b8e2005-11-28 21:19:04 +0000152
j_mayer6ebbf392007-10-14 07:07:08 +0000153#if ACCESS_TYPE != (NB_MMU_MODES + 1)
bellarde16c53f2004-01-04 18:15:29 +0000154
bellard2d603d22004-01-04 23:56:24 +0000155#if DATA_SIZE == 8
Blue Swirl89c33332012-09-02 15:28:56 +0000156static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
157 target_ulong ptr)
bellard2d603d22004-01-04 23:56:24 +0000158{
159 union {
bellard3f87bf62005-11-06 19:56:23 +0000160 float64 d;
bellard2d603d22004-01-04 23:56:24 +0000161 uint64_t i;
162 } u;
Blue Swirl89c33332012-09-02 15:28:56 +0000163 u.i = glue(cpu_ldq, MEMSUFFIX)(env, ptr);
bellard2d603d22004-01-04 23:56:24 +0000164 return u.d;
165}
166
Blue Swirl89c33332012-09-02 15:28:56 +0000167static inline void glue(cpu_stfq, MEMSUFFIX)(CPUArchState *env,
168 target_ulong ptr, float64 v)
bellard2d603d22004-01-04 23:56:24 +0000169{
170 union {
bellard3f87bf62005-11-06 19:56:23 +0000171 float64 d;
bellard2d603d22004-01-04 23:56:24 +0000172 uint64_t i;
173 } u;
174 u.d = v;
Blue Swirl89c33332012-09-02 15:28:56 +0000175 glue(cpu_stq, MEMSUFFIX)(env, ptr, u.i);
bellard2d603d22004-01-04 23:56:24 +0000176}
177#endif /* DATA_SIZE == 8 */
178
179#if DATA_SIZE == 4
Blue Swirl89c33332012-09-02 15:28:56 +0000180static inline float32 glue(cpu_ldfl, MEMSUFFIX)(CPUArchState *env,
181 target_ulong ptr)
bellard2d603d22004-01-04 23:56:24 +0000182{
183 union {
bellard3f87bf62005-11-06 19:56:23 +0000184 float32 f;
bellard2d603d22004-01-04 23:56:24 +0000185 uint32_t i;
186 } u;
Blue Swirl89c33332012-09-02 15:28:56 +0000187 u.i = glue(cpu_ldl, MEMSUFFIX)(env, ptr);
bellard2d603d22004-01-04 23:56:24 +0000188 return u.f;
189}
190
Blue Swirl89c33332012-09-02 15:28:56 +0000191static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
192 target_ulong ptr, float32 v)
bellard2d603d22004-01-04 23:56:24 +0000193{
194 union {
bellard3f87bf62005-11-06 19:56:23 +0000195 float32 f;
bellard2d603d22004-01-04 23:56:24 +0000196 uint32_t i;
197 } u;
198 u.f = v;
Blue Swirl89c33332012-09-02 15:28:56 +0000199 glue(cpu_stl, MEMSUFFIX)(env, ptr, u.i);
bellard2d603d22004-01-04 23:56:24 +0000200}
201#endif /* DATA_SIZE == 4 */
202
j_mayer6ebbf392007-10-14 07:07:08 +0000203#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
bellard84b7b8e2005-11-28 21:19:04 +0000204
bellardb92e5a22003-08-08 23:58:05 +0000205#undef RES_TYPE
206#undef DATA_TYPE
207#undef DATA_STYPE
208#undef SUFFIX
bellard61382a52003-10-27 21:22:23 +0000209#undef USUFFIX
bellardb92e5a22003-08-08 23:58:05 +0000210#undef DATA_SIZE
j_mayer6ebbf392007-10-14 07:07:08 +0000211#undef CPU_MMU_INDEX
bellard61382a52003-10-27 21:22:23 +0000212#undef MMUSUFFIX
bellard84b7b8e2005-11-28 21:19:04 +0000213#undef ADDR_READ