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bellardb92e5a22003-08-08 23:58:05 +00001/*
2 * Software MMU support
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardb92e5a22003-08-08 23:58:05 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define DATA_SIZE (1 << SHIFT)
21
22#if DATA_SIZE == 8
23#define SUFFIX q
bellard61382a52003-10-27 21:22:23 +000024#define USUFFIX q
bellardb92e5a22003-08-08 23:58:05 +000025#define DATA_TYPE uint64_t
26#elif DATA_SIZE == 4
27#define SUFFIX l
bellard61382a52003-10-27 21:22:23 +000028#define USUFFIX l
bellardb92e5a22003-08-08 23:58:05 +000029#define DATA_TYPE uint32_t
30#elif DATA_SIZE == 2
31#define SUFFIX w
bellard61382a52003-10-27 21:22:23 +000032#define USUFFIX uw
bellardb92e5a22003-08-08 23:58:05 +000033#define DATA_TYPE uint16_t
34#elif DATA_SIZE == 1
35#define SUFFIX b
bellard61382a52003-10-27 21:22:23 +000036#define USUFFIX ub
bellardb92e5a22003-08-08 23:58:05 +000037#define DATA_TYPE uint8_t
38#else
39#error unsupported data size
40#endif
41
bellardb769d8f2004-10-03 15:07:13 +000042#ifdef SOFTMMU_CODE_ACCESS
43#define READ_ACCESS_TYPE 2
bellard84b7b8e2005-11-28 21:19:04 +000044#define ADDR_READ addr_code
bellardb769d8f2004-10-03 15:07:13 +000045#else
46#define READ_ACCESS_TYPE 0
bellard84b7b8e2005-11-28 21:19:04 +000047#define ADDR_READ addr_read
bellardb769d8f2004-10-03 15:07:13 +000048#endif
49
ths5fafdf22007-09-16 21:08:06 +000050static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +000051 int is_user,
52 void *retaddr);
ths5fafdf22007-09-16 21:08:06 +000053static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
bellardc27004e2005-01-03 23:35:10 +000054 target_ulong tlb_addr)
bellardb92e5a22003-08-08 23:58:05 +000055{
56 DATA_TYPE res;
57 int index;
58
59 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
60#if SHIFT <= 2
bellarda4193c82004-06-03 14:01:43 +000061 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
bellardb92e5a22003-08-08 23:58:05 +000062#else
63#ifdef TARGET_WORDS_BIGENDIAN
bellarda4193c82004-06-03 14:01:43 +000064 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
65 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
bellardb92e5a22003-08-08 23:58:05 +000066#else
bellarda4193c82004-06-03 14:01:43 +000067 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
68 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
bellardb92e5a22003-08-08 23:58:05 +000069#endif
70#endif /* SHIFT > 2 */
bellardf1c85672006-02-08 22:41:53 +000071#ifdef USE_KQEMU
72 env->last_io_time = cpu_get_time_fast();
73#endif
bellardb92e5a22003-08-08 23:58:05 +000074 return res;
75}
76
bellardb92e5a22003-08-08 23:58:05 +000077/* handle all cases except unaligned access which span two pages */
bellardc27004e2005-01-03 23:35:10 +000078DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +000079 int is_user)
bellardb92e5a22003-08-08 23:58:05 +000080{
81 DATA_TYPE res;
bellard61382a52003-10-27 21:22:23 +000082 int index;
bellardc27004e2005-01-03 23:35:10 +000083 target_ulong tlb_addr;
bellard108c49b2005-07-24 12:55:09 +000084 target_phys_addr_t physaddr;
bellardb92e5a22003-08-08 23:58:05 +000085 void *retaddr;
ths5fafdf22007-09-16 21:08:06 +000086
bellardb92e5a22003-08-08 23:58:05 +000087 /* test if there is match for unaligned or IO access */
88 /* XXX: could done more in memory macro in a non portable way */
bellardb92e5a22003-08-08 23:58:05 +000089 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
90 redo:
bellard84b7b8e2005-11-28 21:19:04 +000091 tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
bellardb92e5a22003-08-08 23:58:05 +000092 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard84b7b8e2005-11-28 21:19:04 +000093 physaddr = addr + env->tlb_table[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +000094 if (tlb_addr & ~TARGET_PAGE_MASK) {
95 /* IO access */
96 if ((addr & (DATA_SIZE - 1)) != 0)
97 goto do_unaligned_access;
98 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
bellard98699962005-11-26 10:29:22 +000099 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000100 /* slow unaligned access (it spans two pages or IO) */
101 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +0000102 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000103#ifdef ALIGNED_ONLY
104 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
105#endif
ths5fafdf22007-09-16 21:08:06 +0000106 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
bellard61382a52003-10-27 21:22:23 +0000107 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000108 } else {
bellarda64d4712005-12-05 19:57:57 +0000109 /* unaligned/aligned access in the same page */
110#ifdef ALIGNED_ONLY
111 if ((addr & (DATA_SIZE - 1)) != 0) {
112 retaddr = GETPC();
113 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
114 }
115#endif
bellard108c49b2005-07-24 12:55:09 +0000116 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
bellardb92e5a22003-08-08 23:58:05 +0000117 }
118 } else {
119 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000120 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000121#ifdef ALIGNED_ONLY
122 if ((addr & (DATA_SIZE - 1)) != 0)
123 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
124#endif
bellardb769d8f2004-10-03 15:07:13 +0000125 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000126 goto redo;
127 }
128 return res;
129}
130
131/* handle all unaligned cases */
ths5fafdf22007-09-16 21:08:06 +0000132static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000133 int is_user,
134 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000135{
136 DATA_TYPE res, res1, res2;
bellard61382a52003-10-27 21:22:23 +0000137 int index, shift;
bellard108c49b2005-07-24 12:55:09 +0000138 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000139 target_ulong tlb_addr, addr1, addr2;
bellardb92e5a22003-08-08 23:58:05 +0000140
bellardb92e5a22003-08-08 23:58:05 +0000141 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
142 redo:
bellard84b7b8e2005-11-28 21:19:04 +0000143 tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
bellardb92e5a22003-08-08 23:58:05 +0000144 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard84b7b8e2005-11-28 21:19:04 +0000145 physaddr = addr + env->tlb_table[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000146 if (tlb_addr & ~TARGET_PAGE_MASK) {
147 /* IO access */
148 if ((addr & (DATA_SIZE - 1)) != 0)
149 goto do_unaligned_access;
150 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
bellard98699962005-11-26 10:29:22 +0000151 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000152 do_unaligned_access:
153 /* slow unaligned access (it spans two pages) */
154 addr1 = addr & ~(DATA_SIZE - 1);
155 addr2 = addr1 + DATA_SIZE;
ths5fafdf22007-09-16 21:08:06 +0000156 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
bellard61382a52003-10-27 21:22:23 +0000157 is_user, retaddr);
ths5fafdf22007-09-16 21:08:06 +0000158 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
bellard61382a52003-10-27 21:22:23 +0000159 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000160 shift = (addr & (DATA_SIZE - 1)) * 8;
161#ifdef TARGET_WORDS_BIGENDIAN
162 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
163#else
164 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
165#endif
bellard6986f882004-01-18 21:53:18 +0000166 res = (DATA_TYPE)res;
bellardb92e5a22003-08-08 23:58:05 +0000167 } else {
168 /* unaligned/aligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000169 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
bellardb92e5a22003-08-08 23:58:05 +0000170 }
171 } else {
172 /* the page is not in the TLB : fill it */
bellardb769d8f2004-10-03 15:07:13 +0000173 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000174 goto redo;
175 }
176 return res;
177}
178
bellardb769d8f2004-10-03 15:07:13 +0000179#ifndef SOFTMMU_CODE_ACCESS
180
ths5fafdf22007-09-16 21:08:06 +0000181static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
182 DATA_TYPE val,
bellardb769d8f2004-10-03 15:07:13 +0000183 int is_user,
184 void *retaddr);
185
ths5fafdf22007-09-16 21:08:06 +0000186static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
bellardb769d8f2004-10-03 15:07:13 +0000187 DATA_TYPE val,
bellardc27004e2005-01-03 23:35:10 +0000188 target_ulong tlb_addr,
bellardb769d8f2004-10-03 15:07:13 +0000189 void *retaddr)
190{
191 int index;
192
193 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
194 env->mem_write_vaddr = tlb_addr;
195 env->mem_write_pc = (unsigned long)retaddr;
196#if SHIFT <= 2
197 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
198#else
199#ifdef TARGET_WORDS_BIGENDIAN
200 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
201 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
202#else
203 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
204 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
205#endif
206#endif /* SHIFT > 2 */
bellardf1c85672006-02-08 22:41:53 +0000207#ifdef USE_KQEMU
208 env->last_io_time = cpu_get_time_fast();
209#endif
bellardb769d8f2004-10-03 15:07:13 +0000210}
bellardb92e5a22003-08-08 23:58:05 +0000211
ths5fafdf22007-09-16 21:08:06 +0000212void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000213 DATA_TYPE val,
214 int is_user)
bellardb92e5a22003-08-08 23:58:05 +0000215{
bellard108c49b2005-07-24 12:55:09 +0000216 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000217 target_ulong tlb_addr;
bellardb92e5a22003-08-08 23:58:05 +0000218 void *retaddr;
bellard61382a52003-10-27 21:22:23 +0000219 int index;
ths5fafdf22007-09-16 21:08:06 +0000220
bellardb92e5a22003-08-08 23:58:05 +0000221 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
222 redo:
bellard84b7b8e2005-11-28 21:19:04 +0000223 tlb_addr = env->tlb_table[is_user][index].addr_write;
bellardb92e5a22003-08-08 23:58:05 +0000224 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard84b7b8e2005-11-28 21:19:04 +0000225 physaddr = addr + env->tlb_table[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000226 if (tlb_addr & ~TARGET_PAGE_MASK) {
227 /* IO access */
228 if ((addr & (DATA_SIZE - 1)) != 0)
229 goto do_unaligned_access;
bellardd720b932004-04-25 17:57:43 +0000230 retaddr = GETPC();
231 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000232 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000233 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +0000234 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000235#ifdef ALIGNED_ONLY
236 do_unaligned_access(addr, 1, is_user, retaddr);
237#endif
ths5fafdf22007-09-16 21:08:06 +0000238 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
bellard61382a52003-10-27 21:22:23 +0000239 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000240 } else {
241 /* aligned/unaligned access in the same page */
bellarda64d4712005-12-05 19:57:57 +0000242#ifdef ALIGNED_ONLY
243 if ((addr & (DATA_SIZE - 1)) != 0) {
244 retaddr = GETPC();
245 do_unaligned_access(addr, 1, is_user, retaddr);
246 }
247#endif
bellard108c49b2005-07-24 12:55:09 +0000248 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
bellardb92e5a22003-08-08 23:58:05 +0000249 }
250 } else {
251 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000252 retaddr = GETPC();
bellarda64d4712005-12-05 19:57:57 +0000253#ifdef ALIGNED_ONLY
254 if ((addr & (DATA_SIZE - 1)) != 0)
255 do_unaligned_access(addr, 1, is_user, retaddr);
256#endif
bellard61382a52003-10-27 21:22:23 +0000257 tlb_fill(addr, 1, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000258 goto redo;
259 }
260}
261
262/* handles all unaligned cases */
ths5fafdf22007-09-16 21:08:06 +0000263static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000264 DATA_TYPE val,
265 int is_user,
266 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000267{
bellard108c49b2005-07-24 12:55:09 +0000268 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000269 target_ulong tlb_addr;
bellard61382a52003-10-27 21:22:23 +0000270 int index, i;
bellardb92e5a22003-08-08 23:58:05 +0000271
bellardb92e5a22003-08-08 23:58:05 +0000272 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
273 redo:
bellard84b7b8e2005-11-28 21:19:04 +0000274 tlb_addr = env->tlb_table[is_user][index].addr_write;
bellardb92e5a22003-08-08 23:58:05 +0000275 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard84b7b8e2005-11-28 21:19:04 +0000276 physaddr = addr + env->tlb_table[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000277 if (tlb_addr & ~TARGET_PAGE_MASK) {
278 /* IO access */
279 if ((addr & (DATA_SIZE - 1)) != 0)
280 goto do_unaligned_access;
bellardd720b932004-04-25 17:57:43 +0000281 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000282 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000283 do_unaligned_access:
284 /* XXX: not efficient, but simple */
285 for(i = 0;i < DATA_SIZE; i++) {
286#ifdef TARGET_WORDS_BIGENDIAN
ths5fafdf22007-09-16 21:08:06 +0000287 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
bellard61382a52003-10-27 21:22:23 +0000288 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000289#else
ths5fafdf22007-09-16 21:08:06 +0000290 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
bellard61382a52003-10-27 21:22:23 +0000291 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000292#endif
293 }
294 } else {
295 /* aligned/unaligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000296 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
bellardb92e5a22003-08-08 23:58:05 +0000297 }
298 } else {
299 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000300 tlb_fill(addr, 1, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000301 goto redo;
302 }
303}
304
bellardb769d8f2004-10-03 15:07:13 +0000305#endif /* !defined(SOFTMMU_CODE_ACCESS) */
306
307#undef READ_ACCESS_TYPE
bellardb92e5a22003-08-08 23:58:05 +0000308#undef SHIFT
309#undef DATA_TYPE
310#undef SUFFIX
bellard61382a52003-10-27 21:22:23 +0000311#undef USUFFIX
bellardb92e5a22003-08-08 23:58:05 +0000312#undef DATA_SIZE
bellard84b7b8e2005-11-28 21:19:04 +0000313#undef ADDR_READ