pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Ultrasparc APB PCI host |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
pbrook | 80b3ada | 2006-09-24 17:01:44 +0000 | [diff] [blame] | 24 | |
blueswir1 | a94fd95 | 2009-01-09 20:53:30 +0000 | [diff] [blame] | 25 | /* XXX This file and most of its contents are somewhat misnamed. The |
pbrook | 80b3ada | 2006-09-24 17:01:44 +0000 | [diff] [blame] | 26 | Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is |
| 27 | the secondary PCI bridge. */ |
| 28 | |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 29 | #include "sysbus.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 30 | #include "pci.h" |
Isaku Yamahata | 4f5e19e | 2009-10-30 21:21:06 +0900 | [diff] [blame] | 31 | #include "pci_host.h" |
Michael S. Tsirkin | 18e08a5 | 2009-11-11 14:59:56 +0200 | [diff] [blame] | 32 | #include "apb_pci.h" |
blueswir1 | a94fd95 | 2009-01-09 20:53:30 +0000 | [diff] [blame] | 33 | |
| 34 | /* debug APB */ |
| 35 | //#define DEBUG_APB |
| 36 | |
| 37 | #ifdef DEBUG_APB |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 38 | #define APB_DPRINTF(fmt, ...) \ |
| 39 | do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) |
blueswir1 | a94fd95 | 2009-01-09 20:53:30 +0000 | [diff] [blame] | 40 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 41 | #define APB_DPRINTF(fmt, ...) |
blueswir1 | a94fd95 | 2009-01-09 20:53:30 +0000 | [diff] [blame] | 42 | #endif |
| 43 | |
Blue Swirl | 930f3fe | 2009-10-13 18:56:27 +0000 | [diff] [blame] | 44 | /* |
| 45 | * Chipset docs: |
| 46 | * PBM: "UltraSPARC IIi User's Manual", |
| 47 | * http://www.sun.com/processors/manuals/805-0087.pdf |
| 48 | * |
| 49 | * APB: "Advanced PCI Bridge (APB) User's Manual", |
| 50 | * http://www.sun.com/processors/manuals/805-1251.pdf |
| 51 | */ |
| 52 | |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 53 | typedef struct APBState { |
| 54 | SysBusDevice busdev; |
| 55 | PCIHostState host_state; |
| 56 | } APBState; |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 57 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 58 | static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 59 | uint32_t val) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 60 | { |
| 61 | //PCIBus *s = opaque; |
| 62 | |
| 63 | switch (addr & 0x3f) { |
| 64 | case 0x00: // Control/Status |
| 65 | case 0x10: // AFSR |
| 66 | case 0x18: // AFAR |
| 67 | case 0x20: // Diagnostic |
| 68 | case 0x28: // Target address space |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 69 | // XXX |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 70 | default: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 71 | break; |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 72 | } |
| 73 | } |
| 74 | |
| 75 | static uint32_t apb_config_readl (void *opaque, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 76 | target_phys_addr_t addr) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 77 | { |
| 78 | //PCIBus *s = opaque; |
| 79 | uint32_t val; |
| 80 | |
| 81 | switch (addr & 0x3f) { |
| 82 | case 0x00: // Control/Status |
| 83 | case 0x10: // AFSR |
| 84 | case 0x18: // AFAR |
| 85 | case 0x20: // Diagnostic |
| 86 | case 0x28: // Target address space |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 87 | // XXX |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 88 | default: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 89 | val = 0; |
| 90 | break; |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 91 | } |
| 92 | return val; |
| 93 | } |
| 94 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 95 | static CPUWriteMemoryFunc * const apb_config_write[] = { |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 96 | &apb_config_writel, |
| 97 | &apb_config_writel, |
| 98 | &apb_config_writel, |
| 99 | }; |
| 100 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 101 | static CPUReadMemoryFunc * const apb_config_read[] = { |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 102 | &apb_config_readl, |
| 103 | &apb_config_readl, |
| 104 | &apb_config_readl, |
| 105 | }; |
| 106 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 107 | static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 108 | uint32_t val) |
| 109 | { |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 110 | cpu_outb(addr & IOPORTS_MASK, val); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 111 | } |
| 112 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 113 | static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 114 | uint32_t val) |
| 115 | { |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 116 | cpu_outw(addr & IOPORTS_MASK, val); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 117 | } |
| 118 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 119 | static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 120 | uint32_t val) |
| 121 | { |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 122 | cpu_outl(addr & IOPORTS_MASK, val); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 123 | } |
| 124 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 125 | static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 126 | { |
| 127 | uint32_t val; |
| 128 | |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 129 | val = cpu_inb(addr & IOPORTS_MASK); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 130 | return val; |
| 131 | } |
| 132 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 133 | static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 134 | { |
| 135 | uint32_t val; |
| 136 | |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 137 | val = cpu_inw(addr & IOPORTS_MASK); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 138 | return val; |
| 139 | } |
| 140 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 141 | static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 142 | { |
| 143 | uint32_t val; |
| 144 | |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 145 | val = cpu_inl(addr & IOPORTS_MASK); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 146 | return val; |
| 147 | } |
| 148 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 149 | static CPUWriteMemoryFunc * const pci_apb_iowrite[] = { |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 150 | &pci_apb_iowriteb, |
| 151 | &pci_apb_iowritew, |
| 152 | &pci_apb_iowritel, |
| 153 | }; |
| 154 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 155 | static CPUReadMemoryFunc * const pci_apb_ioread[] = { |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 156 | &pci_apb_ioreadb, |
| 157 | &pci_apb_ioreadw, |
| 158 | &pci_apb_ioreadl, |
| 159 | }; |
| 160 | |
pbrook | 80b3ada | 2006-09-24 17:01:44 +0000 | [diff] [blame] | 161 | /* The APB host has an IRQ line for each IRQ line of each slot. */ |
pbrook | d2b5931 | 2006-09-24 00:16:34 +0000 | [diff] [blame] | 162 | static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 163 | { |
pbrook | 80b3ada | 2006-09-24 17:01:44 +0000 | [diff] [blame] | 164 | return ((pci_dev->devfn & 0x18) >> 1) + irq_num; |
| 165 | } |
| 166 | |
| 167 | static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num) |
| 168 | { |
| 169 | int bus_offset; |
| 170 | if (pci_dev->devfn & 1) |
| 171 | bus_offset = 16; |
| 172 | else |
| 173 | bus_offset = 0; |
| 174 | return bus_offset + irq_num; |
pbrook | d2b5931 | 2006-09-24 00:16:34 +0000 | [diff] [blame] | 175 | } |
| 176 | |
Juan Quintela | 5d4e84c | 2009-08-28 15:28:17 +0200 | [diff] [blame] | 177 | static void pci_apb_set_irq(void *opaque, int irq_num, int level) |
pbrook | d2b5931 | 2006-09-24 00:16:34 +0000 | [diff] [blame] | 178 | { |
Juan Quintela | 5d4e84c | 2009-08-28 15:28:17 +0200 | [diff] [blame] | 179 | qemu_irq *pic = opaque; |
| 180 | |
pbrook | 80b3ada | 2006-09-24 17:01:44 +0000 | [diff] [blame] | 181 | /* PCI IRQ map onto the first 32 INO. */ |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 182 | qemu_set_irq(pic[irq_num], level); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 183 | } |
| 184 | |
Michael S. Tsirkin | d631873 | 2009-11-11 14:33:54 +0200 | [diff] [blame] | 185 | static void apb_pci_bridge_init(PCIBus *b) |
| 186 | { |
| 187 | PCIDevice *dev = pci_bridge_get_device(b); |
| 188 | |
| 189 | /* |
| 190 | * command register: |
| 191 | * According to PCI bridge spec, after reset |
| 192 | * bus master bit is off |
| 193 | * memory space enable bit is off |
| 194 | * According to manual (805-1251.pdf). |
| 195 | * the reset value should be zero unless the boot pin is tied high |
| 196 | * (which is true) and thus it should be PCI_COMMAND_MEMORY. |
| 197 | */ |
| 198 | pci_set_word(dev->config + PCI_COMMAND, |
| 199 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 200 | dev->config[PCI_LATENCY_TIMER] = 0x10; |
| 201 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
| 202 | } |
| 203 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 204 | PCIBus *pci_apb_init(target_phys_addr_t special_base, |
| 205 | target_phys_addr_t mem_base, |
blueswir1 | c190ea0 | 2009-01-10 11:33:32 +0000 | [diff] [blame] | 206 | qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 207 | { |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 208 | DeviceState *dev; |
| 209 | SysBusDevice *s; |
| 210 | APBState *d; |
| 211 | |
| 212 | /* Ultrasparc PBM main bus */ |
| 213 | dev = qdev_create(NULL, "pbm"); |
Markus Armbruster | e23a1b3 | 2009-10-07 01:15:58 +0200 | [diff] [blame] | 214 | qdev_init_nofail(dev); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 215 | s = sysbus_from_qdev(dev); |
| 216 | /* apb_config */ |
Blue Swirl | bae7b51 | 2010-01-10 18:25:48 +0000 | [diff] [blame] | 217 | sysbus_mmio_map(s, 0, special_base); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 218 | /* pci_ioport */ |
| 219 | sysbus_mmio_map(s, 1, special_base + 0x2000000ULL); |
| 220 | /* mem_config: XXX size should be 4G-prom */ |
| 221 | sysbus_mmio_map(s, 2, special_base + 0x1000000ULL); |
| 222 | /* mem_data */ |
| 223 | sysbus_mmio_map(s, 3, mem_base); |
| 224 | d = FROM_SYSBUS(APBState, s); |
Blue Swirl | c5ff6d5 | 2009-09-13 08:32:40 +0000 | [diff] [blame] | 225 | d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 226 | pci_apb_set_irq, pci_pbm_map_irq, pic, |
| 227 | 0, 32); |
Blue Swirl | f6b6f1b | 2009-12-27 20:52:39 +0000 | [diff] [blame] | 228 | pci_bus_set_mem_base(d->host_state.bus, mem_base); |
| 229 | |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 230 | pci_create_simple(d->host_state.bus, 0, "pbm"); |
| 231 | /* APB secondary busses */ |
Isaku Yamahata | 2217dcf | 2009-10-30 21:20:57 +0900 | [diff] [blame] | 232 | *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0), |
| 233 | PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, |
| 234 | pci_apb_map_irq, |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 235 | "Advanced PCI Bus secondary bridge 1"); |
Michael S. Tsirkin | d631873 | 2009-11-11 14:33:54 +0200 | [diff] [blame] | 236 | apb_pci_bridge_init(*bus2); |
| 237 | |
Isaku Yamahata | 2217dcf | 2009-10-30 21:20:57 +0900 | [diff] [blame] | 238 | *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1), |
| 239 | PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, |
| 240 | pci_apb_map_irq, |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 241 | "Advanced PCI Bus secondary bridge 2"); |
Michael S. Tsirkin | d631873 | 2009-11-11 14:33:54 +0200 | [diff] [blame] | 242 | apb_pci_bridge_init(*bus3); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 243 | |
| 244 | return d->host_state.bus; |
| 245 | } |
| 246 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 247 | static int pci_pbm_init_device(SysBusDevice *dev) |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 248 | { |
| 249 | |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 250 | APBState *s; |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 251 | int pci_mem_config, pci_mem_data, apb_config, pci_ioport; |
| 252 | |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 253 | s = FROM_SYSBUS(APBState, dev); |
| 254 | /* apb_config */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 255 | apb_config = cpu_register_io_memory(apb_config_read, |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 256 | apb_config_write, s); |
Blue Swirl | bae7b51 | 2010-01-10 18:25:48 +0000 | [diff] [blame] | 257 | sysbus_init_mmio(dev, 0x10000ULL, apb_config); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 258 | /* pci_ioport */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 259 | pci_ioport = cpu_register_io_memory(pci_apb_ioread, |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 260 | pci_apb_iowrite, s); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 261 | sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); |
| 262 | /* mem_config */ |
Isaku Yamahata | f08b32f | 2009-11-12 14:58:34 +0900 | [diff] [blame] | 263 | pci_mem_config = pci_host_conf_register_mmio(&s->host_state); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 264 | sysbus_init_mmio(dev, 0x10ULL, pci_mem_config); |
| 265 | /* mem_data */ |
Isaku Yamahata | f08b32f | 2009-11-12 14:58:34 +0900 | [diff] [blame] | 266 | pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 267 | sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data); |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 268 | return 0; |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 269 | } |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 270 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 271 | static int pbm_pci_host_init(PCIDevice *d) |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 272 | { |
aliguori | deb5439 | 2009-01-26 15:37:35 +0000 | [diff] [blame] | 273 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN); |
| 274 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 275 | d->config[0x04] = 0x06; // command = bus master, pci mem |
| 276 | d->config[0x05] = 0x00; |
| 277 | d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| 278 | d->config[0x07] = 0x03; // status = medium devsel |
| 279 | d->config[0x08] = 0x00; // revision |
| 280 | d->config[0x09] = 0x00; // programming i/f |
blueswir1 | 173a543 | 2009-02-01 19:26:20 +0000 | [diff] [blame] | 281 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 282 | d->config[0x0D] = 0x10; // latency_timer |
Blue Swirl | 110c50f | 2009-07-11 08:38:39 +0000 | [diff] [blame] | 283 | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 284 | return 0; |
pbrook | 502a539 | 2006-05-13 16:11:23 +0000 | [diff] [blame] | 285 | } |
Blue Swirl | 72f44c8 | 2009-07-21 08:36:37 +0000 | [diff] [blame] | 286 | |
| 287 | static PCIDeviceInfo pbm_pci_host_info = { |
| 288 | .qdev.name = "pbm", |
| 289 | .qdev.size = sizeof(PCIDevice), |
| 290 | .init = pbm_pci_host_init, |
| 291 | }; |
| 292 | |
| 293 | static void pbm_register_devices(void) |
| 294 | { |
| 295 | sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device); |
| 296 | pci_qdev_register(&pbm_pci_host_info); |
| 297 | } |
| 298 | |
| 299 | device_init(pbm_register_devices) |