ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 2 | * Generic ARM Programmable Interrupt Controller support. |
3 | * | ||||
4 | * Copyright (c) 2006 CodeSourcery. | ||||
5 | * Written by Paul Brook | ||||
6 | * | ||||
7 | * This code is licenced under the LGPL | ||||
8 | */ | ||||
9 | |||||
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 10 | #include "hw.h" |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 11 | #include "pc.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 12 | #include "arm-misc.h" |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 13 | |
14 | /* Stub functions for hardware that doesn't exist. */ | ||||
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 15 | void pic_info(Monitor *mon) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 16 | { |
17 | } | ||||
18 | |||||
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 19 | void irq_info(Monitor *mon) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 20 | { |
21 | } | ||||
22 | |||||
23 | |||||
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 24 | /* Input 0 is IRQ and input 1 is FIQ. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 25 | static void arm_pic_cpu_handler(void *opaque, int irq, int level) |
26 | { | ||||
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 27 | CPUState *env = (CPUState *)opaque; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 28 | switch (irq) { |
29 | case ARM_PIC_CPU_IRQ: | ||||
30 | if (level) | ||||
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 31 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 32 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 33 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 34 | break; |
35 | case ARM_PIC_CPU_FIQ: | ||||
36 | if (level) | ||||
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 37 | cpu_interrupt(env, CPU_INTERRUPT_FIQ); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 38 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 39 | cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 40 | break; |
41 | default: | ||||
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 42 | hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 43 | } |
44 | } | ||||
45 | |||||
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 46 | qemu_irq *arm_pic_init_cpu(CPUState *env) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 47 | { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 48 | return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 49 | } |