target-mips: fix updating BadVAddr for misaligned accesses
Update BadVAddr correctly for the case of misaligned block accesses.
The address reported by BadVAddr on page permission or TLB miss exceptions
must be a byte address in the misaligned access for a page on which the
exception is reported, but may be any such byte address.
It is not required to be the lowest.
Cherry-picked from PRPL QEMU :
https://github.com/yongbok/prpl-qemu/commit/3e5e2b5f6affab2c367e8e774105877bc0f505f3
3e5e2b5f target-mips: fix updating BadVAddr for misaligned accesses
Change-Id: I489effe5b4c0c693dca7a41a01157c3477cea47c
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 48181f2..bfcffa2 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -632,6 +632,9 @@
ret = get_physical_address(env, &physical, &prot,
addr, rw, access_type);
if (ret != TLBRET_MATCH) {
+ if (ret != TLBRET_BADADDR && addr > badvaddr) {
+ badvaddr = addr;
+ }
raise_mmu_exception(env, badvaddr, rw, ret);
return false;
}