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android-review.linaro.org / kernel / hikey-linaro / e02db0aa3e1976ae4e23a66077d252a2f3ba74c7 / . / arch / microblaze / kernel / misc.S
blob: 1dafddeb8a0b51c0da0d709b1eb13c67420bd80d [file] [log] [blame]
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]1/*
2 * Miscellaneous low-level MMU functions.
3 *
4 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2008-2009 PetaLogix
6 * Copyright (C) 2007 Xilinx, Inc. All rights reserved.
7 *
8 * Derived from arch/ppc/kernel/misc.S
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 */
14
15#include <linux/linkage.h>
16#include <linux/sys.h>
17#include <asm/unistd.h>
18#include <linux/errno.h>
19#include <asm/mmu.h>
20#include <asm/page.h>
21
22 .text
23/*
24 * Flush MMU TLB
25 *
26 * We avoid flushing the pinned 0, 1 and possibly 2 entries.
27 */
28.globl _tlbia;
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]29.type _tlbia, @function
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]30.align 4;
31_tlbia:
Michal Simeke02db0a2010-02-08 16:41:38 +0100[diff] [blame^]32 lwi r12, r0, tlb_skip;
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]33 /* isync */
34_tlbia_1:
35 mts rtlbx, r12
36 nop
37 mts rtlbhi, r0 /* flush: ensure V is clear */
38 nop
Michal Simeke02db0a2010-02-08 16:41:38 +0100[diff] [blame^]39 rsubi r11, r12, MICROBLAZE_TLB_SIZE - 1
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]40 bneid r11, _tlbia_1 /* loop for all entries */
Michal Simeke02db0a2010-02-08 16:41:38 +0100[diff] [blame^]41 addik r12, r12, 1
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]42 /* sync */
43 rtsd r15, 8
44 nop
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]45 .size _tlbia, . - _tlbia
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]46
47/*
48 * Flush MMU TLB for a particular address (in r5)
49 */
50.globl _tlbie;
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]51.type _tlbie, @function
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]52.align 4;
53_tlbie:
54 mts rtlbsx, r5 /* look up the address in TLB */
55 nop
56 mfs r12, rtlbx /* Retrieve index */
57 nop
58 blti r12, _tlbie_1 /* Check if found */
59 mts rtlbhi, r0 /* flush: ensure V is clear */
60 nop
61_tlbie_1:
62 rtsd r15, 8
63 nop
64
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]65 .size _tlbie, . - _tlbie
66
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]67/*
68 * Allocate TLB entry for early console
69 */
70.globl early_console_reg_tlb_alloc;
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]71.type early_console_reg_tlb_alloc, @function
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]72.align 4;
73early_console_reg_tlb_alloc:
74 /*
75 * Load a TLB entry for the UART, so that microblaze_progress() can use
76 * the UARTs nice and early. We use a 4k real==virtual mapping.
77 */
Michal Simeke02db0a2010-02-08 16:41:38 +0100[diff] [blame^]78 lwi r4, r0, tlb_skip
Michal Simekaf58ed82010-06-04 12:57:06 +0200[diff] [blame]79 mts rtlbx, r4 /* TLB slot 63 */
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]80
81 or r4,r5,r0
82 andi r4,r4,0xfffff000
83 ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
84
85 andi r5,r5,0xfffff000
86 ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
87
88 mts rtlblo,r4 /* Load the data portion of the entry */
89 nop
90 mts rtlbhi,r5 /* Load the tag portion of the entry */
91 nop
Michal Simeke02db0a2010-02-08 16:41:38 +0100[diff] [blame^]92
93 lwi r5, r0, tlb_skip
94 addik r5, r5, 1
95 swi r5, r0, tlb_skip
96
Michal Simek3f504252009-05-26 16:30:10 +0200[diff] [blame]97 rtsd r15, 8
98 nop
99
Michal Simek13851962010-03-23 08:09:32 +0100[diff] [blame]100 .size early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc