Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-tegra/gpio.c |
| 3 | * |
| 4 | * Copyright (c) 2010 Google, Inc |
| 5 | * |
| 6 | * Author: |
| 7 | * Erik Gilling <konkers@google.com> |
| 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and |
| 11 | * may be copied, distributed, and modified under those terms. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/irq.h> |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 23 | #include <linux/io.h> |
| 24 | #include <linux/gpio.h> |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 25 | #include <linux/of_device.h> |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/module.h> |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 28 | #include <linux/irqdomain.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 29 | |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 30 | #include <asm/mach/irq.h> |
| 31 | |
Stephen Warren | ea5abbd | 2011-09-26 19:00:02 +0100 | [diff] [blame] | 32 | #include <mach/gpio-tegra.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 33 | #include <mach/iomap.h> |
Colin Cross | 2ea67fd | 2010-10-04 08:49:49 -0700 | [diff] [blame] | 34 | #include <mach/suspend.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 35 | |
| 36 | #define GPIO_BANK(x) ((x) >> 5) |
| 37 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) |
| 38 | #define GPIO_BIT(x) ((x) & 0x7) |
| 39 | |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 40 | #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ |
| 41 | GPIO_PORT(x) * 4) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 42 | |
| 43 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) |
| 44 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) |
| 45 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) |
| 46 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) |
| 47 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) |
| 48 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) |
| 49 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) |
| 50 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) |
| 51 | |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 52 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) |
| 53 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) |
| 54 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) |
| 55 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) |
| 56 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) |
| 57 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 58 | |
| 59 | #define GPIO_INT_LVL_MASK 0x010101 |
| 60 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 |
| 61 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 |
| 62 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 |
| 63 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 |
| 64 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 |
| 65 | |
| 66 | struct tegra_gpio_bank { |
| 67 | int bank; |
| 68 | int irq; |
| 69 | spinlock_t lvl_lock[4]; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 70 | #ifdef CONFIG_PM |
| 71 | u32 cnf[4]; |
| 72 | u32 out[4]; |
| 73 | u32 oe[4]; |
| 74 | u32 int_enb[4]; |
| 75 | u32 int_lvl[4]; |
| 76 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 77 | }; |
| 78 | |
Stephen Warren | bdc93a7 | 2012-02-13 16:21:15 -0700 | [diff] [blame] | 79 | static struct irq_domain *irq_domain; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 80 | static void __iomem *regs; |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 81 | static u32 tegra_gpio_bank_count; |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 82 | static u32 tegra_gpio_bank_stride; |
| 83 | static u32 tegra_gpio_upper_offset; |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 84 | static struct tegra_gpio_bank *tegra_gpio_banks; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 85 | |
| 86 | static inline void tegra_gpio_writel(u32 val, u32 reg) |
| 87 | { |
| 88 | __raw_writel(val, regs + reg); |
| 89 | } |
| 90 | |
| 91 | static inline u32 tegra_gpio_readl(u32 reg) |
| 92 | { |
| 93 | return __raw_readl(regs + reg); |
| 94 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 95 | |
| 96 | static int tegra_gpio_compose(int bank, int port, int bit) |
| 97 | { |
| 98 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); |
| 99 | } |
| 100 | |
| 101 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) |
| 102 | { |
| 103 | u32 val; |
| 104 | |
| 105 | val = 0x100 << GPIO_BIT(gpio); |
| 106 | if (value) |
| 107 | val |= 1 << GPIO_BIT(gpio); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 108 | tegra_gpio_writel(val, reg); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | void tegra_gpio_enable(int gpio) |
| 112 | { |
| 113 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); |
| 114 | } |
Arnd Bergmann | 691e06c | 2012-03-02 17:32:24 -0500 | [diff] [blame] | 115 | EXPORT_SYMBOL_GPL(tegra_gpio_enable); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 116 | |
| 117 | void tegra_gpio_disable(int gpio) |
| 118 | { |
| 119 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); |
| 120 | } |
Arnd Bergmann | 691e06c | 2012-03-02 17:32:24 -0500 | [diff] [blame] | 121 | EXPORT_SYMBOL_GPL(tegra_gpio_disable); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 122 | |
| 123 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 124 | { |
| 125 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); |
| 126 | } |
| 127 | |
| 128 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 129 | { |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 130 | return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 134 | { |
| 135 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 140 | int value) |
| 141 | { |
| 142 | tegra_gpio_set(chip, offset, value); |
| 143 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); |
| 144 | return 0; |
| 145 | } |
| 146 | |
Stephen Warren | 438a99c | 2011-08-23 00:39:56 +0100 | [diff] [blame] | 147 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 148 | { |
Stephen Warren | bdc93a7 | 2012-02-13 16:21:15 -0700 | [diff] [blame] | 149 | return irq_find_mapping(irq_domain, offset); |
Stephen Warren | 438a99c | 2011-08-23 00:39:56 +0100 | [diff] [blame] | 150 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 151 | |
| 152 | static struct gpio_chip tegra_gpio_chip = { |
| 153 | .label = "tegra-gpio", |
| 154 | .direction_input = tegra_gpio_direction_input, |
| 155 | .get = tegra_gpio_get, |
| 156 | .direction_output = tegra_gpio_direction_output, |
| 157 | .set = tegra_gpio_set, |
Stephen Warren | 438a99c | 2011-08-23 00:39:56 +0100 | [diff] [blame] | 158 | .to_irq = tegra_gpio_to_irq, |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 159 | .base = 0, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 160 | .ngpio = TEGRA_NR_GPIOS, |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 161 | }; |
| 162 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 163 | static void tegra_gpio_irq_ack(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 164 | { |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 165 | int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 166 | |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 167 | tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 168 | } |
| 169 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 170 | static void tegra_gpio_irq_mask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 171 | { |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 172 | int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 173 | |
| 174 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); |
| 175 | } |
| 176 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 177 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 178 | { |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 179 | int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 180 | |
| 181 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); |
| 182 | } |
| 183 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 184 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 185 | { |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 186 | int gpio = d->hwirq; |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 187 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 188 | int port = GPIO_PORT(gpio); |
| 189 | int lvl_type; |
| 190 | int val; |
| 191 | unsigned long flags; |
| 192 | |
| 193 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 194 | case IRQ_TYPE_EDGE_RISING: |
| 195 | lvl_type = GPIO_INT_LVL_EDGE_RISING; |
| 196 | break; |
| 197 | |
| 198 | case IRQ_TYPE_EDGE_FALLING: |
| 199 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; |
| 200 | break; |
| 201 | |
| 202 | case IRQ_TYPE_EDGE_BOTH: |
| 203 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; |
| 204 | break; |
| 205 | |
| 206 | case IRQ_TYPE_LEVEL_HIGH: |
| 207 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; |
| 208 | break; |
| 209 | |
| 210 | case IRQ_TYPE_LEVEL_LOW: |
| 211 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; |
| 212 | break; |
| 213 | |
| 214 | default: |
| 215 | return -EINVAL; |
| 216 | } |
| 217 | |
| 218 | spin_lock_irqsave(&bank->lvl_lock[port], flags); |
| 219 | |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 220 | val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 221 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
| 222 | val |= lvl_type << GPIO_BIT(gpio); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 223 | tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 224 | |
| 225 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
| 226 | |
Stephen Warren | d941136 | 2012-03-19 10:31:58 -0600 | [diff] [blame^] | 227 | tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); |
| 228 | tegra_gpio_enable(gpio); |
| 229 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 230 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 231 | __irq_set_handler_locked(d->irq, handle_level_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 232 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 233 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 239 | { |
| 240 | struct tegra_gpio_bank *bank; |
| 241 | int port; |
| 242 | int pin; |
| 243 | int unmasked = 0; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 244 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 245 | |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 246 | chained_irq_enter(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 247 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 248 | bank = irq_get_handler_data(irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 249 | |
| 250 | for (port = 0; port < 4; port++) { |
| 251 | int gpio = tegra_gpio_compose(bank->bank, port, 0); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 252 | unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & |
| 253 | tegra_gpio_readl(GPIO_INT_ENB(gpio)); |
| 254 | u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 255 | |
| 256 | for_each_set_bit(pin, &sta, 8) { |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 257 | tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 258 | |
| 259 | /* if gpio is edge triggered, clear condition |
| 260 | * before executing the hander so that we don't |
| 261 | * miss edges |
| 262 | */ |
| 263 | if (lvl & (0x100 << pin)) { |
| 264 | unmasked = 1; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 265 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | generic_handle_irq(gpio_to_irq(gpio + pin)); |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | if (!unmasked) |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 273 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 274 | |
| 275 | } |
| 276 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 277 | #ifdef CONFIG_PM |
| 278 | void tegra_gpio_resume(void) |
| 279 | { |
| 280 | unsigned long flags; |
Colin Cross | c8309ef | 2011-03-30 00:24:43 -0700 | [diff] [blame] | 281 | int b; |
| 282 | int p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 283 | |
| 284 | local_irq_save(flags); |
| 285 | |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 286 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 287 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
| 288 | |
| 289 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
| 290 | unsigned int gpio = (b<<5) | (p<<3); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 291 | tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); |
| 292 | tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); |
| 293 | tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); |
| 294 | tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); |
| 295 | tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 296 | } |
| 297 | } |
| 298 | |
| 299 | local_irq_restore(flags); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | void tegra_gpio_suspend(void) |
| 303 | { |
| 304 | unsigned long flags; |
Colin Cross | c8309ef | 2011-03-30 00:24:43 -0700 | [diff] [blame] | 305 | int b; |
| 306 | int p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 307 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 308 | local_irq_save(flags); |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 309 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 310 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
| 311 | |
| 312 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
| 313 | unsigned int gpio = (b<<5) | (p<<3); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 314 | bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); |
| 315 | bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); |
| 316 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); |
| 317 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); |
| 318 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 319 | } |
| 320 | } |
| 321 | local_irq_restore(flags); |
| 322 | } |
| 323 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 324 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 325 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 326 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 327 | return irq_set_irq_wake(bank->irq, enable); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 328 | } |
| 329 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 330 | |
| 331 | static struct irq_chip tegra_gpio_irq_chip = { |
| 332 | .name = "GPIO", |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 333 | .irq_ack = tegra_gpio_irq_ack, |
| 334 | .irq_mask = tegra_gpio_irq_mask, |
| 335 | .irq_unmask = tegra_gpio_irq_unmask, |
| 336 | .irq_set_type = tegra_gpio_irq_set_type, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 337 | #ifdef CONFIG_PM |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 338 | .irq_set_wake = tegra_gpio_wake_enable, |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 339 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 340 | }; |
| 341 | |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 342 | struct tegra_gpio_soc_config { |
| 343 | u32 bank_stride; |
| 344 | u32 upper_offset; |
| 345 | }; |
| 346 | |
| 347 | static struct tegra_gpio_soc_config tegra20_gpio_config = { |
| 348 | .bank_stride = 0x80, |
| 349 | .upper_offset = 0x800, |
| 350 | }; |
| 351 | |
| 352 | static struct tegra_gpio_soc_config tegra30_gpio_config = { |
| 353 | .bank_stride = 0x100, |
| 354 | .upper_offset = 0x80, |
| 355 | }; |
| 356 | |
| 357 | static struct of_device_id tegra_gpio_of_match[] __devinitdata = { |
| 358 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
| 359 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, |
| 360 | { }, |
| 361 | }; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 362 | |
| 363 | /* This lock class tells lockdep that GPIO irqs are in a different |
| 364 | * category than their parents, so it won't report false recursion. |
| 365 | */ |
| 366 | static struct lock_class_key gpio_lock_class; |
| 367 | |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 368 | static int __devinit tegra_gpio_probe(struct platform_device *pdev) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 369 | { |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 370 | const struct of_device_id *match; |
| 371 | struct tegra_gpio_soc_config *config; |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 372 | int irq_base; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 373 | struct resource *res; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 374 | struct tegra_gpio_bank *bank; |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 375 | int gpio; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 376 | int i; |
| 377 | int j; |
| 378 | |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 379 | match = of_match_device(tegra_gpio_of_match, &pdev->dev); |
| 380 | if (match) |
| 381 | config = (struct tegra_gpio_soc_config *)match->data; |
| 382 | else |
| 383 | config = &tegra20_gpio_config; |
| 384 | |
| 385 | tegra_gpio_bank_stride = config->bank_stride; |
| 386 | tegra_gpio_upper_offset = config->upper_offset; |
| 387 | |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 388 | for (;;) { |
| 389 | res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); |
| 390 | if (!res) |
| 391 | break; |
| 392 | tegra_gpio_bank_count++; |
| 393 | } |
| 394 | if (!tegra_gpio_bank_count) { |
| 395 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
| 396 | return -ENODEV; |
| 397 | } |
| 398 | |
| 399 | tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; |
| 400 | |
| 401 | tegra_gpio_banks = devm_kzalloc(&pdev->dev, |
| 402 | tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), |
| 403 | GFP_KERNEL); |
| 404 | if (!tegra_gpio_banks) { |
| 405 | dev_err(&pdev->dev, "Couldn't allocate bank structure\n"); |
| 406 | return -ENODEV; |
| 407 | } |
| 408 | |
| 409 | irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0); |
| 410 | if (irq_base < 0) { |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 411 | dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n"); |
| 412 | return -ENODEV; |
| 413 | } |
Stephen Warren | bdc93a7 | 2012-02-13 16:21:15 -0700 | [diff] [blame] | 414 | irq_domain = irq_domain_add_legacy(pdev->dev.of_node, |
| 415 | tegra_gpio_chip.ngpio, irq_base, 0, |
| 416 | &irq_domain_simple_ops, NULL); |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 417 | |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 418 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 419 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
| 420 | if (!res) { |
| 421 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
| 422 | return -ENODEV; |
| 423 | } |
| 424 | |
| 425 | bank = &tegra_gpio_banks[i]; |
| 426 | bank->bank = i; |
| 427 | bank->irq = res->start; |
| 428 | } |
| 429 | |
| 430 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 431 | if (!res) { |
| 432 | dev_err(&pdev->dev, "Missing MEM resource\n"); |
| 433 | return -ENODEV; |
| 434 | } |
| 435 | |
Julia Lawall | aedd4fd | 2011-12-27 15:01:26 +0100 | [diff] [blame] | 436 | regs = devm_request_and_ioremap(&pdev->dev, res); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 437 | if (!regs) { |
| 438 | dev_err(&pdev->dev, "Couldn't ioremap regs\n"); |
| 439 | return -ENODEV; |
| 440 | } |
| 441 | |
Stephen Warren | 4a3398e | 2012-03-16 17:37:24 -0600 | [diff] [blame] | 442 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 443 | for (j = 0; j < 4; j++) { |
| 444 | int gpio = tegra_gpio_compose(i, j, 0); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 445 | tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 446 | } |
| 447 | } |
| 448 | |
Grant Likely | df22122 | 2011-06-15 14:54:14 -0600 | [diff] [blame] | 449 | #ifdef CONFIG_OF_GPIO |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 450 | tegra_gpio_chip.of_node = pdev->dev.of_node; |
| 451 | #endif |
Grant Likely | df22122 | 2011-06-15 14:54:14 -0600 | [diff] [blame] | 452 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 453 | gpiochip_add(&tegra_gpio_chip); |
| 454 | |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 455 | for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { |
Stephen Warren | bdc93a7 | 2012-02-13 16:21:15 -0700 | [diff] [blame] | 456 | int irq = irq_find_mapping(irq_domain, gpio); |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 457 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 458 | |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 459 | bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; |
| 460 | |
| 461 | irq_set_lockdep_class(irq, &gpio_lock_class); |
| 462 | irq_set_chip_data(irq, bank); |
| 463 | irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 464 | handle_simple_irq); |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 465 | set_irq_flags(irq, IRQF_VALID); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 466 | } |
| 467 | |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 468 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 469 | bank = &tegra_gpio_banks[i]; |
| 470 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 471 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
| 472 | irq_set_handler_data(bank->irq, bank); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 473 | |
| 474 | for (j = 0; j < 4; j++) |
| 475 | spin_lock_init(&bank->lvl_lock[j]); |
| 476 | } |
| 477 | |
| 478 | return 0; |
| 479 | } |
| 480 | |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 481 | static struct platform_driver tegra_gpio_driver = { |
| 482 | .driver = { |
| 483 | .name = "tegra-gpio", |
| 484 | .owner = THIS_MODULE, |
| 485 | .of_match_table = tegra_gpio_of_match, |
| 486 | }, |
| 487 | .probe = tegra_gpio_probe, |
| 488 | }; |
| 489 | |
| 490 | static int __init tegra_gpio_init(void) |
| 491 | { |
| 492 | return platform_driver_register(&tegra_gpio_driver); |
| 493 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 494 | postcore_initcall(tegra_gpio_init); |
| 495 | |
Stephen Warren | b0092f2 | 2012-03-19 11:36:00 -0600 | [diff] [blame] | 496 | void tegra_gpio_config(struct tegra_gpio_table *table, int num) |
Olof Johansson | 632095e | 2011-02-13 19:12:27 -0800 | [diff] [blame] | 497 | { |
| 498 | int i; |
| 499 | |
| 500 | for (i = 0; i < num; i++) { |
| 501 | int gpio = table[i].gpio; |
| 502 | |
| 503 | if (table[i].enable) |
| 504 | tegra_gpio_enable(gpio); |
| 505 | else |
| 506 | tegra_gpio_disable(gpio); |
| 507 | } |
| 508 | } |
| 509 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 510 | #ifdef CONFIG_DEBUG_FS |
| 511 | |
| 512 | #include <linux/debugfs.h> |
| 513 | #include <linux/seq_file.h> |
| 514 | |
| 515 | static int dbg_gpio_show(struct seq_file *s, void *unused) |
| 516 | { |
| 517 | int i; |
| 518 | int j; |
| 519 | |
Stephen Warren | 4a3398e | 2012-03-16 17:37:24 -0600 | [diff] [blame] | 520 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 521 | for (j = 0; j < 4; j++) { |
| 522 | int gpio = tegra_gpio_compose(i, j, 0); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 523 | seq_printf(s, |
| 524 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", |
| 525 | i, j, |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 526 | tegra_gpio_readl(GPIO_CNF(gpio)), |
| 527 | tegra_gpio_readl(GPIO_OE(gpio)), |
| 528 | tegra_gpio_readl(GPIO_OUT(gpio)), |
| 529 | tegra_gpio_readl(GPIO_IN(gpio)), |
| 530 | tegra_gpio_readl(GPIO_INT_STA(gpio)), |
| 531 | tegra_gpio_readl(GPIO_INT_ENB(gpio)), |
| 532 | tegra_gpio_readl(GPIO_INT_LVL(gpio))); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 533 | } |
| 534 | } |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int dbg_gpio_open(struct inode *inode, struct file *file) |
| 539 | { |
| 540 | return single_open(file, dbg_gpio_show, &inode->i_private); |
| 541 | } |
| 542 | |
| 543 | static const struct file_operations debug_fops = { |
| 544 | .open = dbg_gpio_open, |
| 545 | .read = seq_read, |
| 546 | .llseek = seq_lseek, |
| 547 | .release = single_release, |
| 548 | }; |
| 549 | |
| 550 | static int __init tegra_gpio_debuginit(void) |
| 551 | { |
| 552 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, |
| 553 | NULL, NULL, &debug_fops); |
| 554 | return 0; |
| 555 | } |
| 556 | late_initcall(tegra_gpio_debuginit); |
| 557 | #endif |