Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Texas Instruments DP83867 PHY |
| 3 | * |
| 4 | * Copyright (C) 2015 Texas Instruments Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/ethtool.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/mii.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/phy.h> |
| 22 | |
| 23 | #include <dt-bindings/net/ti-dp83867.h> |
| 24 | |
| 25 | #define DP83867_PHY_ID 0x2000a231 |
| 26 | #define DP83867_DEVADDR 0x1f |
| 27 | |
| 28 | #define MII_DP83867_PHYCTRL 0x10 |
| 29 | #define MII_DP83867_MICR 0x12 |
| 30 | #define MII_DP83867_ISR 0x13 |
| 31 | #define DP83867_CTRL 0x1f |
Grygorii Strashko | 5f7eeee | 2017-01-05 14:48:07 -0600 | [diff] [blame] | 32 | #define DP83867_CFG3 0x1e |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 33 | |
| 34 | /* Extended Registers */ |
| 35 | #define DP83867_RGMIICTL 0x0032 |
| 36 | #define DP83867_RGMIIDCTL 0x0086 |
| 37 | |
| 38 | #define DP83867_SW_RESET BIT(15) |
| 39 | #define DP83867_SW_RESTART BIT(14) |
| 40 | |
| 41 | /* MICR Interrupt bits */ |
| 42 | #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) |
| 43 | #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) |
| 44 | #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) |
| 45 | #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) |
| 46 | #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) |
| 47 | #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) |
| 48 | #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) |
| 49 | #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) |
| 50 | #define MII_DP83867_MICR_WOL_INT_EN BIT(3) |
| 51 | #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) |
| 52 | #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) |
| 53 | #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) |
| 54 | |
| 55 | /* RGMIICTL bits */ |
| 56 | #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) |
| 57 | #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) |
| 58 | |
| 59 | /* PHY CTRL bits */ |
| 60 | #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 |
Stefan Hauser | b291c41 | 2016-07-01 22:35:03 +0200 | [diff] [blame] | 61 | #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 62 | |
| 63 | /* RGMIIDCTL bits */ |
| 64 | #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 |
| 65 | |
| 66 | struct dp83867_private { |
| 67 | int rx_id_delay; |
| 68 | int tx_id_delay; |
| 69 | int fifo_depth; |
| 70 | }; |
| 71 | |
| 72 | static int dp83867_ack_interrupt(struct phy_device *phydev) |
| 73 | { |
| 74 | int err = phy_read(phydev, MII_DP83867_ISR); |
| 75 | |
| 76 | if (err < 0) |
| 77 | return err; |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | static int dp83867_config_intr(struct phy_device *phydev) |
| 83 | { |
| 84 | int micr_status; |
| 85 | |
| 86 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
| 87 | micr_status = phy_read(phydev, MII_DP83867_MICR); |
| 88 | if (micr_status < 0) |
| 89 | return micr_status; |
| 90 | |
| 91 | micr_status |= |
| 92 | (MII_DP83867_MICR_AN_ERR_INT_EN | |
| 93 | MII_DP83867_MICR_SPEED_CHNG_INT_EN | |
Grygorii Strashko | 5f7eeee | 2017-01-05 14:48:07 -0600 | [diff] [blame] | 94 | MII_DP83867_MICR_AUTONEG_COMP_INT_EN | |
| 95 | MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 96 | MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | |
| 97 | MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); |
| 98 | |
| 99 | return phy_write(phydev, MII_DP83867_MICR, micr_status); |
| 100 | } |
| 101 | |
| 102 | micr_status = 0x0; |
| 103 | return phy_write(phydev, MII_DP83867_MICR, micr_status); |
| 104 | } |
| 105 | |
| 106 | #ifdef CONFIG_OF_MDIO |
| 107 | static int dp83867_of_init(struct phy_device *phydev) |
| 108 | { |
| 109 | struct dp83867_private *dp83867 = phydev->priv; |
Andrew Lunn | e5a03bf | 2016-01-06 20:11:16 +0100 | [diff] [blame] | 110 | struct device *dev = &phydev->mdio.dev; |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 111 | struct device_node *of_node = dev->of_node; |
| 112 | int ret; |
| 113 | |
Andrew Lunn | 7bf9ae0 | 2015-12-07 04:38:58 +0100 | [diff] [blame] | 114 | if (!of_node) |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 115 | return -ENODEV; |
| 116 | |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 117 | ret = of_property_read_u32(of_node, "ti,rx-internal-delay", |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 118 | &dp83867->rx_id_delay); |
Karicheri, Muralidharan | 18b200e | 2017-01-13 09:32:34 -0500 | [diff] [blame] | 119 | if (ret && |
| 120 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
| 121 | phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 122 | return ret; |
| 123 | |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 124 | ret = of_property_read_u32(of_node, "ti,tx-internal-delay", |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 125 | &dp83867->tx_id_delay); |
Karicheri, Muralidharan | 18b200e | 2017-01-13 09:32:34 -0500 | [diff] [blame] | 126 | if (ret && |
| 127 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
| 128 | phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 129 | return ret; |
| 130 | |
Wu Fengguang | 9267135 | 2015-07-24 14:16:10 +0800 | [diff] [blame] | 131 | return of_property_read_u32(of_node, "ti,fifo-depth", |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 132 | &dp83867->fifo_depth); |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 133 | } |
| 134 | #else |
| 135 | static int dp83867_of_init(struct phy_device *phydev) |
| 136 | { |
| 137 | return 0; |
| 138 | } |
| 139 | #endif /* CONFIG_OF_MDIO */ |
| 140 | |
| 141 | static int dp83867_config_init(struct phy_device *phydev) |
| 142 | { |
| 143 | struct dp83867_private *dp83867; |
Stefan Hauser | b291c41 | 2016-07-01 22:35:03 +0200 | [diff] [blame] | 144 | int ret, val; |
| 145 | u16 delay; |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 146 | |
| 147 | if (!phydev->priv) { |
Andrew Lunn | e5a03bf | 2016-01-06 20:11:16 +0100 | [diff] [blame] | 148 | dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 149 | GFP_KERNEL); |
| 150 | if (!dp83867) |
| 151 | return -ENOMEM; |
| 152 | |
| 153 | phydev->priv = dp83867; |
| 154 | ret = dp83867_of_init(phydev); |
| 155 | if (ret) |
| 156 | return ret; |
| 157 | } else { |
| 158 | dp83867 = (struct dp83867_private *)phydev->priv; |
| 159 | } |
| 160 | |
| 161 | if (phy_interface_is_rgmii(phydev)) { |
Stefan Hauser | b291c41 | 2016-07-01 22:35:03 +0200 | [diff] [blame] | 162 | val = phy_read(phydev, MII_DP83867_PHYCTRL); |
| 163 | if (val < 0) |
| 164 | return val; |
| 165 | val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; |
| 166 | val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); |
| 167 | ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 168 | if (ret) |
| 169 | return ret; |
| 170 | } |
| 171 | |
Dan Murphy | a46fa26 | 2015-07-21 12:06:45 -0500 | [diff] [blame] | 172 | if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 173 | (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { |
| 174 | val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, |
Andrew Lunn | 053e7e1 | 2016-01-06 20:11:12 +0100 | [diff] [blame] | 175 | DP83867_DEVADDR); |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 176 | |
| 177 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
| 178 | val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); |
| 179 | |
| 180 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
| 181 | val |= DP83867_RGMII_TX_CLK_DELAY_EN; |
| 182 | |
| 183 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 184 | val |= DP83867_RGMII_RX_CLK_DELAY_EN; |
| 185 | |
| 186 | phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, |
Andrew Lunn | 053e7e1 | 2016-01-06 20:11:12 +0100 | [diff] [blame] | 187 | DP83867_DEVADDR, val); |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 188 | |
| 189 | delay = (dp83867->rx_id_delay | |
| 190 | (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); |
| 191 | |
| 192 | phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, |
Andrew Lunn | 053e7e1 | 2016-01-06 20:11:12 +0100 | [diff] [blame] | 193 | DP83867_DEVADDR, delay); |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 194 | } |
| 195 | |
Grygorii Strashko | 5f7eeee | 2017-01-05 14:48:07 -0600 | [diff] [blame] | 196 | /* Enable Interrupt output INT_OE in CFG3 register */ |
| 197 | if (phy_interrupt_is_valid(phydev)) { |
| 198 | val = phy_read(phydev, DP83867_CFG3); |
| 199 | val |= BIT(7); |
| 200 | phy_write(phydev, DP83867_CFG3, val); |
| 201 | } |
| 202 | |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | static int dp83867_phy_reset(struct phy_device *phydev) |
| 207 | { |
| 208 | int err; |
| 209 | |
| 210 | err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); |
| 211 | if (err < 0) |
| 212 | return err; |
| 213 | |
| 214 | return dp83867_config_init(phydev); |
| 215 | } |
| 216 | |
| 217 | static struct phy_driver dp83867_driver[] = { |
| 218 | { |
| 219 | .phy_id = DP83867_PHY_ID, |
| 220 | .phy_id_mask = 0xfffffff0, |
| 221 | .name = "TI DP83867", |
| 222 | .features = PHY_GBIT_FEATURES, |
| 223 | .flags = PHY_HAS_INTERRUPT, |
| 224 | |
| 225 | .config_init = dp83867_config_init, |
| 226 | .soft_reset = dp83867_phy_reset, |
| 227 | |
| 228 | /* IRQ related */ |
| 229 | .ack_interrupt = dp83867_ack_interrupt, |
| 230 | .config_intr = dp83867_config_intr, |
| 231 | |
| 232 | .config_aneg = genphy_config_aneg, |
| 233 | .read_status = genphy_read_status, |
| 234 | .suspend = genphy_suspend, |
| 235 | .resume = genphy_resume, |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 236 | }, |
| 237 | }; |
| 238 | module_phy_driver(dp83867_driver); |
| 239 | |
| 240 | static struct mdio_device_id __maybe_unused dp83867_tbl[] = { |
| 241 | { DP83867_PHY_ID, 0xfffffff0 }, |
| 242 | { } |
| 243 | }; |
| 244 | |
| 245 | MODULE_DEVICE_TABLE(mdio, dp83867_tbl); |
| 246 | |
| 247 | MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); |
| 248 | MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); |
| 249 | MODULE_LICENSE("GPL"); |