blob: 9ed0a8462ccf2983eaa0107e8cf8a4a81dd737b6 [file] [log] [blame]
Honghui Zhang9ca340c2016-06-08 17:50:58 +08001/*
2 * Copyright (c) 2015-2016 MediaTek Inc.
3 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _MTK_IOMMU_H_
16#define _MTK_IOMMU_H_
17
18#include <linux/clk.h>
19#include <linux/component.h>
20#include <linux/device.h>
21#include <linux/io.h>
22#include <linux/iommu.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <soc/mediatek/smi.h>
26
27#include "io-pgtable.h"
28
29struct mtk_iommu_suspend_reg {
30 u32 standard_axi_mode;
31 u32 dcm_dis;
32 u32 ctrl_reg;
33 u32 int_control0;
34 u32 int_main_control;
35};
36
37struct mtk_iommu_client_priv {
38 struct list_head client;
39 unsigned int mtk_m4u_id;
40 struct device *m4udev;
41};
42
43struct mtk_iommu_domain;
44
45struct mtk_iommu_data {
46 void __iomem *base;
47 int irq;
48 struct device *dev;
49 struct clk *bclk;
50 phys_addr_t protect_base; /* protect memory base */
51 struct mtk_iommu_suspend_reg reg;
52 struct mtk_iommu_domain *m4u_dom;
53 struct iommu_group *m4u_group;
54 struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
55 bool enable_4GB;
56};
57
58static int compare_of(struct device *dev, void *data)
59{
60 return dev->of_node == data;
61}
62
63static int mtk_iommu_bind(struct device *dev)
64{
65 struct mtk_iommu_data *data = dev_get_drvdata(dev);
66
67 return component_bind_all(dev, &data->smi_imu);
68}
69
70static void mtk_iommu_unbind(struct device *dev)
71{
72 struct mtk_iommu_data *data = dev_get_drvdata(dev);
73
74 component_unbind_all(dev, &data->smi_imu);
75}
76
77#endif