| Kim Phillips | 9c4a796 | 2008-06-23 19:50:15 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale SEC (talitos) device register and descriptor header defines |
| 3 | * |
| 4 | * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The name of the author may not be used to endorse or promote products |
| 16 | * derived from this software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /* |
| 32 | * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register |
| 33 | */ |
| 34 | |
| 35 | /* global register offset addresses */ |
| 36 | #define TALITOS_MCR 0x1030 /* master control register */ |
| 37 | #define TALITOS_MCR_LO 0x1038 |
| 38 | #define TALITOS_MCR_SWR 0x1 /* s/w reset */ |
| 39 | #define TALITOS_IMR 0x1008 /* interrupt mask register */ |
| 40 | #define TALITOS_IMR_INIT 0x10fff /* enable channel IRQs */ |
| 41 | #define TALITOS_IMR_LO 0x100C |
| 42 | #define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */ |
| 43 | #define TALITOS_ISR 0x1010 /* interrupt status register */ |
| 44 | #define TALITOS_ISR_CHERR 0xaa /* channel errors mask */ |
| 45 | #define TALITOS_ISR_CHDONE 0x55 /* channel done mask */ |
| 46 | #define TALITOS_ISR_LO 0x1014 |
| 47 | #define TALITOS_ICR 0x1018 /* interrupt clear register */ |
| 48 | #define TALITOS_ICR_LO 0x101C |
| 49 | |
| 50 | /* channel register address stride */ |
| 51 | #define TALITOS_CH_STRIDE 0x100 |
| 52 | |
| 53 | /* channel configuration register */ |
| 54 | #define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x1108) |
| 55 | #define TALITOS_CCCR_CONT 0x2 /* channel continue */ |
| 56 | #define TALITOS_CCCR_RESET 0x1 /* channel reset */ |
| 57 | #define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c) |
| 58 | #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */ |
| 59 | #define TALITOS_CCCR_LO_NT 0x4 /* notification type */ |
| 60 | #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */ |
| 61 | |
| 62 | /* CCPSR: channel pointer status register */ |
| 63 | #define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x1110) |
| 64 | #define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1114) |
| 65 | #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */ |
| 66 | #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */ |
| 67 | #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */ |
| 68 | #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */ |
| 69 | #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */ |
| 70 | #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */ |
| 71 | #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */ |
| 72 | #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */ |
| 73 | #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */ |
| 74 | #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */ |
| 75 | #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */ |
| 76 | #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */ |
| 77 | |
| 78 | /* channel fetch fifo register */ |
| 79 | #define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x1148) |
| 80 | #define TALITOS_FF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x114c) |
| 81 | |
| 82 | /* current descriptor pointer register */ |
| 83 | #define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x1140) |
| 84 | #define TALITOS_CDPR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1144) |
| 85 | |
| 86 | /* descriptor buffer register */ |
| 87 | #define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x1180) |
| 88 | #define TALITOS_DESCBUF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1184) |
| 89 | |
| 90 | /* gather link table */ |
| 91 | #define TALITOS_GATHER(ch) (ch * TALITOS_CH_STRIDE + 0x11c0) |
| 92 | #define TALITOS_GATHER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11c4) |
| 93 | |
| 94 | /* scatter link table */ |
| 95 | #define TALITOS_SCATTER(ch) (ch * TALITOS_CH_STRIDE + 0x11e0) |
| 96 | #define TALITOS_SCATTER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11e4) |
| 97 | |
| 98 | /* execution unit interrupt status registers */ |
| 99 | #define TALITOS_DEUISR 0x2030 /* DES unit */ |
| 100 | #define TALITOS_DEUISR_LO 0x2034 |
| 101 | #define TALITOS_AESUISR 0x4030 /* AES unit */ |
| 102 | #define TALITOS_AESUISR_LO 0x4034 |
| 103 | #define TALITOS_MDEUISR 0x6030 /* message digest unit */ |
| 104 | #define TALITOS_MDEUISR_LO 0x6034 |
| 105 | #define TALITOS_AFEUISR 0x8030 /* arc4 unit */ |
| 106 | #define TALITOS_AFEUISR_LO 0x8034 |
| 107 | #define TALITOS_RNGUISR 0xa030 /* random number unit */ |
| 108 | #define TALITOS_RNGUISR_LO 0xa034 |
| 109 | #define TALITOS_RNGUSR 0xa028 /* rng status */ |
| 110 | #define TALITOS_RNGUSR_LO 0xa02c |
| 111 | #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */ |
| 112 | #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */ |
| 113 | #define TALITOS_RNGUDSR 0xa010 /* data size */ |
| 114 | #define TALITOS_RNGUDSR_LO 0xa014 |
| 115 | #define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */ |
| 116 | #define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */ |
| 117 | #define TALITOS_RNGURCR 0xa018 /* reset control */ |
| 118 | #define TALITOS_RNGURCR_LO 0xa01c |
| 119 | #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */ |
| 120 | #define TALITOS_PKEUISR 0xc030 /* public key unit */ |
| 121 | #define TALITOS_PKEUISR_LO 0xc034 |
| 122 | #define TALITOS_KEUISR 0xe030 /* kasumi unit */ |
| 123 | #define TALITOS_KEUISR_LO 0xe034 |
| 124 | #define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/ |
| 125 | #define TALITOS_CRCUISR_LO 0xf034 |
| 126 | |
| 127 | /* |
| 128 | * talitos descriptor header (hdr) bits |
| 129 | */ |
| 130 | |
| 131 | /* written back when done */ |
| 132 | #define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000) |
| 133 | |
| 134 | /* primary execution unit select */ |
| 135 | #define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000) |
| 136 | #define DESC_HDR_SEL0_AFEU __constant_cpu_to_be32(0x10000000) |
| 137 | #define DESC_HDR_SEL0_DEU __constant_cpu_to_be32(0x20000000) |
| 138 | #define DESC_HDR_SEL0_MDEUA __constant_cpu_to_be32(0x30000000) |
| 139 | #define DESC_HDR_SEL0_MDEUB __constant_cpu_to_be32(0xb0000000) |
| 140 | #define DESC_HDR_SEL0_RNG __constant_cpu_to_be32(0x40000000) |
| 141 | #define DESC_HDR_SEL0_PKEU __constant_cpu_to_be32(0x50000000) |
| 142 | #define DESC_HDR_SEL0_AESU __constant_cpu_to_be32(0x60000000) |
| 143 | #define DESC_HDR_SEL0_KEU __constant_cpu_to_be32(0x70000000) |
| 144 | #define DESC_HDR_SEL0_CRCU __constant_cpu_to_be32(0x80000000) |
| 145 | |
| 146 | /* primary execution unit mode (MODE0) and derivatives */ |
| 147 | #define DESC_HDR_MODE0_AESU_CBC __constant_cpu_to_be32(0x00200000) |
| 148 | #define DESC_HDR_MODE0_AESU_ENC __constant_cpu_to_be32(0x00100000) |
| 149 | #define DESC_HDR_MODE0_DEU_CBC __constant_cpu_to_be32(0x00400000) |
| 150 | #define DESC_HDR_MODE0_DEU_3DES __constant_cpu_to_be32(0x00200000) |
| 151 | #define DESC_HDR_MODE0_DEU_ENC __constant_cpu_to_be32(0x00100000) |
| 152 | #define DESC_HDR_MODE0_MDEU_INIT __constant_cpu_to_be32(0x01000000) |
| 153 | #define DESC_HDR_MODE0_MDEU_HMAC __constant_cpu_to_be32(0x00800000) |
| 154 | #define DESC_HDR_MODE0_MDEU_PAD __constant_cpu_to_be32(0x00400000) |
| 155 | #define DESC_HDR_MODE0_MDEU_MD5 __constant_cpu_to_be32(0x00200000) |
| 156 | #define DESC_HDR_MODE0_MDEU_SHA256 __constant_cpu_to_be32(0x00100000) |
| 157 | #define DESC_HDR_MODE0_MDEU_SHA1 __constant_cpu_to_be32(0x00000000) |
| 158 | #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \ |
| 159 | DESC_HDR_MODE0_MDEU_HMAC) |
| 160 | #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \ |
| 161 | DESC_HDR_MODE0_MDEU_HMAC) |
| 162 | #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \ |
| 163 | DESC_HDR_MODE0_MDEU_HMAC) |
| 164 | |
| 165 | /* secondary execution unit select (SEL1) */ |
| 166 | #define DESC_HDR_SEL1_MASK __constant_cpu_to_be32(0x000f0000) |
| 167 | #define DESC_HDR_SEL1_MDEUA __constant_cpu_to_be32(0x00030000) |
| 168 | #define DESC_HDR_SEL1_MDEUB __constant_cpu_to_be32(0x000b0000) |
| 169 | #define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000) |
| 170 | |
| 171 | /* secondary execution unit mode (MODE1) and derivatives */ |
| 172 | #define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000) |
| 173 | #define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800) |
| 174 | #define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400) |
| 175 | #define DESC_HDR_MODE1_MDEU_MD5 __constant_cpu_to_be32(0x00000200) |
| 176 | #define DESC_HDR_MODE1_MDEU_SHA256 __constant_cpu_to_be32(0x00000100) |
| 177 | #define DESC_HDR_MODE1_MDEU_SHA1 __constant_cpu_to_be32(0x00000000) |
| 178 | #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \ |
| 179 | DESC_HDR_MODE1_MDEU_HMAC) |
| 180 | #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \ |
| 181 | DESC_HDR_MODE1_MDEU_HMAC) |
| 182 | #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \ |
| 183 | DESC_HDR_MODE1_MDEU_HMAC) |
| 184 | |
| 185 | /* direction of overall data flow (DIR) */ |
| 186 | #define DESC_HDR_DIR_INBOUND __constant_cpu_to_be32(0x00000002) |
| 187 | |
| 188 | /* request done notification (DN) */ |
| 189 | #define DESC_HDR_DONE_NOTIFY __constant_cpu_to_be32(0x00000001) |
| 190 | |
| 191 | /* descriptor types */ |
| 192 | #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP __constant_cpu_to_be32(0 << 3) |
| 193 | #define DESC_HDR_TYPE_IPSEC_ESP __constant_cpu_to_be32(1 << 3) |
| 194 | #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU __constant_cpu_to_be32(2 << 3) |
| 195 | #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU __constant_cpu_to_be32(4 << 3) |
| 196 | |
| 197 | /* link table extent field bits */ |
| 198 | #define DESC_PTR_LNKTBL_JUMP 0x80 |
| 199 | #define DESC_PTR_LNKTBL_RETURN 0x02 |
| 200 | #define DESC_PTR_LNKTBL_NEXT 0x01 |