blob: 27b818dee7c7f85b5aa730d4db81b9fa4f231782 [file] [log] [blame]
Linus Walleij8d318a52010-03-30 15:33:42 +02001/*
Jonas Aaberg767a9672010-08-09 12:08:34 +00002 * Copyright (C) ST-Ericsson SA 2007-2010
Per Forlind49278e2010-12-20 18:31:38 +01003 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
Jonas Aaberg767a9672010-08-09 12:08:34 +00004 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
Linus Walleij8d318a52010-03-30 15:33:42 +02005 * License terms: GNU General Public License (GPL) version 2
Linus Walleij8d318a52010-03-30 15:33:42 +02006 */
7
8#include <linux/kernel.h>
Linus Walleij865fab62012-10-18 14:20:16 +02009#include <linux/platform_data/dma-ste-dma40.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020010
11#include "ste_dma40_ll.h"
12
Lee Jones43f2e1a2013-05-15 11:51:57 +020013u8 d40_width_to_bits(enum dma_slave_buswidth width)
14{
15 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
16 return STEDMA40_ESIZE_8_BIT;
17 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
18 return STEDMA40_ESIZE_16_BIT;
19 else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
20 return STEDMA40_ESIZE_64_BIT;
21 else
22 return STEDMA40_ESIZE_32_BIT;
23}
24
Linus Walleij8d318a52010-03-30 15:33:42 +020025/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
26void d40_log_cfg(struct stedma40_chan_cfg *cfg,
27 u32 *lcsp1, u32 *lcsp3)
28{
29 u32 l3 = 0; /* dst */
30 u32 l1 = 0; /* src */
31
32 /* src is mem? -> increase address pos */
Lee Jones2c2b62d2013-05-15 10:51:54 +010033 if (cfg->dir == DMA_MEM_TO_DEV ||
34 cfg->dir == DMA_MEM_TO_MEM)
Lee Jones16db3412013-05-15 10:51:56 +010035 l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020036
37 /* dst is mem? -> increase address pos */
Lee Jones2c2b62d2013-05-15 10:51:54 +010038 if (cfg->dir == DMA_DEV_TO_MEM ||
39 cfg->dir == DMA_MEM_TO_MEM)
Lee Jones16db3412013-05-15 10:51:56 +010040 l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020041
42 /* src is hw? -> master port 1 */
Lee Jones2c2b62d2013-05-15 10:51:54 +010043 if (cfg->dir == DMA_DEV_TO_MEM ||
44 cfg->dir == DMA_DEV_TO_DEV)
Lee Jones16db3412013-05-15 10:51:56 +010045 l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020046
47 /* dst is hw? -> master port 1 */
Lee Jones2c2b62d2013-05-15 10:51:54 +010048 if (cfg->dir == DMA_MEM_TO_DEV ||
49 cfg->dir == DMA_DEV_TO_DEV)
Lee Jones16db3412013-05-15 10:51:56 +010050 l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020051
Lee Jones16db3412013-05-15 10:51:56 +010052 l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020053 l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
Lee Jones43f2e1a2013-05-15 11:51:57 +020054 l3 |= d40_width_to_bits(cfg->dst_info.data_width)
55 << D40_MEM_LCSP3_DCFG_ESIZE_POS;
Linus Walleij8d318a52010-03-30 15:33:42 +020056
Lee Jones16db3412013-05-15 10:51:56 +010057 l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020058 l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
Lee Jones43f2e1a2013-05-15 11:51:57 +020059 l1 |= d40_width_to_bits(cfg->src_info.data_width)
60 << D40_MEM_LCSP1_SCFG_ESIZE_POS;
Linus Walleij8d318a52010-03-30 15:33:42 +020061
62 *lcsp1 = l1;
63 *lcsp3 = l3;
64
65}
66
Lee Jones57e65ad2013-05-15 10:51:25 +010067void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
Linus Walleij8d318a52010-03-30 15:33:42 +020068{
69 u32 src = 0;
70 u32 dst = 0;
71
Lee Jones2c2b62d2013-05-15 10:51:54 +010072 if ((cfg->dir == DMA_DEV_TO_MEM) ||
73 (cfg->dir == DMA_DEV_TO_DEV)) {
Lee Jones57e65ad2013-05-15 10:51:25 +010074 /* Set master port to 1 */
Lee Jones16db3412013-05-15 10:51:56 +010075 src |= BIT(D40_SREG_CFG_MST_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +010076 src |= D40_TYPE_TO_EVENT(cfg->dev_type);
Linus Walleij8d318a52010-03-30 15:33:42 +020077
Lee Jones57e65ad2013-05-15 10:51:25 +010078 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
Lee Jones16db3412013-05-15 10:51:56 +010079 src |= BIT(D40_SREG_CFG_PHY_TM_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +010080 else
81 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
82 }
Lee Jones2c2b62d2013-05-15 10:51:54 +010083 if ((cfg->dir == DMA_MEM_TO_DEV) ||
84 (cfg->dir == DMA_DEV_TO_DEV)) {
Lee Jones57e65ad2013-05-15 10:51:25 +010085 /* Set master port to 1 */
Lee Jones16db3412013-05-15 10:51:56 +010086 dst |= BIT(D40_SREG_CFG_MST_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +010087 dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
Linus Walleij8d318a52010-03-30 15:33:42 +020088
Lee Jones57e65ad2013-05-15 10:51:25 +010089 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
Lee Jones16db3412013-05-15 10:51:56 +010090 dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +010091 else
92 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
93 }
94 /* Interrupt on end of transfer for destination */
Lee Jones16db3412013-05-15 10:51:56 +010095 dst |= BIT(D40_SREG_CFG_TIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +020096
Lee Jones57e65ad2013-05-15 10:51:25 +010097 /* Generate interrupt on error */
Lee Jones16db3412013-05-15 10:51:56 +010098 src |= BIT(D40_SREG_CFG_EIM_POS);
99 dst |= BIT(D40_SREG_CFG_EIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200100
Lee Jones57e65ad2013-05-15 10:51:25 +0100101 /* PSIZE */
102 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
Lee Jones16db3412013-05-15 10:51:56 +0100103 src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +0100104 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
105 }
106 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
Lee Jones16db3412013-05-15 10:51:56 +0100107 dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
Lee Jones57e65ad2013-05-15 10:51:25 +0100108 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
109 }
Linus Walleij8d318a52010-03-30 15:33:42 +0200110
Lee Jones57e65ad2013-05-15 10:51:25 +0100111 /* Element size */
Lee Jones43f2e1a2013-05-15 11:51:57 +0200112 src |= d40_width_to_bits(cfg->src_info.data_width)
113 << D40_SREG_CFG_ESIZE_POS;
114 dst |= d40_width_to_bits(cfg->dst_info.data_width)
115 << D40_SREG_CFG_ESIZE_POS;
Linus Walleij8d318a52010-03-30 15:33:42 +0200116
Lee Jones57e65ad2013-05-15 10:51:25 +0100117 /* Set the priority bit to high for the physical channel */
118 if (cfg->high_priority) {
Lee Jones16db3412013-05-15 10:51:56 +0100119 src |= BIT(D40_SREG_CFG_PRI_POS);
120 dst |= BIT(D40_SREG_CFG_PRI_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200121 }
122
Rabin Vincent51f5d742010-10-12 13:00:54 +0000123 if (cfg->src_info.big_endian)
Lee Jones16db3412013-05-15 10:51:56 +0100124 src |= BIT(D40_SREG_CFG_LBE_POS);
Rabin Vincent51f5d742010-10-12 13:00:54 +0000125 if (cfg->dst_info.big_endian)
Lee Jones16db3412013-05-15 10:51:56 +0100126 dst |= BIT(D40_SREG_CFG_LBE_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200127
128 *src_cfg = src;
129 *dst_cfg = dst;
130}
131
Per Forlind49278e2010-12-20 18:31:38 +0100132static int d40_phy_fill_lli(struct d40_phy_lli *lli,
133 dma_addr_t data,
134 u32 data_size,
Per Forlind49278e2010-12-20 18:31:38 +0100135 dma_addr_t next_lli,
136 u32 reg_cfg,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100137 struct stedma40_half_channel_info *info,
138 unsigned int flags)
Linus Walleij8d318a52010-03-30 15:33:42 +0200139{
Rabin Vincent7f933be2011-01-25 11:18:30 +0100140 bool addr_inc = flags & LLI_ADDR_INC;
141 bool term_int = flags & LLI_TERM_INT;
Rabin Vincentcc31b6f2011-01-25 11:18:27 +0100142 unsigned int data_width = info->data_width;
143 int psize = info->psize;
Linus Walleij8d318a52010-03-30 15:33:42 +0200144 int num_elems;
145
146 if (psize == STEDMA40_PSIZE_PHY_1)
147 num_elems = 1;
148 else
149 num_elems = 2 << psize;
150
Linus Walleij8d318a52010-03-30 15:33:42 +0200151 /* Must be aligned */
Lee Jones43f2e1a2013-05-15 11:51:57 +0200152 if (!IS_ALIGNED(data, data_width))
Linus Walleij8d318a52010-03-30 15:33:42 +0200153 return -EINVAL;
154
155 /* Transfer size can't be smaller than (num_elms * elem_size) */
Lee Jones43f2e1a2013-05-15 11:51:57 +0200156 if (data_size < num_elems * data_width)
Linus Walleij8d318a52010-03-30 15:33:42 +0200157 return -EINVAL;
158
159 /* The number of elements. IE now many chunks */
Lee Jones43f2e1a2013-05-15 11:51:57 +0200160 lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
Linus Walleij8d318a52010-03-30 15:33:42 +0200161
162 /*
163 * Distance to next element sized entry.
164 * Usually the size of the element unless you want gaps.
165 */
Rabin Vincent7f933be2011-01-25 11:18:30 +0100166 if (addr_inc)
Lee Jones43f2e1a2013-05-15 11:51:57 +0200167 lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
Linus Walleij8d318a52010-03-30 15:33:42 +0200168
169 /* Where the data is */
170 lli->reg_ptr = data;
171 lli->reg_cfg = reg_cfg;
172
173 /* If this scatter list entry is the last one, no next link */
174 if (next_lli == 0)
Lee Jones16db3412013-05-15 10:51:56 +0100175 lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200176 else
177 lli->reg_lnk = next_lli;
178
179 /* Set/clear interrupt generation on this link item.*/
180 if (term_int)
Lee Jones16db3412013-05-15 10:51:56 +0100181 lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200182 else
Lee Jones16db3412013-05-15 10:51:56 +0100183 lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
Linus Walleij8d318a52010-03-30 15:33:42 +0200184
Lee Jones8cc5af12013-05-15 10:51:58 +0100185 /*
186 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
187 * Relink happens after transfer completion.
188 */
Linus Walleij8d318a52010-03-30 15:33:42 +0200189
190 return 0;
191}
192
Per Forlind49278e2010-12-20 18:31:38 +0100193static int d40_seg_size(int size, int data_width1, int data_width2)
194{
195 u32 max_w = max(data_width1, data_width2);
196 u32 min_w = min(data_width1, data_width2);
Lee Jones43f2e1a2013-05-15 11:51:57 +0200197 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
Per Forlind49278e2010-12-20 18:31:38 +0100198
199 if (seg_max > STEDMA40_MAX_SEG_SIZE)
Lee Jones43f2e1a2013-05-15 11:51:57 +0200200 seg_max -= max_w;
Per Forlind49278e2010-12-20 18:31:38 +0100201
202 if (size <= seg_max)
203 return size;
204
205 if (size <= 2 * seg_max)
Lee Jones43f2e1a2013-05-15 11:51:57 +0200206 return ALIGN(size / 2, max_w);
Per Forlind49278e2010-12-20 18:31:38 +0100207
208 return seg_max;
209}
210
Rabin Vincentcc31b6f2011-01-25 11:18:27 +0100211static struct d40_phy_lli *
212d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100213 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100214 struct stedma40_half_channel_info *info,
215 struct stedma40_half_channel_info *otherinfo,
216 unsigned long flags)
Per Forlind49278e2010-12-20 18:31:38 +0100217{
Rabin Vincent0c842b52011-01-25 11:18:35 +0100218 bool lastlink = flags & LLI_LAST_LINK;
Rabin Vincent7f933be2011-01-25 11:18:30 +0100219 bool addr_inc = flags & LLI_ADDR_INC;
220 bool term_int = flags & LLI_TERM_INT;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100221 bool cyclic = flags & LLI_CYCLIC;
Per Forlind49278e2010-12-20 18:31:38 +0100222 int err;
223 dma_addr_t next = lli_phys;
224 int size_rest = size;
225 int size_seg = 0;
226
Rabin Vincent7f933be2011-01-25 11:18:30 +0100227 /*
228 * This piece may be split up based on d40_seg_size(); we only want the
229 * term int on the last part.
230 */
231 if (term_int)
232 flags &= ~LLI_TERM_INT;
233
Per Forlind49278e2010-12-20 18:31:38 +0100234 do {
Rabin Vincentcc31b6f2011-01-25 11:18:27 +0100235 size_seg = d40_seg_size(size_rest, info->data_width,
236 otherinfo->data_width);
Per Forlind49278e2010-12-20 18:31:38 +0100237 size_rest -= size_seg;
238
Rabin Vincent0c842b52011-01-25 11:18:35 +0100239 if (size_rest == 0 && term_int)
Rabin Vincent7f933be2011-01-25 11:18:30 +0100240 flags |= LLI_TERM_INT;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100241
242 if (size_rest == 0 && lastlink)
243 next = cyclic ? first_phys : 0;
244 else
Per Forlind49278e2010-12-20 18:31:38 +0100245 next = ALIGN(next + sizeof(struct d40_phy_lli),
246 D40_LLI_ALIGN);
247
Rabin Vincent7f933be2011-01-25 11:18:30 +0100248 err = d40_phy_fill_lli(lli, addr, size_seg, next,
249 reg_cfg, info, flags);
Per Forlind49278e2010-12-20 18:31:38 +0100250
251 if (err)
252 goto err;
253
254 lli++;
Rabin Vincent7f933be2011-01-25 11:18:30 +0100255 if (addr_inc)
Per Forlind49278e2010-12-20 18:31:38 +0100256 addr += size_seg;
257 } while (size_rest);
258
259 return lli;
260
Fabio Baltierif26e03a2012-12-13 17:12:37 +0100261err:
Per Forlind49278e2010-12-20 18:31:38 +0100262 return NULL;
263}
264
Linus Walleij8d318a52010-03-30 15:33:42 +0200265int d40_phy_sg_to_lli(struct scatterlist *sg,
266 int sg_len,
267 dma_addr_t target,
Per Forlind49278e2010-12-20 18:31:38 +0100268 struct d40_phy_lli *lli_sg,
Linus Walleij8d318a52010-03-30 15:33:42 +0200269 dma_addr_t lli_phys,
270 u32 reg_cfg,
Rabin Vincentcc31b6f2011-01-25 11:18:27 +0100271 struct stedma40_half_channel_info *info,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100272 struct stedma40_half_channel_info *otherinfo,
273 unsigned long flags)
Linus Walleij8d318a52010-03-30 15:33:42 +0200274{
275 int total_size = 0;
276 int i;
277 struct scatterlist *current_sg = sg;
Per Forlind49278e2010-12-20 18:31:38 +0100278 struct d40_phy_lli *lli = lli_sg;
279 dma_addr_t l_phys = lli_phys;
Rabin Vincent7f933be2011-01-25 11:18:30 +0100280
281 if (!target)
282 flags |= LLI_ADDR_INC;
Linus Walleij8d318a52010-03-30 15:33:42 +0200283
284 for_each_sg(sg, current_sg, sg_len, i) {
Rabin Vincent7f933be2011-01-25 11:18:30 +0100285 dma_addr_t sg_addr = sg_dma_address(current_sg);
286 unsigned int len = sg_dma_len(current_sg);
287 dma_addr_t dst = target ?: sg_addr;
Linus Walleij8d318a52010-03-30 15:33:42 +0200288
289 total_size += sg_dma_len(current_sg);
290
Rabin Vincent7f933be2011-01-25 11:18:30 +0100291 if (i == sg_len - 1)
Rabin Vincent0c842b52011-01-25 11:18:35 +0100292 flags |= LLI_TERM_INT | LLI_LAST_LINK;
Linus Walleij8d318a52010-03-30 15:33:42 +0200293
Per Forlind49278e2010-12-20 18:31:38 +0100294 l_phys = ALIGN(lli_phys + (lli - lli_sg) *
295 sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
296
Rabin Vincent0c842b52011-01-25 11:18:35 +0100297 lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100298 reg_cfg, info, otherinfo, flags);
299
Per Forlind49278e2010-12-20 18:31:38 +0100300 if (lli == NULL)
301 return -EINVAL;
Linus Walleij8d318a52010-03-30 15:33:42 +0200302 }
303
304 return total_size;
Linus Walleij8d318a52010-03-30 15:33:42 +0200305}
306
307
Linus Walleij8d318a52010-03-30 15:33:42 +0200308/* DMA logical lli operations */
309
Jonas Aaberg698e4732010-08-09 12:08:56 +0000310static void d40_log_lli_link(struct d40_log_lli *lli_dst,
311 struct d40_log_lli *lli_src,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100312 int next, unsigned int flags)
Jonas Aaberg698e4732010-08-09 12:08:56 +0000313{
Rabin Vincent0c842b52011-01-25 11:18:35 +0100314 bool interrupt = flags & LLI_TERM_INT;
Jonas Aaberg698e4732010-08-09 12:08:56 +0000315 u32 slos = 0;
316 u32 dlos = 0;
317
318 if (next != -EINVAL) {
319 slos = next * 2;
320 dlos = next * 2 + 1;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100321 }
322
323 if (interrupt) {
Jonas Aaberg698e4732010-08-09 12:08:56 +0000324 lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
325 lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
326 }
327
328 lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
329 (slos << D40_MEM_LCSP1_SLOS_POS);
330
331 lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
332 (dlos << D40_MEM_LCSP1_SLOS_POS);
333}
334
335void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
336 struct d40_log_lli *lli_dst,
337 struct d40_log_lli *lli_src,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100338 int next, unsigned int flags)
Jonas Aaberg698e4732010-08-09 12:08:56 +0000339{
Rabin Vincent0c842b52011-01-25 11:18:35 +0100340 d40_log_lli_link(lli_dst, lli_src, next, flags);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000341
Per Forlin8a5d2032011-09-28 09:32:20 +0200342 writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
343 writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
344 writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
345 writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000346}
347
348void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
349 struct d40_log_lli *lli_dst,
350 struct d40_log_lli *lli_src,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100351 int next, unsigned int flags)
Jonas Aaberg698e4732010-08-09 12:08:56 +0000352{
Rabin Vincent0c842b52011-01-25 11:18:35 +0100353 d40_log_lli_link(lli_dst, lli_src, next, flags);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000354
Per Forlin8a5d2032011-09-28 09:32:20 +0200355 writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
356 writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
357 writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
358 writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000359}
360
Per Forlind49278e2010-12-20 18:31:38 +0100361static void d40_log_fill_lli(struct d40_log_lli *lli,
362 dma_addr_t data, u32 data_size,
363 u32 reg_cfg,
364 u32 data_width,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100365 unsigned int flags)
Linus Walleij8d318a52010-03-30 15:33:42 +0200366{
Rabin Vincent7f933be2011-01-25 11:18:30 +0100367 bool addr_inc = flags & LLI_ADDR_INC;
368
Linus Walleij8d318a52010-03-30 15:33:42 +0200369 lli->lcsp13 = reg_cfg;
370
371 /* The number of elements to transfer */
Lee Jones43f2e1a2013-05-15 11:51:57 +0200372 lli->lcsp02 = ((data_size / data_width) <<
Linus Walleij8d318a52010-03-30 15:33:42 +0200373 D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
Per Forlind49278e2010-12-20 18:31:38 +0100374
Lee Jones43f2e1a2013-05-15 11:51:57 +0200375 BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
Per Forlind49278e2010-12-20 18:31:38 +0100376
Linus Walleij8d318a52010-03-30 15:33:42 +0200377 /* 16 LSBs address of the current element */
378 lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
379 /* 16 MSBs address of the current element */
380 lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
381
382 if (addr_inc)
383 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
384
Linus Walleij8d318a52010-03-30 15:33:42 +0200385}
386
Rabin Vincent1f7622c2011-01-25 11:18:29 +0100387static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
Per Forlind49278e2010-12-20 18:31:38 +0100388 dma_addr_t addr,
389 int size,
390 u32 lcsp13, /* src or dst*/
391 u32 data_width1,
392 u32 data_width2,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100393 unsigned int flags)
Per Forlind49278e2010-12-20 18:31:38 +0100394{
Rabin Vincent7f933be2011-01-25 11:18:30 +0100395 bool addr_inc = flags & LLI_ADDR_INC;
Per Forlind49278e2010-12-20 18:31:38 +0100396 struct d40_log_lli *lli = lli_sg;
397 int size_rest = size;
398 int size_seg = 0;
399
400 do {
401 size_seg = d40_seg_size(size_rest, data_width1, data_width2);
402 size_rest -= size_seg;
403
404 d40_log_fill_lli(lli,
405 addr,
406 size_seg,
407 lcsp13, data_width1,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100408 flags);
Per Forlind49278e2010-12-20 18:31:38 +0100409 if (addr_inc)
410 addr += size_seg;
411 lli++;
412 } while (size_rest);
413
414 return lli;
415}
416
Jonas Aaberg698e4732010-08-09 12:08:56 +0000417int d40_log_sg_to_lli(struct scatterlist *sg,
Linus Walleij8d318a52010-03-30 15:33:42 +0200418 int sg_len,
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100419 dma_addr_t dev_addr,
Linus Walleij8d318a52010-03-30 15:33:42 +0200420 struct d40_log_lli *lli_sg,
421 u32 lcsp13, /* src or dst*/
Per Forlind49278e2010-12-20 18:31:38 +0100422 u32 data_width1, u32 data_width2)
Linus Walleij8d318a52010-03-30 15:33:42 +0200423{
424 int total_size = 0;
425 struct scatterlist *current_sg = sg;
426 int i;
Per Forlind49278e2010-12-20 18:31:38 +0100427 struct d40_log_lli *lli = lli_sg;
Rabin Vincent7f933be2011-01-25 11:18:30 +0100428 unsigned long flags = 0;
429
430 if (!dev_addr)
431 flags |= LLI_ADDR_INC;
Linus Walleij8d318a52010-03-30 15:33:42 +0200432
433 for_each_sg(sg, current_sg, sg_len, i) {
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100434 dma_addr_t sg_addr = sg_dma_address(current_sg);
435 unsigned int len = sg_dma_len(current_sg);
436 dma_addr_t addr = dev_addr ?: sg_addr;
437
Linus Walleij8d318a52010-03-30 15:33:42 +0200438 total_size += sg_dma_len(current_sg);
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100439
440 lli = d40_log_buf_to_lli(lli, addr, len,
Per Forlind49278e2010-12-20 18:31:38 +0100441 lcsp13,
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100442 data_width1,
443 data_width2,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100444 flags);
Linus Walleij8d318a52010-03-30 15:33:42 +0200445 }
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100446
Linus Walleij8d318a52010-03-30 15:33:42 +0200447 return total_size;
448}