blob: 6038503ed929cc5c9332e7f4903412cf2d1d3611 [file] [log] [blame]
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
Thomas Abraham8dc35682013-03-27 00:12:33 +090023#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +090026#include "core.h"
27
28/* EXYNOS5440 GPIO and Pinctrl register offsets */
29#define GPIO_MUX 0x00
30#define GPIO_IE 0x04
31#define GPIO_INT 0x08
32#define GPIO_TYPE 0x0C
33#define GPIO_VAL 0x10
34#define GPIO_OE 0x14
35#define GPIO_IN 0x18
36#define GPIO_PE 0x1C
37#define GPIO_PS 0x20
38#define GPIO_SR 0x24
39#define GPIO_DS0 0x28
40#define GPIO_DS1 0x2C
41
42#define EXYNOS5440_MAX_PINS 23
Thomas Abraham8dc35682013-03-27 00:12:33 +090043#define EXYNOS5440_MAX_GPIO_INT 8
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +090044#define PIN_NAME_LENGTH 10
45
46#define GROUP_SUFFIX "-grp"
47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
48#define FUNCTION_SUFFIX "-mux"
49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
50
51/*
52 * pin configuration type and its value are packed together into a 16-bits.
53 * The upper 8-bits represent the configuration type and the lower 8-bits
54 * hold the value of the configuration type.
55 */
56#define PINCFG_TYPE_MASK 0xFF
57#define PINCFG_VALUE_SHIFT 8
58#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
59#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
60#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
61#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
62 PINCFG_VALUE_SHIFT)
63
64/**
65 * enum pincfg_type - possible pin configuration types supported.
66 * @PINCFG_TYPE_PUD: Pull up/down configuration.
67 * @PINCFG_TYPE_DRV: Drive strength configuration.
68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
70 */
71enum pincfg_type {
72 PINCFG_TYPE_PUD,
73 PINCFG_TYPE_DRV,
74 PINCFG_TYPE_SKEW_RATE,
75 PINCFG_TYPE_INPUT_TYPE
76};
77
78/**
79 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
80 * @name: name of the pin group, used to lookup the group.
81 * @pins: the pins included in this group.
82 * @num_pins: number of pins included in this group.
83 */
84struct exynos5440_pin_group {
85 const char *name;
86 const unsigned int *pins;
87 u8 num_pins;
88};
89
90/**
91 * struct exynos5440_pmx_func: represent a pin function.
92 * @name: name of the pin function, used to lookup the function.
93 * @groups: one or more names of pin groups that provide this function.
94 * @num_groups: number of groups included in @groups.
95 * @function: the function number to be programmed when selected.
96 */
97struct exynos5440_pmx_func {
98 const char *name;
99 const char **groups;
100 u8 num_groups;
101 unsigned long function;
102};
103
104/**
105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
106 * @reg_base: ioremapped based address of the register space.
107 * @gc: gpio chip registered with gpiolib.
108 * @pin_groups: list of pin groups parsed from device tree.
109 * @nr_groups: number of pin groups available.
110 * @pmx_functions: list of pin functions parsed from device tree.
111 * @nr_functions: number of pin functions available.
112 */
113struct exynos5440_pinctrl_priv_data {
114 void __iomem *reg_base;
115 struct gpio_chip *gc;
Thomas Abraham8dc35682013-03-27 00:12:33 +0900116 struct irq_domain *irq_domain;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900117
118 const struct exynos5440_pin_group *pin_groups;
119 unsigned int nr_groups;
120 const struct exynos5440_pmx_func *pmx_functions;
121 unsigned int nr_functions;
122};
123
Thomas Abraham8dc35682013-03-27 00:12:33 +0900124/**
125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126 * @priv: driver's private runtime data.
127 * @gpio_int: gpio interrupt number.
128 */
129struct exynos5440_gpio_intr_data {
130 struct exynos5440_pinctrl_priv_data *priv;
131 unsigned int gpio_int;
132};
133
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900134/* list of all possible config options supported */
Axel Lind5fd5da2012-12-10 09:54:03 +0900135static struct pin_config {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900136 char *prop_cfg;
137 unsigned int cfg_type;
138} pcfgs[] = {
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
143};
144
145/* check if the selector is a valid pin group selector */
146static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
147{
148 struct exynos5440_pinctrl_priv_data *priv;
149
150 priv = pinctrl_dev_get_drvdata(pctldev);
151 return priv->nr_groups;
152}
153
154/* return the name of the group selected by the group selector */
155static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
156 unsigned selector)
157{
158 struct exynos5440_pinctrl_priv_data *priv;
159
160 priv = pinctrl_dev_get_drvdata(pctldev);
161 return priv->pin_groups[selector].name;
162}
163
164/* return the pin numbers associated with the specified group */
165static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
166 unsigned selector, const unsigned **pins, unsigned *num_pins)
167{
168 struct exynos5440_pinctrl_priv_data *priv;
169
170 priv = pinctrl_dev_get_drvdata(pctldev);
171 *pins = priv->pin_groups[selector].pins;
172 *num_pins = priv->pin_groups[selector].num_pins;
173 return 0;
174}
175
176/* create pinctrl_map entries by parsing device tree nodes */
177static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
178 struct device_node *np, struct pinctrl_map **maps,
179 unsigned *nmaps)
180{
181 struct device *dev = pctldev->dev;
182 struct pinctrl_map *map;
183 unsigned long *cfg = NULL;
184 char *gname, *fname;
185 int cfg_cnt = 0, map_cnt = 0, idx = 0;
186
187 /* count the number of config options specfied in the node */
188 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
189 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
190 cfg_cnt++;
191
192 /*
193 * Find out the number of map entries to create. All the config options
194 * can be accomadated into a single config map entry.
195 */
196 if (cfg_cnt)
197 map_cnt = 1;
198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
199 map_cnt++;
200 if (!map_cnt) {
201 dev_err(dev, "node %s does not have either config or function "
202 "configurations\n", np->name);
203 return -EINVAL;
204 }
205
206 /* Allocate memory for pin-map entries */
207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
208 if (!map) {
209 dev_err(dev, "could not alloc memory for pin-maps\n");
210 return -ENOMEM;
211 }
212 *nmaps = 0;
213
214 /*
215 * Allocate memory for pin group name. The pin group name is derived
216 * from the node name from which these map entries are be created.
217 */
218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
219 if (!gname) {
220 dev_err(dev, "failed to alloc memory for group name\n");
221 goto free_map;
222 }
223 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
224
225 /*
226 * don't have config options? then skip over to creating function
227 * map entries.
228 */
229 if (!cfg_cnt)
230 goto skip_cfgs;
231
232 /* Allocate memory for config entries */
233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
234 if (!cfg) {
235 dev_err(dev, "failed to alloc memory for configs\n");
236 goto free_gname;
237 }
238
239 /* Prepare a list of config settings */
240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
241 u32 value;
242 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
243 cfg[cfg_cnt++] =
244 PINCFG_PACK(pcfgs[idx].cfg_type, value);
245 }
246
247 /* create the config map entry */
248 map[*nmaps].data.configs.group_or_pin = gname;
249 map[*nmaps].data.configs.configs = cfg;
250 map[*nmaps].data.configs.num_configs = cfg_cnt;
251 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
252 *nmaps += 1;
253
254skip_cfgs:
255 /* create the function map entry */
256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
258 if (!fname) {
259 dev_err(dev, "failed to alloc memory for func name\n");
260 goto free_cfg;
261 }
262 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
263
264 map[*nmaps].data.mux.group = gname;
265 map[*nmaps].data.mux.function = fname;
266 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
267 *nmaps += 1;
268 }
269
270 *maps = map;
271 return 0;
272
273free_cfg:
274 kfree(cfg);
275free_gname:
276 kfree(gname);
277free_map:
278 kfree(map);
279 return -ENOMEM;
280}
281
282/* free the memory allocated to hold the pin-map table */
283static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
284 struct pinctrl_map *map, unsigned num_maps)
285{
286 int idx;
287
288 for (idx = 0; idx < num_maps; idx++) {
289 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
290 kfree(map[idx].data.mux.function);
291 if (!idx)
292 kfree(map[idx].data.mux.group);
293 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
294 kfree(map[idx].data.configs.configs);
295 if (!idx)
296 kfree(map[idx].data.configs.group_or_pin);
297 }
298 };
299
300 kfree(map);
301}
302
303/* list of pinctrl callbacks for the pinctrl core */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100304static const struct pinctrl_ops exynos5440_pctrl_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900305 .get_groups_count = exynos5440_get_group_count,
306 .get_group_name = exynos5440_get_group_name,
307 .get_group_pins = exynos5440_get_group_pins,
308 .dt_node_to_map = exynos5440_dt_node_to_map,
309 .dt_free_map = exynos5440_dt_free_map,
310};
311
312/* check if the selector is a valid pin function selector */
313static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
314{
315 struct exynos5440_pinctrl_priv_data *priv;
316
317 priv = pinctrl_dev_get_drvdata(pctldev);
318 return priv->nr_functions;
319}
320
321/* return the name of the pin function specified */
322static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
323 unsigned selector)
324{
325 struct exynos5440_pinctrl_priv_data *priv;
326
327 priv = pinctrl_dev_get_drvdata(pctldev);
328 return priv->pmx_functions[selector].name;
329}
330
331/* return the groups associated for the specified function selector */
332static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
333 unsigned selector, const char * const **groups,
334 unsigned * const num_groups)
335{
336 struct exynos5440_pinctrl_priv_data *priv;
337
338 priv = pinctrl_dev_get_drvdata(pctldev);
339 *groups = priv->pmx_functions[selector].groups;
340 *num_groups = priv->pmx_functions[selector].num_groups;
341 return 0;
342}
343
344/* enable or disable a pinmux function */
345static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
346 unsigned group, bool enable)
347{
348 struct exynos5440_pinctrl_priv_data *priv;
349 void __iomem *base;
350 u32 function;
351 u32 data;
352
353 priv = pinctrl_dev_get_drvdata(pctldev);
354 base = priv->reg_base;
355 function = priv->pmx_functions[selector].function;
356
357 data = readl(base + GPIO_MUX);
358 if (enable)
359 data |= (1 << function);
360 else
361 data &= ~(1 << function);
362 writel(data, base + GPIO_MUX);
363}
364
365/* enable a specified pinmux by writing to registers */
366static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
367 unsigned group)
368{
369 exynos5440_pinmux_setup(pctldev, selector, group, true);
370 return 0;
371}
372
373/* disable a specified pinmux by writing to registers */
374static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
375 unsigned selector, unsigned group)
376{
377 exynos5440_pinmux_setup(pctldev, selector, group, false);
378}
379
380/*
381 * The calls to gpio_direction_output() and gpio_direction_input()
382 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
383 * function called from the gpiolib interface).
384 */
385static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
386 struct pinctrl_gpio_range *range, unsigned offset, bool input)
387{
388 return 0;
389}
390
391/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100392static const struct pinmux_ops exynos5440_pinmux_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900393 .get_functions_count = exynos5440_get_functions_count,
394 .get_function_name = exynos5440_pinmux_get_fname,
395 .get_function_groups = exynos5440_pinmux_get_groups,
396 .enable = exynos5440_pinmux_enable,
397 .disable = exynos5440_pinmux_disable,
398 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
399};
400
401/* set the pin config settings for a specified pin */
402static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
403 unsigned long config)
404{
405 struct exynos5440_pinctrl_priv_data *priv;
406 void __iomem *base;
407 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
408 u32 cfg_value = PINCFG_UNPACK_VALUE(config);
409 u32 data;
410
411 priv = pinctrl_dev_get_drvdata(pctldev);
412 base = priv->reg_base;
413
414 switch (cfg_type) {
415 case PINCFG_TYPE_PUD:
416 /* first set pull enable/disable bit */
417 data = readl(base + GPIO_PE);
418 data &= ~(1 << pin);
419 if (cfg_value)
420 data |= (1 << pin);
421 writel(data, base + GPIO_PE);
422
423 /* then set pull up/down bit */
424 data = readl(base + GPIO_PS);
425 data &= ~(1 << pin);
426 if (cfg_value == 2)
427 data |= (1 << pin);
428 writel(data, base + GPIO_PS);
429 break;
430
431 case PINCFG_TYPE_DRV:
432 /* set the first bit of the drive strength */
433 data = readl(base + GPIO_DS0);
434 data &= ~(1 << pin);
435 data |= ((cfg_value & 1) << pin);
436 writel(data, base + GPIO_DS0);
437 cfg_value >>= 1;
438
439 /* set the second bit of the driver strength */
440 data = readl(base + GPIO_DS1);
441 data &= ~(1 << pin);
442 data |= ((cfg_value & 1) << pin);
443 writel(data, base + GPIO_DS1);
444 break;
445 case PINCFG_TYPE_SKEW_RATE:
446 data = readl(base + GPIO_SR);
447 data &= ~(1 << pin);
448 data |= ((cfg_value & 1) << pin);
449 writel(data, base + GPIO_SR);
450 break;
451 case PINCFG_TYPE_INPUT_TYPE:
452 data = readl(base + GPIO_TYPE);
453 data &= ~(1 << pin);
454 data |= ((cfg_value & 1) << pin);
455 writel(data, base + GPIO_TYPE);
456 break;
457 default:
458 WARN_ON(1);
459 return -EINVAL;
460 }
461
462 return 0;
463}
464
465/* get the pin config settings for a specified pin */
466static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
467 unsigned long *config)
468{
469 struct exynos5440_pinctrl_priv_data *priv;
470 void __iomem *base;
471 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
472 u32 data;
473
474 priv = pinctrl_dev_get_drvdata(pctldev);
475 base = priv->reg_base;
476
477 switch (cfg_type) {
478 case PINCFG_TYPE_PUD:
479 data = readl(base + GPIO_PE);
480 data = (data >> pin) & 1;
481 if (!data)
482 *config = 0;
483 else
484 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
485 break;
486 case PINCFG_TYPE_DRV:
487 data = readl(base + GPIO_DS0);
488 data = (data >> pin) & 1;
489 *config = data;
490 data = readl(base + GPIO_DS1);
491 data = (data >> pin) & 1;
492 *config |= (data << 1);
493 break;
494 case PINCFG_TYPE_SKEW_RATE:
495 data = readl(base + GPIO_SR);
496 *config = (data >> pin) & 1;
497 break;
498 case PINCFG_TYPE_INPUT_TYPE:
499 data = readl(base + GPIO_TYPE);
500 *config = (data >> pin) & 1;
501 break;
502 default:
503 WARN_ON(1);
504 return -EINVAL;
505 }
506
507 return 0;
508}
509
510/* set the pin config settings for a specified pin group */
511static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
512 unsigned group, unsigned long config)
513{
514 struct exynos5440_pinctrl_priv_data *priv;
515 const unsigned int *pins;
516 unsigned int cnt;
517
518 priv = pinctrl_dev_get_drvdata(pctldev);
519 pins = priv->pin_groups[group].pins;
520
521 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
522 exynos5440_pinconf_set(pctldev, pins[cnt], config);
523
524 return 0;
525}
526
527/* get the pin config settings for a specified pin group */
528static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
529 unsigned int group, unsigned long *config)
530{
531 struct exynos5440_pinctrl_priv_data *priv;
532 const unsigned int *pins;
533
534 priv = pinctrl_dev_get_drvdata(pctldev);
535 pins = priv->pin_groups[group].pins;
536 exynos5440_pinconf_get(pctldev, pins[0], config);
537 return 0;
538}
539
540/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100541static const struct pinconf_ops exynos5440_pinconf_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900542 .pin_config_get = exynos5440_pinconf_get,
543 .pin_config_set = exynos5440_pinconf_set,
544 .pin_config_group_get = exynos5440_pinconf_group_get,
545 .pin_config_group_set = exynos5440_pinconf_group_set,
546};
547
548/* gpiolib gpio_set callback function */
549static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
550{
551 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
552 void __iomem *base = priv->reg_base;
553 u32 data;
554
555 data = readl(base + GPIO_VAL);
556 data &= ~(1 << offset);
557 if (value)
558 data |= 1 << offset;
559 writel(data, base + GPIO_VAL);
560}
561
562/* gpiolib gpio_get callback function */
563static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
564{
565 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
566 void __iomem *base = priv->reg_base;
567 u32 data;
568
569 data = readl(base + GPIO_IN);
570 data >>= offset;
571 data &= 1;
572 return data;
573}
574
575/* gpiolib gpio_direction_input callback function */
576static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
577{
578 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
579 void __iomem *base = priv->reg_base;
580 u32 data;
581
582 /* first disable the data output enable on this pin */
583 data = readl(base + GPIO_OE);
584 data &= ~(1 << offset);
585 writel(data, base + GPIO_OE);
586
587 /* now enable input on this pin */
588 data = readl(base + GPIO_IE);
589 data |= 1 << offset;
590 writel(data, base + GPIO_IE);
591 return 0;
592}
593
594/* gpiolib gpio_direction_output callback function */
595static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
596 int value)
597{
598 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
599 void __iomem *base = priv->reg_base;
600 u32 data;
601
602 exynos5440_gpio_set(gc, offset, value);
603
604 /* first disable the data input enable on this pin */
605 data = readl(base + GPIO_IE);
606 data &= ~(1 << offset);
607 writel(data, base + GPIO_IE);
608
609 /* now enable output on this pin */
610 data = readl(base + GPIO_OE);
611 data |= 1 << offset;
612 writel(data, base + GPIO_OE);
613 return 0;
614}
615
Thomas Abraham8dc35682013-03-27 00:12:33 +0900616/* gpiolib gpio_to_irq callback function */
617static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
618{
619 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
620 unsigned int virq;
621
622 if (offset < 16 || offset > 23)
623 return -ENXIO;
624
625 if (!priv->irq_domain)
626 return -ENXIO;
627
628 virq = irq_create_mapping(priv->irq_domain, offset - 16);
629 return virq ? : -ENXIO;
630}
631
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900632/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000633static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900634 struct device_node *cfg_np, unsigned int **pin_list,
635 unsigned int *npins)
636{
637 struct device *dev = &pdev->dev;
638 struct property *prop;
639
640 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
641 if (!prop)
642 return -ENOENT;
643
644 *npins = prop->length / sizeof(unsigned long);
645 if (!*npins) {
646 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
647 return -EINVAL;
648 }
649
650 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
651 if (!*pin_list) {
652 dev_err(dev, "failed to allocate memory for pin list\n");
653 return -ENOMEM;
654 }
655
656 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
657 *pin_list, *npins);
658}
659
660/*
661 * Parse the information about all the available pin groups and pin functions
662 * from device node of the pin-controller.
663 */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000664static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900665 struct exynos5440_pinctrl_priv_data *priv)
666{
667 struct device *dev = &pdev->dev;
668 struct device_node *dev_np = dev->of_node;
669 struct device_node *cfg_np;
670 struct exynos5440_pin_group *groups, *grp;
671 struct exynos5440_pmx_func *functions, *func;
672 unsigned *pin_list;
673 unsigned int npins, grp_cnt, func_idx = 0;
674 char *gname, *fname;
675 int ret;
676
677 grp_cnt = of_get_child_count(dev_np);
678 if (!grp_cnt)
679 return -EINVAL;
680
681 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
682 if (!groups) {
683 dev_err(dev, "failed allocate memory for ping group list\n");
684 return -EINVAL;
685 }
686 grp = groups;
687
688 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
689 if (!functions) {
690 dev_err(dev, "failed to allocate memory for function list\n");
691 return -EINVAL;
692 }
693 func = functions;
694
695 /*
696 * Iterate over all the child nodes of the pin controller node
697 * and create pin groups and pin function lists.
698 */
699 for_each_child_of_node(dev_np, cfg_np) {
700 u32 function;
701
702 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
703 &pin_list, &npins);
Thomas Abrahamf9819732013-03-27 00:12:32 +0900704 if (ret) {
705 gname = NULL;
706 goto skip_to_pin_function;
707 }
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900708
709 /* derive pin group name from the node name */
710 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
711 GFP_KERNEL);
712 if (!gname) {
713 dev_err(dev, "failed to alloc memory for group name\n");
714 return -ENOMEM;
715 }
716 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
717
718 grp->name = gname;
719 grp->pins = pin_list;
720 grp->num_pins = npins;
721 grp++;
722
Thomas Abrahamf9819732013-03-27 00:12:32 +0900723skip_to_pin_function:
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900724 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
725 &function);
726 if (ret)
727 continue;
728
729 /* derive function name from the node name */
730 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
731 GFP_KERNEL);
732 if (!fname) {
733 dev_err(dev, "failed to alloc memory for func name\n");
734 return -ENOMEM;
735 }
736 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
737
738 func->name = fname;
739 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
740 if (!func->groups) {
741 dev_err(dev, "failed to alloc memory for group list "
742 "in pin function");
743 return -ENOMEM;
744 }
745 func->groups[0] = gname;
Thomas Abrahamf9819732013-03-27 00:12:32 +0900746 func->num_groups = gname ? 1 : 0;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900747 func->function = function;
748 func++;
749 func_idx++;
750 }
751
752 priv->pin_groups = groups;
753 priv->nr_groups = grp_cnt;
754 priv->pmx_functions = functions;
755 priv->nr_functions = func_idx;
756 return 0;
757}
758
759/* register the pinctrl interface with the pinctrl subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000760static int exynos5440_pinctrl_register(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900761 struct exynos5440_pinctrl_priv_data *priv)
762{
763 struct device *dev = &pdev->dev;
764 struct pinctrl_desc *ctrldesc;
765 struct pinctrl_dev *pctl_dev;
766 struct pinctrl_pin_desc *pindesc, *pdesc;
767 struct pinctrl_gpio_range grange;
768 char *pin_names;
769 int pin, ret;
770
771 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
772 if (!ctrldesc) {
773 dev_err(dev, "could not allocate memory for pinctrl desc\n");
774 return -ENOMEM;
775 }
776
777 ctrldesc->name = "exynos5440-pinctrl";
778 ctrldesc->owner = THIS_MODULE;
779 ctrldesc->pctlops = &exynos5440_pctrl_ops;
780 ctrldesc->pmxops = &exynos5440_pinmux_ops;
781 ctrldesc->confops = &exynos5440_pinconf_ops;
782
783 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
784 EXYNOS5440_MAX_PINS, GFP_KERNEL);
785 if (!pindesc) {
786 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
787 return -ENOMEM;
788 }
789 ctrldesc->pins = pindesc;
790 ctrldesc->npins = EXYNOS5440_MAX_PINS;
791
792 /* dynamically populate the pin number and pin name for pindesc */
793 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
794 pdesc->number = pin;
795
796 /*
797 * allocate space for storing the dynamically generated names for all
798 * the pins which belong to this pin-controller.
799 */
800 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
801 ctrldesc->npins, GFP_KERNEL);
802 if (!pin_names) {
803 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
804 return -ENOMEM;
805 }
806
807 /* for each pin, set the name of the pin */
808 for (pin = 0; pin < ctrldesc->npins; pin++) {
809 sprintf(pin_names, "gpio%02d", pin);
810 pdesc = pindesc + pin;
811 pdesc->name = pin_names;
812 pin_names += PIN_NAME_LENGTH;
813 }
814
815 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
816 if (ret)
817 return ret;
818
819 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
820 if (!pctl_dev) {
821 dev_err(&pdev->dev, "could not register pinctrl driver\n");
822 return -EINVAL;
823 }
824
825 grange.name = "exynos5440-pctrl-gpio-range";
826 grange.id = 0;
827 grange.base = 0;
828 grange.npins = EXYNOS5440_MAX_PINS;
829 grange.gc = priv->gc;
830 pinctrl_add_gpio_range(pctl_dev, &grange);
831 return 0;
832}
833
834/* register the gpiolib interface with the gpiolib subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000835static int exynos5440_gpiolib_register(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900836 struct exynos5440_pinctrl_priv_data *priv)
837{
838 struct gpio_chip *gc;
839 int ret;
840
841 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
842 if (!gc) {
843 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
844 return -ENOMEM;
845 }
846
847 priv->gc = gc;
848 gc->base = 0;
849 gc->ngpio = EXYNOS5440_MAX_PINS;
850 gc->dev = &pdev->dev;
851 gc->set = exynos5440_gpio_set;
852 gc->get = exynos5440_gpio_get;
853 gc->direction_input = exynos5440_gpio_direction_input;
854 gc->direction_output = exynos5440_gpio_direction_output;
Thomas Abraham8dc35682013-03-27 00:12:33 +0900855 gc->to_irq = exynos5440_gpio_to_irq;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900856 gc->label = "gpiolib-exynos5440";
857 gc->owner = THIS_MODULE;
858 ret = gpiochip_add(gc);
859 if (ret) {
860 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
861 "code: %d\n", gc->label, ret);
862 return ret;
863 }
864
865 return 0;
866}
867
868/* unregister the gpiolib interface with the gpiolib subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000869static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900870 struct exynos5440_pinctrl_priv_data *priv)
871{
872 int ret = gpiochip_remove(priv->gc);
873 if (ret) {
874 dev_err(&pdev->dev, "gpio chip remove failed\n");
875 return ret;
876 }
877 return 0;
878}
879
Thomas Abraham8dc35682013-03-27 00:12:33 +0900880static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
881{
882 struct exynos5440_pinctrl_priv_data *d;
883 unsigned long gpio_int;
884
885 d = irq_data_get_irq_chip_data(irqd);
886 gpio_int = readl(d->reg_base + GPIO_INT);
887 gpio_int |= 1 << irqd->hwirq;
888 writel(gpio_int, d->reg_base + GPIO_INT);
889}
890
891static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
892{
893 struct exynos5440_pinctrl_priv_data *d;
894 unsigned long gpio_int;
895
896 d = irq_data_get_irq_chip_data(irqd);
897 gpio_int = readl(d->reg_base + GPIO_INT);
898 gpio_int &= ~(1 << irqd->hwirq);
899 writel(gpio_int, d->reg_base + GPIO_INT);
900}
901
902/* irq_chip for gpio interrupts */
903static struct irq_chip exynos5440_gpio_irq_chip = {
904 .name = "exynos5440_gpio_irq_chip",
905 .irq_unmask = exynos5440_gpio_irq_unmask,
906 .irq_mask = exynos5440_gpio_irq_mask,
907};
908
909/* interrupt handler for GPIO interrupts 0..7 */
910static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
911{
912 struct exynos5440_gpio_intr_data *intd = data;
913 struct exynos5440_pinctrl_priv_data *d = intd->priv;
914 int virq;
915
916 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
917 if (!virq)
918 return IRQ_NONE;
919 generic_handle_irq(virq);
920 return IRQ_HANDLED;
921}
922
923static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
924 irq_hw_number_t hw)
925{
926 struct exynos5440_pinctrl_priv_data *d = h->host_data;
927
928 irq_set_chip_data(virq, d);
929 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
930 handle_level_irq);
931 set_irq_flags(virq, IRQF_VALID);
932 return 0;
933}
934
935/* irq domain callbacks for gpio interrupt controller */
936static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
937 .map = exynos5440_gpio_irq_map,
938 .xlate = irq_domain_xlate_twocell,
939};
940
941/* setup handling of gpio interrupts */
942static int exynos5440_gpio_irq_init(struct platform_device *pdev,
943 struct exynos5440_pinctrl_priv_data *priv)
944{
945 struct device *dev = &pdev->dev;
946 struct exynos5440_gpio_intr_data *intd;
947 int i, irq, ret;
948
949 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
950 GFP_KERNEL);
951 if (!intd) {
952 dev_err(dev, "failed to allocate memory for gpio intr data\n");
953 return -ENOMEM;
954 }
955
956 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
957 irq = irq_of_parse_and_map(dev->of_node, i);
958 if (irq <= 0) {
959 dev_err(dev, "irq parsing failed\n");
960 return -EINVAL;
961 }
962
963 intd->gpio_int = i;
964 intd->priv = priv;
965 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
966 0, dev_name(dev), intd++);
967 if (ret) {
968 dev_err(dev, "irq request failed\n");
969 return -ENXIO;
970 }
971 }
972
973 priv->irq_domain = irq_domain_add_linear(dev->of_node,
974 EXYNOS5440_MAX_GPIO_INT,
975 &exynos5440_gpio_irqd_ops, priv);
976 if (!priv->irq_domain) {
977 dev_err(dev, "failed to create irq domain\n");
978 return -ENXIO;
979 }
980
981 return 0;
982}
983
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800984static int exynos5440_pinctrl_probe(struct platform_device *pdev)
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900985{
986 struct device *dev = &pdev->dev;
987 struct exynos5440_pinctrl_priv_data *priv;
988 struct resource *res;
989 int ret;
990
991 if (!dev->of_node) {
992 dev_err(dev, "device tree node not found\n");
993 return -ENODEV;
994 }
995
Wei Yongjunc078d782013-03-14 21:59:38 +0800996 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900997 if (!priv) {
998 dev_err(dev, "could not allocate memory for private data\n");
999 return -ENOMEM;
1000 }
1001
1002 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1003 if (!res) {
1004 dev_err(dev, "cannot find IO resource\n");
1005 return -ENOENT;
1006 }
1007
Thierry Reding9e0c1fb2013-01-21 11:09:14 +01001008 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
1009 if (IS_ERR(priv->reg_base))
1010 return PTR_ERR(priv->reg_base);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001011
1012 ret = exynos5440_gpiolib_register(pdev, priv);
1013 if (ret)
1014 return ret;
1015
1016 ret = exynos5440_pinctrl_register(pdev, priv);
1017 if (ret) {
1018 exynos5440_gpiolib_unregister(pdev, priv);
1019 return ret;
1020 }
1021
Thomas Abraham8dc35682013-03-27 00:12:33 +09001022 ret = exynos5440_gpio_irq_init(pdev, priv);
1023 if (ret) {
1024 dev_err(dev, "failed to setup gpio interrupts\n");
1025 return ret;
1026 }
1027
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001028 platform_set_drvdata(pdev, priv);
1029 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
1030 return 0;
1031}
1032
1033static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
1034 { .compatible = "samsung,exynos5440-pinctrl" },
1035 {},
1036};
1037MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
1038
1039static struct platform_driver exynos5440_pinctrl_driver = {
1040 .probe = exynos5440_pinctrl_probe,
1041 .driver = {
1042 .name = "exynos5440-pinctrl",
1043 .owner = THIS_MODULE,
1044 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
1045 },
1046};
1047
1048static int __init exynos5440_pinctrl_drv_register(void)
1049{
1050 return platform_driver_register(&exynos5440_pinctrl_driver);
1051}
1052postcore_initcall(exynos5440_pinctrl_drv_register);
1053
1054static void __exit exynos5440_pinctrl_drv_unregister(void)
1055{
1056 platform_driver_unregister(&exynos5440_pinctrl_driver);
1057}
1058module_exit(exynos5440_pinctrl_drv_unregister);
1059
1060MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1061MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1062MODULE_LICENSE("GPL v2");