blob: 53fa19cf2f0636d6dd79d0918266243441bda31f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/string.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/tty.h>
24#include <linux/serial_core.h>
25#include <linux/8250_pci.h>
26#include <linux/bitops.h>
27
28#include <asm/byteorder.h>
29#include <asm/io.h>
30
31#include "8250.h"
32
33#undef SERIAL_DEBUG_PCI
34
35/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*init)(struct pci_dev *dev);
Russell King70db3d92005-07-27 11:34:27 +010047 int (*setup)(struct serial_private *, struct pciserial_board *,
Russell King05caac52005-07-27 11:41:18 +010048 struct uart_port *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
Russell King70db3d92005-07-27 11:34:27 +010055 struct pci_dev *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
62static void moan_device(const char *str, struct pci_dev *dev)
63{
64 printk(KERN_WARNING "%s: %s\n"
65 KERN_WARNING "Please send the output of lspci -vv, this\n"
66 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 KERN_WARNING "manufacturer and name of serial board or\n"
68 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
Russell King70db3d92005-07-27 11:34:27 +010074setup_port(struct serial_private *priv, struct uart_port *port,
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 int bar, int offset, int regshift)
76{
Russell King70db3d92005-07-27 11:34:27 +010077 struct pci_dev *dev = priv->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
Russell King72ce9a82005-07-27 11:32:04 +010083 base = pci_resource_start(dev, bar);
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
Alan Cox6f441fe2008-05-01 04:34:59 -070089 priv->remapped_bar[bar] = ioremap_nocache(base, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
Russell King72ce9a82005-07-27 11:32:04 +010094 port->iobase = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 port->iotype = UPIO_PORT;
Russell King72ce9a82005-07-27 11:32:04 +0100100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 }
105 return 0;
106}
107
108/*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111static int addidata_apci7800_setup(struct serial_private *priv,
112 struct pciserial_board *board,
113 struct uart_port *port, int idx)
114{
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132}
133
134/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138static int
Russell King70db3d92005-07-27 11:34:27 +0100139afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 struct uart_port *port, int idx)
141{
142 unsigned int bar, offset = board->first_offset;
Alan Cox5756ee92008-02-08 04:18:51 -0800143
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
Russell King70db3d92005-07-27 11:34:27 +0100152 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153}
154
155/*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
Russell King61a116e2006-07-03 15:22:35 +0100162static int pci_hp_diva_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163{
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
Justin Chen551f8f02005-10-24 22:16:38 +0100180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 rc = 1;
182 break;
183 }
184
185 return rc;
186}
187
188/*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192static int
Russell King70db3d92005-07-27 11:34:27 +0100193pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 struct uart_port *port, int idx)
195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
Russell King70db3d92005-07-27 11:34:27 +0100199 switch (priv->dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
Russell King70db3d92005-07-27 11:34:27 +0100216 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
Russell King61a116e2006-07-03 15:22:35 +0100222static int pci_inteli960ni_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
Alan Cox5756ee92008-02-08 04:18:51 -0800230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
Russell King61a116e2006-07-03 15:22:35 +0100244static int pci_plx9050_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
Alan Cox5756ee92008-02-08 04:18:51 -0800256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 irq_config = 0x43;
Alan Cox5756ee92008-02-08 04:18:51 -0800258
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
Alan Cox5756ee92008-02-08 04:18:51 -0800260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 /*
271 * enable/disable interrupts
272 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
287static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int
Russell King70db3d92005-07-27 11:34:27 +0100311sbs_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 struct uart_port *port, int idx)
313{
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
Russell King70db3d92005-07-27 11:34:27 +0100327 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328}
329
330/*
331* This does initialization for PMC OCTALPRO cards:
332* maps the device memory, resets the UARTs (needed, bc
333* if the module is removed and inserted again, the card
334* is in the sleep mode) and enables global interrupt.
335*/
336
337/* global control register offset for SBS PMC-OctalPro */
338#define OCT_REG_CR_OFF 0x500
339
Russell King61a116e2006-07-03 15:22:35 +0100340static int sbs_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341{
342 u8 __iomem *p;
343
Alan Cox6f441fe2008-05-01 04:34:59 -0700344 p = ioremap_nocache(pci_resource_start(dev, 0),
345 pci_resource_len(dev, 0));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346
347 if (p == NULL)
348 return -ENOMEM;
349 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
Alan Cox5756ee92008-02-08 04:18:51 -0800350 writeb(0x10, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 udelay(50);
Alan Cox5756ee92008-02-08 04:18:51 -0800352 writeb(0x0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 /* Set bit-2 (INTENABLE) of Control Register */
355 writeb(0x4, p + OCT_REG_CR_OFF);
356 iounmap(p);
357
358 return 0;
359}
360
361/*
362 * Disables the global interrupt of PMC-OctalPro
363 */
364
365static void __devexit sbs_exit(struct pci_dev *dev)
366{
367 u8 __iomem *p;
368
Alan Cox6f441fe2008-05-01 04:34:59 -0700369 p = ioremap_nocache(pci_resource_start(dev, 0),
370 pci_resource_len(dev, 0));
Alan Cox5756ee92008-02-08 04:18:51 -0800371 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
372 if (p != NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 writeb(0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 iounmap(p);
375}
376
377/*
378 * SIIG serial cards have an PCI interface chip which also controls
379 * the UART clocking frequency. Each UART can be clocked independently
380 * (except cards equiped with 4 UARTs) and initial clocking settings
381 * are stored in the EEPROM chip. It can cause problems because this
382 * version of serial driver doesn't support differently clocked UART's
383 * on single PCI card. To prevent this, initialization functions set
384 * high frequency clocking for all UART's on given card. It is safe (I
385 * hope) because it doesn't touch EEPROM settings to prevent conflicts
386 * with other OSes (like M$ DOS).
387 *
388 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
Alan Cox5756ee92008-02-08 04:18:51 -0800389 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 * There is two family of SIIG serial cards with different PCI
391 * interface chip and different configuration methods:
392 * - 10x cards have control registers in IO and/or memory space;
393 * - 20x cards have control registers in standard PCI configuration space.
394 *
Russell King67d74b82005-07-27 11:33:03 +0100395 * Note: all 10x cards have PCI device ids 0x10..
396 * all 20x cards have PCI device ids 0x20..
397 *
Andrey Paninfbc0dc02005-07-18 11:38:09 +0100398 * There are also Quartet Serial cards which use Oxford Semiconductor
399 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
400 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 * Note: some SIIG cards are probed by the parport_serial object.
402 */
403
404#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
405#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
406
407static int pci_siig10x_init(struct pci_dev *dev)
408{
409 u16 data;
410 void __iomem *p;
411
412 switch (dev->device & 0xfff8) {
413 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 data = 0xffdf;
415 break;
416 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 data = 0xf7ff;
418 break;
419 default: /* 1S1P, 4S */
420 data = 0xfffb;
421 break;
422 }
423
Alan Cox6f441fe2008-05-01 04:34:59 -0700424 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 if (p == NULL)
426 return -ENOMEM;
427
428 writew(readw(p + 0x28) & data, p + 0x28);
429 readw(p + 0x28);
430 iounmap(p);
431 return 0;
432}
433
434#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
435#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
436
437static int pci_siig20x_init(struct pci_dev *dev)
438{
439 u8 data;
440
441 /* Change clock frequency for the first UART. */
442 pci_read_config_byte(dev, 0x6f, &data);
443 pci_write_config_byte(dev, 0x6f, data & 0xef);
444
445 /* If this card has 2 UART, we have to do the same with second UART. */
446 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
447 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
448 pci_read_config_byte(dev, 0x73, &data);
449 pci_write_config_byte(dev, 0x73, data & 0xef);
450 }
451 return 0;
452}
453
Russell King67d74b82005-07-27 11:33:03 +0100454static int pci_siig_init(struct pci_dev *dev)
455{
456 unsigned int type = dev->device & 0xff00;
457
458 if (type == 0x1000)
459 return pci_siig10x_init(dev);
460 else if (type == 0x2000)
461 return pci_siig20x_init(dev);
462
463 moan_device("Unknown SIIG card", dev);
464 return -ENODEV;
465}
466
Andrey Panin3ec9c592006-02-02 20:15:09 +0000467static int pci_siig_setup(struct serial_private *priv,
468 struct pciserial_board *board,
469 struct uart_port *port, int idx)
470{
471 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
472
473 if (idx > 3) {
474 bar = 4;
475 offset = (idx - 4) * 8;
476 }
477
478 return setup_port(priv, port, bar, offset, 0);
479}
480
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481/*
482 * Timedia has an explosion of boards, and to avoid the PCI table from
483 * growing *huge*, we use this function to collapse some 70 entries
484 * in the PCI table into one, for sanity's and compactness's sake.
485 */
Helge Dellere9422e02006-08-29 21:57:29 +0200486static const unsigned short timedia_single_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488};
489
Helge Dellere9422e02006-08-29 21:57:29 +0200490static const unsigned short timedia_dual_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
Alan Cox5756ee92008-02-08 04:18:51 -0800492 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
493 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
495 0xD079, 0
496};
497
Helge Dellere9422e02006-08-29 21:57:29 +0200498static const unsigned short timedia_quad_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800499 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
500 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
502 0xB157, 0
503};
504
Helge Dellere9422e02006-08-29 21:57:29 +0200505static const unsigned short timedia_eight_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800506 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508};
509
Arjan van de Vencb3592b2005-11-28 21:04:11 +0000510static const struct timedia_struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 int num;
Helge Dellere9422e02006-08-29 21:57:29 +0200512 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513} timedia_data[] = {
514 { 1, timedia_single_port },
515 { 2, timedia_dual_port },
516 { 4, timedia_quad_port },
Helge Dellere9422e02006-08-29 21:57:29 +0200517 { 8, timedia_eight_port }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518};
519
Russell King61a116e2006-07-03 15:22:35 +0100520static int pci_timedia_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521{
Helge Dellere9422e02006-08-29 21:57:29 +0200522 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 int i, j;
524
Helge Dellere9422e02006-08-29 21:57:29 +0200525 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 ids = timedia_data[i].ids;
527 for (j = 0; ids[j]; j++)
528 if (dev->subsystem_device == ids[j])
529 return timedia_data[i].num;
530 }
531 return 0;
532}
533
534/*
535 * Timedia/SUNIX uses a mixture of BARs and offsets
536 * Ugh, this is ugly as all hell --- TYT
537 */
538static int
Russell King70db3d92005-07-27 11:34:27 +0100539pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 struct uart_port *port, int idx)
541{
542 unsigned int bar = 0, offset = board->first_offset;
543
544 switch (idx) {
545 case 0:
546 bar = 0;
547 break;
548 case 1:
549 offset = board->uart_offset;
550 bar = 0;
551 break;
552 case 2:
553 bar = 1;
554 break;
555 case 3:
556 offset = board->uart_offset;
Dave Jonesc2cd6d32005-12-07 18:11:26 +0000557 /* FALLTHROUGH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 case 4: /* BAR 2 */
559 case 5: /* BAR 3 */
560 case 6: /* BAR 4 */
561 case 7: /* BAR 5 */
562 bar = idx - 2;
563 }
564
Russell King70db3d92005-07-27 11:34:27 +0100565 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566}
567
568/*
569 * Some Titan cards are also a little weird
570 */
571static int
Russell King70db3d92005-07-27 11:34:27 +0100572titan_400l_800l_setup(struct serial_private *priv,
Russell King1c7c1fe2005-07-27 11:31:19 +0100573 struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574 struct uart_port *port, int idx)
575{
576 unsigned int bar, offset = board->first_offset;
577
578 switch (idx) {
579 case 0:
580 bar = 1;
581 break;
582 case 1:
583 bar = 2;
584 break;
585 default:
586 bar = 4;
587 offset = (idx - 2) * board->uart_offset;
588 }
589
Russell King70db3d92005-07-27 11:34:27 +0100590 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591}
592
Russell King61a116e2006-07-03 15:22:35 +0100593static int pci_xircom_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594{
595 msleep(100);
596 return 0;
597}
598
Russell King61a116e2006-07-03 15:22:35 +0100599static int pci_netmos_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600{
601 /* subdevice 0x00PS means <P> parallel, <S> serial */
602 unsigned int num_serial = dev->subsystem_device & 0xf;
603
604 if (num_serial == 0)
605 return -ENODEV;
606 return num_serial;
607}
608
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700609/*
610 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
611 *
612 * These chips are available with optionally one parallel port and up to
613 * two serial ports. Unfortunately they all have the same product id.
614 *
615 * Basic configuration is done over a region of 32 I/O ports. The base
616 * ioport is called INTA or INTC, depending on docs/other drivers.
617 *
618 * The region of the 32 I/O ports is configured in POSIO0R...
619 */
620
621/* registers */
622#define ITE_887x_MISCR 0x9c
623#define ITE_887x_INTCBAR 0x78
624#define ITE_887x_UARTBAR 0x7c
625#define ITE_887x_PS0BAR 0x10
626#define ITE_887x_POSIO0 0x60
627
628/* I/O space size */
629#define ITE_887x_IOSIZE 32
630/* I/O space size (bits 26-24; 8 bytes = 011b) */
631#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
632/* I/O space size (bits 26-24; 32 bytes = 101b) */
633#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
634/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
635#define ITE_887x_POSIO_SPEED (3 << 29)
636/* enable IO_Space bit */
637#define ITE_887x_POSIO_ENABLE (1 << 31)
638
Ralf Baechlef79abb82007-08-30 23:56:31 -0700639static int pci_ite887x_init(struct pci_dev *dev)
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700640{
641 /* inta_addr are the configuration addresses of the ITE */
642 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
643 0x200, 0x280, 0 };
644 int ret, i, type;
645 struct resource *iobase = NULL;
646 u32 miscr, uartbar, ioport;
647
648 /* search for the base-ioport */
649 i = 0;
650 while (inta_addr[i] && iobase == NULL) {
651 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
652 "ite887x");
653 if (iobase != NULL) {
654 /* write POSIO0R - speed | size | ioport */
655 pci_write_config_dword(dev, ITE_887x_POSIO0,
656 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
657 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
658 /* write INTCBAR - ioport */
Alan Cox5756ee92008-02-08 04:18:51 -0800659 pci_write_config_dword(dev, ITE_887x_INTCBAR,
660 inta_addr[i]);
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700661 ret = inb(inta_addr[i]);
662 if (ret != 0xff) {
663 /* ioport connected */
664 break;
665 }
666 release_region(iobase->start, ITE_887x_IOSIZE);
667 iobase = NULL;
668 }
669 i++;
670 }
671
672 if (!inta_addr[i]) {
673 printk(KERN_ERR "ite887x: could not find iobase\n");
674 return -ENODEV;
675 }
676
677 /* start of undocumented type checking (see parport_pc.c) */
678 type = inb(iobase->start + 0x18) & 0x0f;
679
680 switch (type) {
681 case 0x2: /* ITE8871 (1P) */
682 case 0xa: /* ITE8875 (1P) */
683 ret = 0;
684 break;
685 case 0xe: /* ITE8872 (2S1P) */
686 ret = 2;
687 break;
688 case 0x6: /* ITE8873 (1S) */
689 ret = 1;
690 break;
691 case 0x8: /* ITE8874 (2S) */
692 ret = 2;
693 break;
694 default:
695 moan_device("Unknown ITE887x", dev);
696 ret = -ENODEV;
697 }
698
699 /* configure all serial ports */
700 for (i = 0; i < ret; i++) {
701 /* read the I/O port from the device */
702 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
703 &ioport);
704 ioport &= 0x0000FF00; /* the actual base address */
705 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
706 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
707 ITE_887x_POSIO_IOSIZE_8 | ioport);
708
709 /* write the ioport to the UARTBAR */
710 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
711 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
712 uartbar |= (ioport << (16 * i)); /* set the ioport */
713 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
714
715 /* get current config */
716 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
717 /* disable interrupts (UARTx_Routing[3:0]) */
718 miscr &= ~(0xf << (12 - 4 * i));
719 /* activate the UART (UARTx_En) */
720 miscr |= 1 << (23 - i);
721 /* write new config with activated UART */
722 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
723 }
724
725 if (ret <= 0) {
726 /* the device has no UARTs if we get here */
727 release_region(iobase->start, ITE_887x_IOSIZE);
728 }
729
730 return ret;
731}
732
733static void __devexit pci_ite887x_exit(struct pci_dev *dev)
734{
735 u32 ioport;
736 /* the ioport is bit 0-15 in POSIO0R */
737 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
738 ioport &= 0xffff;
739 release_region(ioport, ITE_887x_IOSIZE);
740}
741
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742static int
Russell King70db3d92005-07-27 11:34:27 +0100743pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 struct uart_port *port, int idx)
745{
746 unsigned int bar, offset = board->first_offset, maxnr;
747
748 bar = FL_GET_BASE(board->flags);
749 if (board->flags & FL_BASE_BARS)
750 bar += idx;
751 else
752 offset += idx * board->uart_offset;
753
Greg Kroah-Hartman2427ddd2006-06-12 17:07:52 -0700754 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
755 (board->reg_shift + 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756
757 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
758 return 1;
Alan Cox5756ee92008-02-08 04:18:51 -0800759
Russell King70db3d92005-07-27 11:34:27 +0100760 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761}
762
763/* This should be in linux/pci_ids.h */
764#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
765#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
766#define PCI_DEVICE_ID_OCTPRO 0x0001
767#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
768#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
769#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
770#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
771
772/*
773 * Master list of serial port init/setup/exit quirks.
774 * This does not describe the general nature of the port.
775 * (ie, baud base, number and location of ports, etc)
776 *
777 * This list is ordered alphabetically by vendor then device.
778 * Specific entries must come before more generic entries.
779 */
Sam Ravnborg7a63ce52008-04-28 02:14:02 -0700780static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800782 * ADDI-DATA GmbH communication cards <info@addi-data.com>
783 */
784 {
785 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
786 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
787 .subvendor = PCI_ANY_ID,
788 .subdevice = PCI_ANY_ID,
789 .setup = addidata_apci7800_setup,
790 },
791 /*
Russell King61a116e2006-07-03 15:22:35 +0100792 * AFAVLAB cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 * It is not clear whether this applies to all products.
794 */
795 {
796 .vendor = PCI_VENDOR_ID_AFAVLAB,
797 .device = PCI_ANY_ID,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .setup = afavlab_setup,
801 },
802 /*
803 * HP Diva
804 */
805 {
806 .vendor = PCI_VENDOR_ID_HP,
807 .device = PCI_DEVICE_ID_HP_DIVA,
808 .subvendor = PCI_ANY_ID,
809 .subdevice = PCI_ANY_ID,
810 .init = pci_hp_diva_init,
811 .setup = pci_hp_diva_setup,
812 },
813 /*
814 * Intel
815 */
816 {
817 .vendor = PCI_VENDOR_ID_INTEL,
818 .device = PCI_DEVICE_ID_INTEL_80960_RP,
819 .subvendor = 0xe4bf,
820 .subdevice = PCI_ANY_ID,
821 .init = pci_inteli960ni_init,
822 .setup = pci_default_setup,
823 },
824 /*
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700825 * ITE
826 */
827 {
828 .vendor = PCI_VENDOR_ID_ITE,
829 .device = PCI_DEVICE_ID_ITE_8872,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .init = pci_ite887x_init,
833 .setup = pci_default_setup,
834 .exit = __devexit_p(pci_ite887x_exit),
835 },
836 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 * Panacom
838 */
839 {
840 .vendor = PCI_VENDOR_ID_PANACOM,
841 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .init = pci_plx9050_init,
845 .setup = pci_default_setup,
846 .exit = __devexit_p(pci_plx9050_exit),
Alan Cox5756ee92008-02-08 04:18:51 -0800847 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848 {
849 .vendor = PCI_VENDOR_ID_PANACOM,
850 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
851 .subvendor = PCI_ANY_ID,
852 .subdevice = PCI_ANY_ID,
853 .init = pci_plx9050_init,
854 .setup = pci_default_setup,
855 .exit = __devexit_p(pci_plx9050_exit),
856 },
857 /*
858 * PLX
859 */
860 {
861 .vendor = PCI_VENDOR_ID_PLX,
Thomas Hoehn48212002007-02-10 01:46:05 -0800862 .device = PCI_DEVICE_ID_PLX_9030,
863 .subvendor = PCI_SUBVENDOR_ID_PERLE,
864 .subdevice = PCI_ANY_ID,
865 .setup = pci_default_setup,
866 },
867 {
868 .vendor = PCI_VENDOR_ID_PLX,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 .device = PCI_DEVICE_ID_PLX_9050,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100870 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
871 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
872 .init = pci_plx9050_init,
873 .setup = pci_default_setup,
874 .exit = __devexit_p(pci_plx9050_exit),
875 },
876 {
877 .vendor = PCI_VENDOR_ID_PLX,
878 .device = PCI_DEVICE_ID_PLX_9050,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
880 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
881 .init = pci_plx9050_init,
882 .setup = pci_default_setup,
883 .exit = __devexit_p(pci_plx9050_exit),
884 },
885 {
886 .vendor = PCI_VENDOR_ID_PLX,
887 .device = PCI_DEVICE_ID_PLX_ROMULUS,
888 .subvendor = PCI_VENDOR_ID_PLX,
889 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
890 .init = pci_plx9050_init,
891 .setup = pci_default_setup,
892 .exit = __devexit_p(pci_plx9050_exit),
893 },
894 /*
895 * SBS Technologies, Inc., PMC-OCTALPRO 232
896 */
897 {
898 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
899 .device = PCI_DEVICE_ID_OCTPRO,
900 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
901 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
902 .init = sbs_init,
903 .setup = sbs_setup,
904 .exit = __devexit_p(sbs_exit),
905 },
906 /*
907 * SBS Technologies, Inc., PMC-OCTALPRO 422
908 */
909 {
910 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
911 .device = PCI_DEVICE_ID_OCTPRO,
912 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
913 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
914 .init = sbs_init,
915 .setup = sbs_setup,
916 .exit = __devexit_p(sbs_exit),
917 },
918 /*
919 * SBS Technologies, Inc., P-Octal 232
920 */
921 {
922 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
923 .device = PCI_DEVICE_ID_OCTPRO,
924 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
925 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
926 .init = sbs_init,
927 .setup = sbs_setup,
928 .exit = __devexit_p(sbs_exit),
929 },
930 /*
931 * SBS Technologies, Inc., P-Octal 422
932 */
933 {
934 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
935 .device = PCI_DEVICE_ID_OCTPRO,
936 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
937 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
938 .init = sbs_init,
939 .setup = sbs_setup,
940 .exit = __devexit_p(sbs_exit),
941 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 /*
Russell King61a116e2006-07-03 15:22:35 +0100943 * SIIG cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 */
945 {
946 .vendor = PCI_VENDOR_ID_SIIG,
Russell King67d74b82005-07-27 11:33:03 +0100947 .device = PCI_ANY_ID,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 .subvendor = PCI_ANY_ID,
949 .subdevice = PCI_ANY_ID,
Russell King67d74b82005-07-27 11:33:03 +0100950 .init = pci_siig_init,
Andrey Panin3ec9c592006-02-02 20:15:09 +0000951 .setup = pci_siig_setup,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952 },
953 /*
954 * Titan cards
955 */
956 {
957 .vendor = PCI_VENDOR_ID_TITAN,
958 .device = PCI_DEVICE_ID_TITAN_400L,
959 .subvendor = PCI_ANY_ID,
960 .subdevice = PCI_ANY_ID,
961 .setup = titan_400l_800l_setup,
962 },
963 {
964 .vendor = PCI_VENDOR_ID_TITAN,
965 .device = PCI_DEVICE_ID_TITAN_800L,
966 .subvendor = PCI_ANY_ID,
967 .subdevice = PCI_ANY_ID,
968 .setup = titan_400l_800l_setup,
969 },
970 /*
971 * Timedia cards
972 */
973 {
974 .vendor = PCI_VENDOR_ID_TIMEDIA,
975 .device = PCI_DEVICE_ID_TIMEDIA_1889,
976 .subvendor = PCI_VENDOR_ID_TIMEDIA,
977 .subdevice = PCI_ANY_ID,
978 .init = pci_timedia_init,
979 .setup = pci_timedia_setup,
980 },
981 {
982 .vendor = PCI_VENDOR_ID_TIMEDIA,
983 .device = PCI_ANY_ID,
984 .subvendor = PCI_ANY_ID,
985 .subdevice = PCI_ANY_ID,
986 .setup = pci_timedia_setup,
987 },
988 /*
989 * Xircom cards
990 */
991 {
992 .vendor = PCI_VENDOR_ID_XIRCOM,
993 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .init = pci_xircom_init,
997 .setup = pci_default_setup,
998 },
999 /*
Russell King61a116e2006-07-03 15:22:35 +01001000 * Netmos cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 */
1002 {
1003 .vendor = PCI_VENDOR_ID_NETMOS,
1004 .device = PCI_ANY_ID,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .init = pci_netmos_init,
1008 .setup = pci_default_setup,
1009 },
1010 /*
1011 * Default "match everything" terminator entry
1012 */
1013 {
1014 .vendor = PCI_ANY_ID,
1015 .device = PCI_ANY_ID,
1016 .subvendor = PCI_ANY_ID,
1017 .subdevice = PCI_ANY_ID,
1018 .setup = pci_default_setup,
1019 }
1020};
1021
1022static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1023{
1024 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1025}
1026
1027static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1028{
1029 struct pci_serial_quirk *quirk;
1030
1031 for (quirk = pci_serial_quirks; ; quirk++)
1032 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1033 quirk_id_matches(quirk->device, dev->device) &&
1034 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1035 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
Alan Cox5756ee92008-02-08 04:18:51 -08001036 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 return quirk;
1038}
1039
Andrew Mortondd68e882006-01-05 10:55:26 +00001040static inline int get_pci_irq(struct pci_dev *dev,
1041 struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042{
1043 if (board->flags & FL_NOIRQ)
1044 return 0;
1045 else
1046 return dev->irq;
1047}
1048
1049/*
1050 * This is the configuration table for all of the PCI serial boards
1051 * which we support. It is directly indexed by the pci_board_num_t enum
1052 * value, which is encoded in the pci_device_id PCI probe table's
1053 * driver_data member.
1054 *
1055 * The makeup of these names are:
Gareth Howlett26e92862006-01-04 17:00:42 +00001056 * pbn_bn{_bt}_n_baud{_offsetinhex}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001058 * bn = PCI BAR number
1059 * bt = Index using PCI BARs
1060 * n = number of serial ports
1061 * baud = baud rate
1062 * offsetinhex = offset for each sequential port (in hex)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001064 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
Russell Kingf1690f32005-05-06 10:19:09 +01001065 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 * Please note: in theory if n = 1, _bt infix should make no difference.
1067 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1068 */
1069enum pci_board_num_t {
1070 pbn_default = 0,
1071
1072 pbn_b0_1_115200,
1073 pbn_b0_2_115200,
1074 pbn_b0_4_115200,
1075 pbn_b0_5_115200,
Alan Coxbf0df632007-10-16 01:24:00 -07001076 pbn_b0_8_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077
1078 pbn_b0_1_921600,
1079 pbn_b0_2_921600,
1080 pbn_b0_4_921600,
1081
David Ransondb1de152005-07-27 11:43:55 -07001082 pbn_b0_2_1130000,
1083
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001084 pbn_b0_4_1152000,
1085
Gareth Howlett26e92862006-01-04 17:00:42 +00001086 pbn_b0_2_1843200,
1087 pbn_b0_4_1843200,
1088
1089 pbn_b0_2_1843200_200,
1090 pbn_b0_4_1843200_200,
1091 pbn_b0_8_1843200_200,
1092
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 pbn_b0_bt_1_115200,
1094 pbn_b0_bt_2_115200,
1095 pbn_b0_bt_8_115200,
1096
1097 pbn_b0_bt_1_460800,
1098 pbn_b0_bt_2_460800,
1099 pbn_b0_bt_4_460800,
1100
1101 pbn_b0_bt_1_921600,
1102 pbn_b0_bt_2_921600,
1103 pbn_b0_bt_4_921600,
1104 pbn_b0_bt_8_921600,
1105
1106 pbn_b1_1_115200,
1107 pbn_b1_2_115200,
1108 pbn_b1_4_115200,
1109 pbn_b1_8_115200,
1110
1111 pbn_b1_1_921600,
1112 pbn_b1_2_921600,
1113 pbn_b1_4_921600,
1114 pbn_b1_8_921600,
1115
Gareth Howlett26e92862006-01-04 17:00:42 +00001116 pbn_b1_2_1250000,
1117
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001118 pbn_b1_bt_1_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119 pbn_b1_bt_2_921600,
1120
1121 pbn_b1_1_1382400,
1122 pbn_b1_2_1382400,
1123 pbn_b1_4_1382400,
1124 pbn_b1_8_1382400,
1125
1126 pbn_b2_1_115200,
Peter Horton737c1752006-08-26 09:07:36 +01001127 pbn_b2_2_115200,
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001128 pbn_b2_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 pbn_b2_8_115200,
1130
1131 pbn_b2_1_460800,
1132 pbn_b2_4_460800,
1133 pbn_b2_8_460800,
1134 pbn_b2_16_460800,
1135
1136 pbn_b2_1_921600,
1137 pbn_b2_4_921600,
1138 pbn_b2_8_921600,
1139
1140 pbn_b2_bt_1_115200,
1141 pbn_b2_bt_2_115200,
1142 pbn_b2_bt_4_115200,
1143
1144 pbn_b2_bt_2_921600,
1145 pbn_b2_bt_4_921600,
1146
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001147 pbn_b3_2_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148 pbn_b3_4_115200,
1149 pbn_b3_8_115200,
1150
1151 /*
1152 * Board-specific versions.
1153 */
1154 pbn_panacom,
1155 pbn_panacom2,
1156 pbn_panacom4,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001157 pbn_exsys_4055,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 pbn_plx_romulus,
1159 pbn_oxsemi,
1160 pbn_intel_i960,
1161 pbn_sgi_ioc3,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162 pbn_computone_4,
1163 pbn_computone_6,
1164 pbn_computone_8,
1165 pbn_sbsxrsio,
1166 pbn_exar_XR17C152,
1167 pbn_exar_XR17C154,
1168 pbn_exar_XR17C158,
Olof Johanssonaa798502007-08-22 14:01:55 -07001169 pbn_pasemi_1682M,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170};
1171
1172/*
1173 * uart_offset - the space between channels
1174 * reg_shift - describes how the UART registers are mapped
1175 * to PCI memory by the card.
1176 * For example IER register on SBS, Inc. PMC-OctPro is located at
1177 * offset 0x10 from the UART base, while UART_IER is defined as 1
1178 * in include/linux/serial_reg.h,
1179 * see first lines of serial_in() and serial_out() in 8250.c
1180*/
1181
Russell King1c7c1fe2005-07-27 11:31:19 +01001182static struct pciserial_board pci_boards[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 [pbn_default] = {
1184 .flags = FL_BASE0,
1185 .num_ports = 1,
1186 .base_baud = 115200,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b0_1_115200] = {
1190 .flags = FL_BASE0,
1191 .num_ports = 1,
1192 .base_baud = 115200,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b0_2_115200] = {
1196 .flags = FL_BASE0,
1197 .num_ports = 2,
1198 .base_baud = 115200,
1199 .uart_offset = 8,
1200 },
1201 [pbn_b0_4_115200] = {
1202 .flags = FL_BASE0,
1203 .num_ports = 4,
1204 .base_baud = 115200,
1205 .uart_offset = 8,
1206 },
1207 [pbn_b0_5_115200] = {
1208 .flags = FL_BASE0,
1209 .num_ports = 5,
1210 .base_baud = 115200,
1211 .uart_offset = 8,
1212 },
Alan Coxbf0df632007-10-16 01:24:00 -07001213 [pbn_b0_8_115200] = {
1214 .flags = FL_BASE0,
1215 .num_ports = 8,
1216 .base_baud = 115200,
1217 .uart_offset = 8,
1218 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219 [pbn_b0_1_921600] = {
1220 .flags = FL_BASE0,
1221 .num_ports = 1,
1222 .base_baud = 921600,
1223 .uart_offset = 8,
1224 },
1225 [pbn_b0_2_921600] = {
1226 .flags = FL_BASE0,
1227 .num_ports = 2,
1228 .base_baud = 921600,
1229 .uart_offset = 8,
1230 },
1231 [pbn_b0_4_921600] = {
1232 .flags = FL_BASE0,
1233 .num_ports = 4,
1234 .base_baud = 921600,
1235 .uart_offset = 8,
1236 },
David Ransondb1de152005-07-27 11:43:55 -07001237
1238 [pbn_b0_2_1130000] = {
1239 .flags = FL_BASE0,
1240 .num_ports = 2,
1241 .base_baud = 1130000,
1242 .uart_offset = 8,
1243 },
1244
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001245 [pbn_b0_4_1152000] = {
1246 .flags = FL_BASE0,
1247 .num_ports = 4,
1248 .base_baud = 1152000,
1249 .uart_offset = 8,
1250 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251
Gareth Howlett26e92862006-01-04 17:00:42 +00001252 [pbn_b0_2_1843200] = {
1253 .flags = FL_BASE0,
1254 .num_ports = 2,
1255 .base_baud = 1843200,
1256 .uart_offset = 8,
1257 },
1258 [pbn_b0_4_1843200] = {
1259 .flags = FL_BASE0,
1260 .num_ports = 4,
1261 .base_baud = 1843200,
1262 .uart_offset = 8,
1263 },
1264
1265 [pbn_b0_2_1843200_200] = {
1266 .flags = FL_BASE0,
1267 .num_ports = 2,
1268 .base_baud = 1843200,
1269 .uart_offset = 0x200,
1270 },
1271 [pbn_b0_4_1843200_200] = {
1272 .flags = FL_BASE0,
1273 .num_ports = 4,
1274 .base_baud = 1843200,
1275 .uart_offset = 0x200,
1276 },
1277 [pbn_b0_8_1843200_200] = {
1278 .flags = FL_BASE0,
1279 .num_ports = 8,
1280 .base_baud = 1843200,
1281 .uart_offset = 0x200,
1282 },
1283
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284 [pbn_b0_bt_1_115200] = {
1285 .flags = FL_BASE0|FL_BASE_BARS,
1286 .num_ports = 1,
1287 .base_baud = 115200,
1288 .uart_offset = 8,
1289 },
1290 [pbn_b0_bt_2_115200] = {
1291 .flags = FL_BASE0|FL_BASE_BARS,
1292 .num_ports = 2,
1293 .base_baud = 115200,
1294 .uart_offset = 8,
1295 },
1296 [pbn_b0_bt_8_115200] = {
1297 .flags = FL_BASE0|FL_BASE_BARS,
1298 .num_ports = 8,
1299 .base_baud = 115200,
1300 .uart_offset = 8,
1301 },
1302
1303 [pbn_b0_bt_1_460800] = {
1304 .flags = FL_BASE0|FL_BASE_BARS,
1305 .num_ports = 1,
1306 .base_baud = 460800,
1307 .uart_offset = 8,
1308 },
1309 [pbn_b0_bt_2_460800] = {
1310 .flags = FL_BASE0|FL_BASE_BARS,
1311 .num_ports = 2,
1312 .base_baud = 460800,
1313 .uart_offset = 8,
1314 },
1315 [pbn_b0_bt_4_460800] = {
1316 .flags = FL_BASE0|FL_BASE_BARS,
1317 .num_ports = 4,
1318 .base_baud = 460800,
1319 .uart_offset = 8,
1320 },
1321
1322 [pbn_b0_bt_1_921600] = {
1323 .flags = FL_BASE0|FL_BASE_BARS,
1324 .num_ports = 1,
1325 .base_baud = 921600,
1326 .uart_offset = 8,
1327 },
1328 [pbn_b0_bt_2_921600] = {
1329 .flags = FL_BASE0|FL_BASE_BARS,
1330 .num_ports = 2,
1331 .base_baud = 921600,
1332 .uart_offset = 8,
1333 },
1334 [pbn_b0_bt_4_921600] = {
1335 .flags = FL_BASE0|FL_BASE_BARS,
1336 .num_ports = 4,
1337 .base_baud = 921600,
1338 .uart_offset = 8,
1339 },
1340 [pbn_b0_bt_8_921600] = {
1341 .flags = FL_BASE0|FL_BASE_BARS,
1342 .num_ports = 8,
1343 .base_baud = 921600,
1344 .uart_offset = 8,
1345 },
1346
1347 [pbn_b1_1_115200] = {
1348 .flags = FL_BASE1,
1349 .num_ports = 1,
1350 .base_baud = 115200,
1351 .uart_offset = 8,
1352 },
1353 [pbn_b1_2_115200] = {
1354 .flags = FL_BASE1,
1355 .num_ports = 2,
1356 .base_baud = 115200,
1357 .uart_offset = 8,
1358 },
1359 [pbn_b1_4_115200] = {
1360 .flags = FL_BASE1,
1361 .num_ports = 4,
1362 .base_baud = 115200,
1363 .uart_offset = 8,
1364 },
1365 [pbn_b1_8_115200] = {
1366 .flags = FL_BASE1,
1367 .num_ports = 8,
1368 .base_baud = 115200,
1369 .uart_offset = 8,
1370 },
1371
1372 [pbn_b1_1_921600] = {
1373 .flags = FL_BASE1,
1374 .num_ports = 1,
1375 .base_baud = 921600,
1376 .uart_offset = 8,
1377 },
1378 [pbn_b1_2_921600] = {
1379 .flags = FL_BASE1,
1380 .num_ports = 2,
1381 .base_baud = 921600,
1382 .uart_offset = 8,
1383 },
1384 [pbn_b1_4_921600] = {
1385 .flags = FL_BASE1,
1386 .num_ports = 4,
1387 .base_baud = 921600,
1388 .uart_offset = 8,
1389 },
1390 [pbn_b1_8_921600] = {
1391 .flags = FL_BASE1,
1392 .num_ports = 8,
1393 .base_baud = 921600,
1394 .uart_offset = 8,
1395 },
Gareth Howlett26e92862006-01-04 17:00:42 +00001396 [pbn_b1_2_1250000] = {
1397 .flags = FL_BASE1,
1398 .num_ports = 2,
1399 .base_baud = 1250000,
1400 .uart_offset = 8,
1401 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001403 [pbn_b1_bt_1_115200] = {
1404 .flags = FL_BASE1|FL_BASE_BARS,
1405 .num_ports = 1,
1406 .base_baud = 115200,
1407 .uart_offset = 8,
1408 },
1409
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 [pbn_b1_bt_2_921600] = {
1411 .flags = FL_BASE1|FL_BASE_BARS,
1412 .num_ports = 2,
1413 .base_baud = 921600,
1414 .uart_offset = 8,
1415 },
1416
1417 [pbn_b1_1_1382400] = {
1418 .flags = FL_BASE1,
1419 .num_ports = 1,
1420 .base_baud = 1382400,
1421 .uart_offset = 8,
1422 },
1423 [pbn_b1_2_1382400] = {
1424 .flags = FL_BASE1,
1425 .num_ports = 2,
1426 .base_baud = 1382400,
1427 .uart_offset = 8,
1428 },
1429 [pbn_b1_4_1382400] = {
1430 .flags = FL_BASE1,
1431 .num_ports = 4,
1432 .base_baud = 1382400,
1433 .uart_offset = 8,
1434 },
1435 [pbn_b1_8_1382400] = {
1436 .flags = FL_BASE1,
1437 .num_ports = 8,
1438 .base_baud = 1382400,
1439 .uart_offset = 8,
1440 },
1441
1442 [pbn_b2_1_115200] = {
1443 .flags = FL_BASE2,
1444 .num_ports = 1,
1445 .base_baud = 115200,
1446 .uart_offset = 8,
1447 },
Peter Horton737c1752006-08-26 09:07:36 +01001448 [pbn_b2_2_115200] = {
1449 .flags = FL_BASE2,
1450 .num_ports = 2,
1451 .base_baud = 115200,
1452 .uart_offset = 8,
1453 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001454 [pbn_b2_4_115200] = {
1455 .flags = FL_BASE2,
1456 .num_ports = 4,
1457 .base_baud = 115200,
1458 .uart_offset = 8,
1459 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460 [pbn_b2_8_115200] = {
1461 .flags = FL_BASE2,
1462 .num_ports = 8,
1463 .base_baud = 115200,
1464 .uart_offset = 8,
1465 },
1466
1467 [pbn_b2_1_460800] = {
1468 .flags = FL_BASE2,
1469 .num_ports = 1,
1470 .base_baud = 460800,
1471 .uart_offset = 8,
1472 },
1473 [pbn_b2_4_460800] = {
1474 .flags = FL_BASE2,
1475 .num_ports = 4,
1476 .base_baud = 460800,
1477 .uart_offset = 8,
1478 },
1479 [pbn_b2_8_460800] = {
1480 .flags = FL_BASE2,
1481 .num_ports = 8,
1482 .base_baud = 460800,
1483 .uart_offset = 8,
1484 },
1485 [pbn_b2_16_460800] = {
1486 .flags = FL_BASE2,
1487 .num_ports = 16,
1488 .base_baud = 460800,
1489 .uart_offset = 8,
1490 },
1491
1492 [pbn_b2_1_921600] = {
1493 .flags = FL_BASE2,
1494 .num_ports = 1,
1495 .base_baud = 921600,
1496 .uart_offset = 8,
1497 },
1498 [pbn_b2_4_921600] = {
1499 .flags = FL_BASE2,
1500 .num_ports = 4,
1501 .base_baud = 921600,
1502 .uart_offset = 8,
1503 },
1504 [pbn_b2_8_921600] = {
1505 .flags = FL_BASE2,
1506 .num_ports = 8,
1507 .base_baud = 921600,
1508 .uart_offset = 8,
1509 },
1510
1511 [pbn_b2_bt_1_115200] = {
1512 .flags = FL_BASE2|FL_BASE_BARS,
1513 .num_ports = 1,
1514 .base_baud = 115200,
1515 .uart_offset = 8,
1516 },
1517 [pbn_b2_bt_2_115200] = {
1518 .flags = FL_BASE2|FL_BASE_BARS,
1519 .num_ports = 2,
1520 .base_baud = 115200,
1521 .uart_offset = 8,
1522 },
1523 [pbn_b2_bt_4_115200] = {
1524 .flags = FL_BASE2|FL_BASE_BARS,
1525 .num_ports = 4,
1526 .base_baud = 115200,
1527 .uart_offset = 8,
1528 },
1529
1530 [pbn_b2_bt_2_921600] = {
1531 .flags = FL_BASE2|FL_BASE_BARS,
1532 .num_ports = 2,
1533 .base_baud = 921600,
1534 .uart_offset = 8,
1535 },
1536 [pbn_b2_bt_4_921600] = {
1537 .flags = FL_BASE2|FL_BASE_BARS,
1538 .num_ports = 4,
1539 .base_baud = 921600,
1540 .uart_offset = 8,
1541 },
1542
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001543 [pbn_b3_2_115200] = {
1544 .flags = FL_BASE3,
1545 .num_ports = 2,
1546 .base_baud = 115200,
1547 .uart_offset = 8,
1548 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 [pbn_b3_4_115200] = {
1550 .flags = FL_BASE3,
1551 .num_ports = 4,
1552 .base_baud = 115200,
1553 .uart_offset = 8,
1554 },
1555 [pbn_b3_8_115200] = {
1556 .flags = FL_BASE3,
1557 .num_ports = 8,
1558 .base_baud = 115200,
1559 .uart_offset = 8,
1560 },
1561
1562 /*
1563 * Entries following this are board-specific.
1564 */
1565
1566 /*
1567 * Panacom - IOMEM
1568 */
1569 [pbn_panacom] = {
1570 .flags = FL_BASE2,
1571 .num_ports = 2,
1572 .base_baud = 921600,
1573 .uart_offset = 0x400,
1574 .reg_shift = 7,
1575 },
1576 [pbn_panacom2] = {
1577 .flags = FL_BASE2|FL_BASE_BARS,
1578 .num_ports = 2,
1579 .base_baud = 921600,
1580 .uart_offset = 0x400,
1581 .reg_shift = 7,
1582 },
1583 [pbn_panacom4] = {
1584 .flags = FL_BASE2|FL_BASE_BARS,
1585 .num_ports = 4,
1586 .base_baud = 921600,
1587 .uart_offset = 0x400,
1588 .reg_shift = 7,
1589 },
1590
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001591 [pbn_exsys_4055] = {
1592 .flags = FL_BASE2,
1593 .num_ports = 4,
1594 .base_baud = 115200,
1595 .uart_offset = 8,
1596 },
1597
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598 /* I think this entry is broken - the first_offset looks wrong --rmk */
1599 [pbn_plx_romulus] = {
1600 .flags = FL_BASE2,
1601 .num_ports = 4,
1602 .base_baud = 921600,
1603 .uart_offset = 8 << 2,
1604 .reg_shift = 2,
1605 .first_offset = 0x03,
1606 },
1607
1608 /*
1609 * This board uses the size of PCI Base region 0 to
1610 * signal now many ports are available
1611 */
1612 [pbn_oxsemi] = {
1613 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1614 .num_ports = 32,
1615 .base_baud = 115200,
1616 .uart_offset = 8,
1617 },
1618
1619 /*
1620 * EKF addition for i960 Boards form EKF with serial port.
1621 * Max 256 ports.
1622 */
1623 [pbn_intel_i960] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 32,
1626 .base_baud = 921600,
1627 .uart_offset = 8 << 2,
1628 .reg_shift = 2,
1629 .first_offset = 0x10000,
1630 },
1631 [pbn_sgi_ioc3] = {
1632 .flags = FL_BASE0|FL_NOIRQ,
1633 .num_ports = 1,
1634 .base_baud = 458333,
1635 .uart_offset = 8,
1636 .reg_shift = 0,
1637 .first_offset = 0x20178,
1638 },
1639
1640 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001641 * Computone - uses IOMEM.
1642 */
1643 [pbn_computone_4] = {
1644 .flags = FL_BASE0,
1645 .num_ports = 4,
1646 .base_baud = 921600,
1647 .uart_offset = 0x40,
1648 .reg_shift = 2,
1649 .first_offset = 0x200,
1650 },
1651 [pbn_computone_6] = {
1652 .flags = FL_BASE0,
1653 .num_ports = 6,
1654 .base_baud = 921600,
1655 .uart_offset = 0x40,
1656 .reg_shift = 2,
1657 .first_offset = 0x200,
1658 },
1659 [pbn_computone_8] = {
1660 .flags = FL_BASE0,
1661 .num_ports = 8,
1662 .base_baud = 921600,
1663 .uart_offset = 0x40,
1664 .reg_shift = 2,
1665 .first_offset = 0x200,
1666 },
1667 [pbn_sbsxrsio] = {
1668 .flags = FL_BASE0,
1669 .num_ports = 8,
1670 .base_baud = 460800,
1671 .uart_offset = 256,
1672 .reg_shift = 4,
1673 },
1674 /*
1675 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1676 * Only basic 16550A support.
1677 * XR17C15[24] are not tested, but they should work.
1678 */
1679 [pbn_exar_XR17C152] = {
1680 .flags = FL_BASE0,
1681 .num_ports = 2,
1682 .base_baud = 921600,
1683 .uart_offset = 0x200,
1684 },
1685 [pbn_exar_XR17C154] = {
1686 .flags = FL_BASE0,
1687 .num_ports = 4,
1688 .base_baud = 921600,
1689 .uart_offset = 0x200,
1690 },
1691 [pbn_exar_XR17C158] = {
1692 .flags = FL_BASE0,
1693 .num_ports = 8,
1694 .base_baud = 921600,
1695 .uart_offset = 0x200,
1696 },
Olof Johanssonaa798502007-08-22 14:01:55 -07001697 /*
1698 * PA Semi PWRficient PA6T-1682M on-chip UART
1699 */
1700 [pbn_pasemi_1682M] = {
1701 .flags = FL_BASE0,
1702 .num_ports = 1,
1703 .base_baud = 8333333,
1704 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705};
1706
Christian Schmidt436bbd42007-08-22 14:01:19 -07001707static const struct pci_device_id softmodem_blacklist[] = {
Alan Cox5756ee92008-02-08 04:18:51 -08001708 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
Christian Schmidt436bbd42007-08-22 14:01:19 -07001709};
1710
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711/*
1712 * Given a complete unknown PCI device, try to use some heuristics to
1713 * guess what the configuration might be, based on the pitiful PCI
1714 * serial specs. Returns 0 on success, 1 on failure.
1715 */
1716static int __devinit
Russell King1c7c1fe2005-07-27 11:31:19 +01001717serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718{
Christian Schmidt436bbd42007-08-22 14:01:19 -07001719 const struct pci_device_id *blacklist;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720 int num_iomem, num_port, first_port = -1, i;
Alan Cox5756ee92008-02-08 04:18:51 -08001721
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722 /*
1723 * If it is not a communications device or the programming
1724 * interface is greater than 6, give up.
1725 *
1726 * (Should we try to make guesses for multiport serial devices
Alan Cox5756ee92008-02-08 04:18:51 -08001727 * later?)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 */
1729 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1730 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1731 (dev->class & 0xff) > 6)
1732 return -ENODEV;
1733
Christian Schmidt436bbd42007-08-22 14:01:19 -07001734 /*
1735 * Do not access blacklisted devices that are known not to
1736 * feature serial ports.
1737 */
1738 for (blacklist = softmodem_blacklist;
1739 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1740 blacklist++) {
1741 if (dev->vendor == blacklist->vendor &&
1742 dev->device == blacklist->device)
1743 return -ENODEV;
1744 }
1745
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 num_iomem = num_port = 0;
1747 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1748 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1749 num_port++;
1750 if (first_port == -1)
1751 first_port = i;
1752 }
1753 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1754 num_iomem++;
1755 }
1756
1757 /*
1758 * If there is 1 or 0 iomem regions, and exactly one port,
1759 * use it. We guess the number of ports based on the IO
1760 * region size.
1761 */
1762 if (num_iomem <= 1 && num_port == 1) {
1763 board->flags = first_port;
1764 board->num_ports = pci_resource_len(dev, first_port) / 8;
1765 return 0;
1766 }
1767
1768 /*
1769 * Now guess if we've got a board which indexes by BARs.
1770 * Each IO BAR should be 8 bytes, and they should follow
1771 * consecutively.
1772 */
1773 first_port = -1;
1774 num_port = 0;
1775 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1776 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1777 pci_resource_len(dev, i) == 8 &&
1778 (first_port == -1 || (first_port + num_port) == i)) {
1779 num_port++;
1780 if (first_port == -1)
1781 first_port = i;
1782 }
1783 }
1784
1785 if (num_port > 1) {
1786 board->flags = first_port | FL_BASE_BARS;
1787 board->num_ports = num_port;
1788 return 0;
1789 }
1790
1791 return -ENODEV;
1792}
1793
1794static inline int
Russell King1c7c1fe2005-07-27 11:31:19 +01001795serial_pci_matches(struct pciserial_board *board,
1796 struct pciserial_board *guessed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797{
1798 return
1799 board->num_ports == guessed->num_ports &&
1800 board->base_baud == guessed->base_baud &&
1801 board->uart_offset == guessed->uart_offset &&
1802 board->reg_shift == guessed->reg_shift &&
1803 board->first_offset == guessed->first_offset;
1804}
1805
Russell King241fc432005-07-27 11:35:54 +01001806struct serial_private *
1807pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1808{
1809 struct uart_port serial_port;
1810 struct serial_private *priv;
1811 struct pci_serial_quirk *quirk;
1812 int rc, nr_ports, i;
1813
1814 nr_ports = board->num_ports;
1815
1816 /*
1817 * Find an init and setup quirks.
1818 */
1819 quirk = find_quirk(dev);
1820
1821 /*
1822 * Run the new-style initialization function.
1823 * The initialization function returns:
1824 * <0 - error
1825 * 0 - use board->num_ports
1826 * >0 - number of ports
1827 */
1828 if (quirk->init) {
1829 rc = quirk->init(dev);
1830 if (rc < 0) {
1831 priv = ERR_PTR(rc);
1832 goto err_out;
1833 }
1834 if (rc)
1835 nr_ports = rc;
1836 }
1837
Burman Yan8f31bb32007-02-14 00:33:07 -08001838 priv = kzalloc(sizeof(struct serial_private) +
Russell King241fc432005-07-27 11:35:54 +01001839 sizeof(unsigned int) * nr_ports,
1840 GFP_KERNEL);
1841 if (!priv) {
1842 priv = ERR_PTR(-ENOMEM);
1843 goto err_deinit;
1844 }
1845
Russell King241fc432005-07-27 11:35:54 +01001846 priv->dev = dev;
1847 priv->quirk = quirk;
1848
1849 memset(&serial_port, 0, sizeof(struct uart_port));
1850 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1851 serial_port.uartclk = board->base_baud * 16;
1852 serial_port.irq = get_pci_irq(dev, board);
1853 serial_port.dev = &dev->dev;
1854
1855 for (i = 0; i < nr_ports; i++) {
1856 if (quirk->setup(priv, board, &serial_port, i))
1857 break;
1858
1859#ifdef SERIAL_DEBUG_PCI
Alan Cox5756ee92008-02-08 04:18:51 -08001860 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
Russell King241fc432005-07-27 11:35:54 +01001861 serial_port.iobase, serial_port.irq, serial_port.iotype);
1862#endif
Alan Cox5756ee92008-02-08 04:18:51 -08001863
Russell King241fc432005-07-27 11:35:54 +01001864 priv->line[i] = serial8250_register_port(&serial_port);
1865 if (priv->line[i] < 0) {
1866 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1867 break;
1868 }
1869 }
Russell King241fc432005-07-27 11:35:54 +01001870 priv->nr = i;
Russell King241fc432005-07-27 11:35:54 +01001871 return priv;
1872
Alan Cox5756ee92008-02-08 04:18:51 -08001873err_deinit:
Russell King241fc432005-07-27 11:35:54 +01001874 if (quirk->exit)
1875 quirk->exit(dev);
Alan Cox5756ee92008-02-08 04:18:51 -08001876err_out:
Russell King241fc432005-07-27 11:35:54 +01001877 return priv;
1878}
1879EXPORT_SYMBOL_GPL(pciserial_init_ports);
1880
1881void pciserial_remove_ports(struct serial_private *priv)
1882{
1883 struct pci_serial_quirk *quirk;
1884 int i;
1885
1886 for (i = 0; i < priv->nr; i++)
1887 serial8250_unregister_port(priv->line[i]);
1888
1889 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1890 if (priv->remapped_bar[i])
1891 iounmap(priv->remapped_bar[i]);
1892 priv->remapped_bar[i] = NULL;
1893 }
1894
1895 /*
1896 * Find the exit quirks.
1897 */
1898 quirk = find_quirk(priv->dev);
1899 if (quirk->exit)
1900 quirk->exit(priv->dev);
1901
1902 kfree(priv);
1903}
1904EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1905
1906void pciserial_suspend_ports(struct serial_private *priv)
1907{
1908 int i;
1909
1910 for (i = 0; i < priv->nr; i++)
1911 if (priv->line[i] >= 0)
1912 serial8250_suspend_port(priv->line[i]);
1913}
1914EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1915
1916void pciserial_resume_ports(struct serial_private *priv)
1917{
1918 int i;
1919
1920 /*
1921 * Ensure that the board is correctly configured.
1922 */
1923 if (priv->quirk->init)
1924 priv->quirk->init(priv->dev);
1925
1926 for (i = 0; i < priv->nr; i++)
1927 if (priv->line[i] >= 0)
1928 serial8250_resume_port(priv->line[i]);
1929}
1930EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1931
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932/*
1933 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1934 * to the arrangement of serial ports on a PCI card.
1935 */
1936static int __devinit
1937pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1938{
1939 struct serial_private *priv;
Russell King1c7c1fe2005-07-27 11:31:19 +01001940 struct pciserial_board *board, tmp;
Russell King241fc432005-07-27 11:35:54 +01001941 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942
1943 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1944 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1945 ent->driver_data);
1946 return -EINVAL;
1947 }
1948
1949 board = &pci_boards[ent->driver_data];
1950
1951 rc = pci_enable_device(dev);
1952 if (rc)
1953 return rc;
1954
1955 if (ent->driver_data == pbn_default) {
1956 /*
1957 * Use a copy of the pci_board entry for this;
1958 * avoid changing entries in the table.
1959 */
Russell King1c7c1fe2005-07-27 11:31:19 +01001960 memcpy(&tmp, board, sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961 board = &tmp;
1962
1963 /*
1964 * We matched one of our class entries. Try to
1965 * determine the parameters of this board.
1966 */
1967 rc = serial_pci_guess_board(dev, board);
1968 if (rc)
1969 goto disable;
1970 } else {
1971 /*
1972 * We matched an explicit entry. If we are able to
1973 * detect this boards settings with our heuristic,
1974 * then we no longer need this entry.
1975 */
Russell King1c7c1fe2005-07-27 11:31:19 +01001976 memcpy(&tmp, &pci_boards[pbn_default],
1977 sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001978 rc = serial_pci_guess_board(dev, &tmp);
1979 if (rc == 0 && serial_pci_matches(board, &tmp))
1980 moan_device("Redundant entry in serial pci_table.",
1981 dev);
1982 }
1983
Russell King241fc432005-07-27 11:35:54 +01001984 priv = pciserial_init_ports(dev, board);
1985 if (!IS_ERR(priv)) {
1986 pci_set_drvdata(dev, priv);
1987 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001988 }
1989
Russell King241fc432005-07-27 11:35:54 +01001990 rc = PTR_ERR(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001991
Linus Torvalds1da177e2005-04-16 15:20:36 -07001992 disable:
1993 pci_disable_device(dev);
1994 return rc;
1995}
1996
1997static void __devexit pciserial_remove_one(struct pci_dev *dev)
1998{
1999 struct serial_private *priv = pci_get_drvdata(dev);
2000
2001 pci_set_drvdata(dev, NULL);
2002
Russell King241fc432005-07-27 11:35:54 +01002003 pciserial_remove_ports(priv);
Russell King056a8762005-07-22 10:15:04 +01002004
2005 pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002006}
2007
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002008#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002009static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2010{
2011 struct serial_private *priv = pci_get_drvdata(dev);
2012
Russell King241fc432005-07-27 11:35:54 +01002013 if (priv)
2014 pciserial_suspend_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015
Linus Torvalds1da177e2005-04-16 15:20:36 -07002016 pci_save_state(dev);
2017 pci_set_power_state(dev, pci_choose_state(dev, state));
2018 return 0;
2019}
2020
2021static int pciserial_resume_one(struct pci_dev *dev)
2022{
Dirk Hohndelccb9d592007-10-29 06:28:17 -07002023 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024 struct serial_private *priv = pci_get_drvdata(dev);
2025
2026 pci_set_power_state(dev, PCI_D0);
2027 pci_restore_state(dev);
2028
2029 if (priv) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002030 /*
2031 * The device may have been disabled. Re-enable it.
2032 */
Dirk Hohndelccb9d592007-10-29 06:28:17 -07002033 err = pci_enable_device(dev);
2034 if (err)
2035 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036
Russell King241fc432005-07-27 11:35:54 +01002037 pciserial_resume_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 }
2039 return 0;
2040}
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002041#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002042
2043static struct pci_device_id serial_pci_tbl[] = {
2044 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2045 PCI_SUBVENDOR_ID_CONNECT_TECH,
2046 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2047 pbn_b1_8_1382400 },
2048 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2049 PCI_SUBVENDOR_ID_CONNECT_TECH,
2050 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2051 pbn_b1_4_1382400 },
2052 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2053 PCI_SUBVENDOR_ID_CONNECT_TECH,
2054 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2055 pbn_b1_2_1382400 },
2056 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2057 PCI_SUBVENDOR_ID_CONNECT_TECH,
2058 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2059 pbn_b1_8_1382400 },
2060 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2061 PCI_SUBVENDOR_ID_CONNECT_TECH,
2062 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2063 pbn_b1_4_1382400 },
2064 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2065 PCI_SUBVENDOR_ID_CONNECT_TECH,
2066 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2067 pbn_b1_2_1382400 },
2068 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2069 PCI_SUBVENDOR_ID_CONNECT_TECH,
2070 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2071 pbn_b1_8_921600 },
2072 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2073 PCI_SUBVENDOR_ID_CONNECT_TECH,
2074 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2075 pbn_b1_8_921600 },
2076 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2077 PCI_SUBVENDOR_ID_CONNECT_TECH,
2078 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2079 pbn_b1_4_921600 },
2080 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2081 PCI_SUBVENDOR_ID_CONNECT_TECH,
2082 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2083 pbn_b1_4_921600 },
2084 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2085 PCI_SUBVENDOR_ID_CONNECT_TECH,
2086 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2087 pbn_b1_2_921600 },
2088 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2089 PCI_SUBVENDOR_ID_CONNECT_TECH,
2090 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2091 pbn_b1_8_921600 },
2092 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2093 PCI_SUBVENDOR_ID_CONNECT_TECH,
2094 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2095 pbn_b1_8_921600 },
2096 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2097 PCI_SUBVENDOR_ID_CONNECT_TECH,
2098 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2099 pbn_b1_4_921600 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002100 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2101 PCI_SUBVENDOR_ID_CONNECT_TECH,
2102 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2103 pbn_b1_2_1250000 },
2104 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2105 PCI_SUBVENDOR_ID_CONNECT_TECH,
2106 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2107 pbn_b0_2_1843200 },
2108 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2109 PCI_SUBVENDOR_ID_CONNECT_TECH,
2110 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2111 pbn_b0_4_1843200 },
Yoichi Yuasa85d14942006-02-08 21:46:24 +00002112 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2113 PCI_VENDOR_ID_AFAVLAB,
2114 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2115 pbn_b0_4_1152000 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002116 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2117 PCI_SUBVENDOR_ID_CONNECT_TECH,
2118 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2119 pbn_b0_2_1843200_200 },
2120 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2121 PCI_SUBVENDOR_ID_CONNECT_TECH,
2122 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2123 pbn_b0_4_1843200_200 },
2124 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2125 PCI_SUBVENDOR_ID_CONNECT_TECH,
2126 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2127 pbn_b0_8_1843200_200 },
2128 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2129 PCI_SUBVENDOR_ID_CONNECT_TECH,
2130 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2131 pbn_b0_2_1843200_200 },
2132 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2133 PCI_SUBVENDOR_ID_CONNECT_TECH,
2134 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2135 pbn_b0_4_1843200_200 },
2136 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2137 PCI_SUBVENDOR_ID_CONNECT_TECH,
2138 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2139 pbn_b0_8_1843200_200 },
2140 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2141 PCI_SUBVENDOR_ID_CONNECT_TECH,
2142 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2143 pbn_b0_2_1843200_200 },
2144 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2145 PCI_SUBVENDOR_ID_CONNECT_TECH,
2146 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2147 pbn_b0_4_1843200_200 },
2148 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2149 PCI_SUBVENDOR_ID_CONNECT_TECH,
2150 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2151 pbn_b0_8_1843200_200 },
2152 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2153 PCI_SUBVENDOR_ID_CONNECT_TECH,
2154 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2155 pbn_b0_2_1843200_200 },
2156 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2157 PCI_SUBVENDOR_ID_CONNECT_TECH,
2158 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2159 pbn_b0_4_1843200_200 },
2160 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2161 PCI_SUBVENDOR_ID_CONNECT_TECH,
2162 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2163 pbn_b0_8_1843200_200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002164
2165 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
Alan Cox5756ee92008-02-08 04:18:51 -08002166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167 pbn_b2_bt_1_115200 },
2168 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
Alan Cox5756ee92008-02-08 04:18:51 -08002169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170 pbn_b2_bt_2_115200 },
2171 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
Alan Cox5756ee92008-02-08 04:18:51 -08002172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 pbn_b2_bt_4_115200 },
2174 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
Alan Cox5756ee92008-02-08 04:18:51 -08002175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176 pbn_b2_bt_2_115200 },
2177 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
Alan Cox5756ee92008-02-08 04:18:51 -08002178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179 pbn_b2_bt_4_115200 },
2180 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
Alan Cox5756ee92008-02-08 04:18:51 -08002181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002182 pbn_b2_8_115200 },
2183 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2185 pbn_b2_8_115200 },
2186
2187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189 pbn_b2_bt_2_115200 },
2190 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192 pbn_b2_bt_2_921600 },
2193 /*
2194 * VScom SPCOM800, from sl@s.pl
2195 */
Alan Cox5756ee92008-02-08 04:18:51 -08002196 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002198 pbn_b2_8_921600 },
2199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
Alan Cox5756ee92008-02-08 04:18:51 -08002200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002201 pbn_b2_4_921600 },
2202 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2203 PCI_SUBVENDOR_ID_KEYSPAN,
2204 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2205 pbn_panacom },
2206 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2208 pbn_panacom4 },
2209 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211 pbn_panacom2 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08002212 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2213 PCI_VENDOR_ID_ESDGMBH,
2214 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2215 pbn_b2_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002216 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2217 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002218 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219 pbn_b2_4_460800 },
2220 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2221 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002222 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223 pbn_b2_8_460800 },
2224 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2225 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002226 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002227 pbn_b2_16_460800 },
2228 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2229 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08002230 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231 pbn_b2_16_460800 },
2232 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2233 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08002234 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235 pbn_b2_4_460800 },
2236 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2237 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08002238 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002239 pbn_b2_8_460800 },
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2241 PCI_SUBVENDOR_ID_EXSYS,
2242 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2243 pbn_exsys_4055 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002244 /*
2245 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2246 * (Exoray@isys.ca)
2247 */
2248 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2249 0x10b5, 0x106a, 0, 0,
2250 pbn_plx_romulus },
2251 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2253 pbn_b1_4_115200 },
2254 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2256 pbn_b1_2_115200 },
2257 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2259 pbn_b1_8_115200 },
2260 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2262 pbn_b1_8_115200 },
2263 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08002264 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2265 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266 pbn_b0_4_921600 },
2267 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08002268 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2269 0, 0,
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002270 pbn_b0_4_1152000 },
David Ransondb1de152005-07-27 11:43:55 -07002271
2272 /*
2273 * The below card is a little controversial since it is the
2274 * subject of a PCI vendor/device ID clash. (See
2275 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2276 * For now just used the hex ID 0x950a.
2277 */
2278 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2280 pbn_b0_2_1130000 },
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002281 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2283 pbn_b0_4_115200 },
2284 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2286 pbn_b0_bt_2_921600 },
2287
2288 /*
2289 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2290 * from skokodyn@yahoo.com
2291 */
2292 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2293 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2294 pbn_sbsxrsio },
2295 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2296 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2297 pbn_sbsxrsio },
2298 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2299 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2300 pbn_sbsxrsio },
2301 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2302 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2303 pbn_sbsxrsio },
2304
2305 /*
2306 * Digitan DS560-558, from jimd@esoft.com
2307 */
2308 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
Alan Cox5756ee92008-02-08 04:18:51 -08002309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002310 pbn_b1_1_115200 },
2311
2312 /*
2313 * Titan Electronic cards
2314 * The 400L and 800L have a custom setup quirk.
2315 */
2316 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
Alan Cox5756ee92008-02-08 04:18:51 -08002317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002318 pbn_b0_1_921600 },
2319 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
Alan Cox5756ee92008-02-08 04:18:51 -08002320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002321 pbn_b0_2_921600 },
2322 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
Alan Cox5756ee92008-02-08 04:18:51 -08002323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002324 pbn_b0_4_921600 },
2325 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
Alan Cox5756ee92008-02-08 04:18:51 -08002326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002327 pbn_b0_4_921600 },
2328 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2330 pbn_b1_1_921600 },
2331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333 pbn_b1_bt_2_921600 },
2334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336 pbn_b0_bt_4_921600 },
2337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339 pbn_b0_bt_8_921600 },
2340
2341 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2343 pbn_b2_1_460800 },
2344 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2346 pbn_b2_1_460800 },
2347 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2349 pbn_b2_1_460800 },
2350 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2352 pbn_b2_bt_2_921600 },
2353 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2355 pbn_b2_bt_2_921600 },
2356 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358 pbn_b2_bt_2_921600 },
2359 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361 pbn_b2_bt_4_921600 },
2362 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364 pbn_b2_bt_4_921600 },
2365 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367 pbn_b2_bt_4_921600 },
2368 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2370 pbn_b0_1_921600 },
2371 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2373 pbn_b0_1_921600 },
2374 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2376 pbn_b0_1_921600 },
2377 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2379 pbn_b0_bt_2_921600 },
2380 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2382 pbn_b0_bt_2_921600 },
2383 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2385 pbn_b0_bt_2_921600 },
2386 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2388 pbn_b0_bt_4_921600 },
2389 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391 pbn_b0_bt_4_921600 },
2392 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394 pbn_b0_bt_4_921600 },
Andrey Panin3ec9c592006-02-02 20:15:09 +00002395 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397 pbn_b0_bt_8_921600 },
2398 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2400 pbn_b0_bt_8_921600 },
2401 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2403 pbn_b0_bt_8_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404
2405 /*
2406 * Computone devices submitted by Doug McNash dmcnash@computone.com
2407 */
2408 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2409 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2410 0, 0, pbn_computone_4 },
2411 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2412 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2413 0, 0, pbn_computone_8 },
2414 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2415 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2416 0, 0, pbn_computone_6 },
2417
2418 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2420 pbn_oxsemi },
2421 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2422 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2423 pbn_b0_bt_1_921600 },
2424
2425 /*
2426 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2427 */
2428 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2430 pbn_b0_bt_8_115200 },
2431 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2433 pbn_b0_bt_8_115200 },
2434
2435 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2437 pbn_b0_bt_2_115200 },
2438 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2440 pbn_b0_bt_2_115200 },
2441 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2443 pbn_b0_bt_2_115200 },
2444 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2446 pbn_b0_bt_4_460800 },
2447 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2449 pbn_b0_bt_4_460800 },
2450 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2452 pbn_b0_bt_2_460800 },
2453 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2455 pbn_b0_bt_2_460800 },
2456 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2458 pbn_b0_bt_2_460800 },
2459 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2461 pbn_b0_bt_1_115200 },
2462 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2464 pbn_b0_bt_1_460800 },
2465
2466 /*
Russell King1fb8cac2006-12-13 14:45:46 +00002467 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2468 * Cards are identified by their subsystem vendor IDs, which
2469 * (in hex) match the model number.
2470 *
2471 * Note that JC140x are RS422/485 cards which require ox950
2472 * ACR = 0x10, and as such are not currently fully supported.
2473 */
2474 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2475 0x1204, 0x0004, 0, 0,
2476 pbn_b0_4_921600 },
2477 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2478 0x1208, 0x0004, 0, 0,
2479 pbn_b0_4_921600 },
2480/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2481 0x1402, 0x0002, 0, 0,
2482 pbn_b0_2_921600 }, */
2483/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2484 0x1404, 0x0004, 0, 0,
2485 pbn_b0_4_921600 }, */
2486 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2487 0x1208, 0x0004, 0, 0,
2488 pbn_b0_4_921600 },
2489
2490 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002491 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2492 */
2493 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2495 pbn_b1_1_1382400 },
2496
2497 /*
2498 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2499 */
2500 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2502 pbn_b1_1_1382400 },
2503
2504 /*
2505 * RAStel 2 port modem, gerg@moreton.com.au
2506 */
2507 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2509 pbn_b2_bt_2_115200 },
2510
2511 /*
2512 * EKF addition for i960 Boards form EKF with serial port
2513 */
2514 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2515 0xE4BF, PCI_ANY_ID, 0, 0,
2516 pbn_intel_i960 },
2517
2518 /*
2519 * Xircom Cardbus/Ethernet combos
2520 */
2521 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2523 pbn_b0_1_115200 },
2524 /*
2525 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2526 */
2527 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2529 pbn_b0_1_115200 },
2530
2531 /*
2532 * Untested PCI modems, sent in from various folks...
2533 */
2534
2535 /*
2536 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2537 */
2538 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2539 0x1048, 0x1500, 0, 0,
2540 pbn_b1_1_115200 },
2541
2542 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2543 0xFF00, 0, 0, 0,
2544 pbn_sgi_ioc3 },
2545
2546 /*
2547 * HP Diva card
2548 */
2549 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2550 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2551 pbn_b1_1_115200 },
2552 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2554 pbn_b0_5_115200 },
2555 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2557 pbn_b2_1_115200 },
2558
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00002559 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2561 pbn_b3_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2564 pbn_b3_4_115200 },
2565 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2567 pbn_b3_8_115200 },
2568
2569 /*
2570 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2571 */
2572 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2573 PCI_ANY_ID, PCI_ANY_ID,
2574 0,
2575 0, pbn_exar_XR17C152 },
2576 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2577 PCI_ANY_ID, PCI_ANY_ID,
2578 0,
2579 0, pbn_exar_XR17C154 },
2580 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2581 PCI_ANY_ID, PCI_ANY_ID,
2582 0,
2583 0, pbn_exar_XR17C158 },
2584
2585 /*
2586 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2587 */
2588 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2590 pbn_b0_1_115200 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07002591 /*
2592 * ITE
2593 */
2594 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2595 PCI_ANY_ID, PCI_ANY_ID,
2596 0, 0,
2597 pbn_b1_bt_1_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002598
2599 /*
Peter Horton737c1752006-08-26 09:07:36 +01002600 * IntaShield IS-200
2601 */
2602 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2604 pbn_b2_2_115200 },
2605
2606 /*
Thomas Hoehn48212002007-02-10 01:46:05 -08002607 * Perle PCI-RAS cards
2608 */
2609 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2610 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2611 0, 0, pbn_b2_4_921600 },
2612 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2613 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2614 0, 0, pbn_b2_8_921600 },
Alan Coxbf0df632007-10-16 01:24:00 -07002615
2616 /*
2617 * Mainpine series cards: Fairly standard layout but fools
2618 * parts of the autodetect in some cases and uses otherwise
2619 * unmatched communications subclasses in the PCI Express case
2620 */
2621
2622 { /* RockForceDUO */
2623 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2624 PCI_VENDOR_ID_MAINPINE, 0x0200,
2625 0, 0, pbn_b0_2_115200 },
2626 { /* RockForceQUATRO */
2627 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2628 PCI_VENDOR_ID_MAINPINE, 0x0300,
2629 0, 0, pbn_b0_4_115200 },
2630 { /* RockForceDUO+ */
2631 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2632 PCI_VENDOR_ID_MAINPINE, 0x0400,
2633 0, 0, pbn_b0_2_115200 },
2634 { /* RockForceQUATRO+ */
2635 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2636 PCI_VENDOR_ID_MAINPINE, 0x0500,
2637 0, 0, pbn_b0_4_115200 },
2638 { /* RockForce+ */
2639 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2640 PCI_VENDOR_ID_MAINPINE, 0x0600,
2641 0, 0, pbn_b0_2_115200 },
2642 { /* RockForce+ */
2643 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2644 PCI_VENDOR_ID_MAINPINE, 0x0700,
2645 0, 0, pbn_b0_4_115200 },
2646 { /* RockForceOCTO+ */
2647 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2648 PCI_VENDOR_ID_MAINPINE, 0x0800,
2649 0, 0, pbn_b0_8_115200 },
2650 { /* RockForceDUO+ */
2651 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2652 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2653 0, 0, pbn_b0_2_115200 },
2654 { /* RockForceQUARTRO+ */
2655 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2656 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2657 0, 0, pbn_b0_4_115200 },
2658 { /* RockForceOCTO+ */
2659 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2660 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2661 0, 0, pbn_b0_8_115200 },
2662 { /* RockForceD1 */
2663 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2664 PCI_VENDOR_ID_MAINPINE, 0x2000,
2665 0, 0, pbn_b0_1_115200 },
2666 { /* RockForceF1 */
2667 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2668 PCI_VENDOR_ID_MAINPINE, 0x2100,
2669 0, 0, pbn_b0_1_115200 },
2670 { /* RockForceD2 */
2671 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2672 PCI_VENDOR_ID_MAINPINE, 0x2200,
2673 0, 0, pbn_b0_2_115200 },
2674 { /* RockForceF2 */
2675 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2676 PCI_VENDOR_ID_MAINPINE, 0x2300,
2677 0, 0, pbn_b0_2_115200 },
2678 { /* RockForceD4 */
2679 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2680 PCI_VENDOR_ID_MAINPINE, 0x2400,
2681 0, 0, pbn_b0_4_115200 },
2682 { /* RockForceF4 */
2683 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2684 PCI_VENDOR_ID_MAINPINE, 0x2500,
2685 0, 0, pbn_b0_4_115200 },
2686 { /* RockForceD8 */
2687 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2688 PCI_VENDOR_ID_MAINPINE, 0x2600,
2689 0, 0, pbn_b0_8_115200 },
2690 { /* RockForceF8 */
2691 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2692 PCI_VENDOR_ID_MAINPINE, 0x2700,
2693 0, 0, pbn_b0_8_115200 },
2694 { /* IQ Express D1 */
2695 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2696 PCI_VENDOR_ID_MAINPINE, 0x3000,
2697 0, 0, pbn_b0_1_115200 },
2698 { /* IQ Express F1 */
2699 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2700 PCI_VENDOR_ID_MAINPINE, 0x3100,
2701 0, 0, pbn_b0_1_115200 },
2702 { /* IQ Express D2 */
2703 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2704 PCI_VENDOR_ID_MAINPINE, 0x3200,
2705 0, 0, pbn_b0_2_115200 },
2706 { /* IQ Express F2 */
2707 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2708 PCI_VENDOR_ID_MAINPINE, 0x3300,
2709 0, 0, pbn_b0_2_115200 },
2710 { /* IQ Express D4 */
2711 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2712 PCI_VENDOR_ID_MAINPINE, 0x3400,
2713 0, 0, pbn_b0_4_115200 },
2714 { /* IQ Express F4 */
2715 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2716 PCI_VENDOR_ID_MAINPINE, 0x3500,
2717 0, 0, pbn_b0_4_115200 },
2718 { /* IQ Express D8 */
2719 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2720 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2721 0, 0, pbn_b0_8_115200 },
2722 { /* IQ Express F8 */
2723 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2724 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2725 0, 0, pbn_b0_8_115200 },
2726
2727
Thomas Hoehn48212002007-02-10 01:46:05 -08002728 /*
Olof Johanssonaa798502007-08-22 14:01:55 -07002729 * PA Semi PA6T-1682M on-chip UART
2730 */
2731 { PCI_VENDOR_ID_PASEMI, 0xa004,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2733 pbn_pasemi_1682M },
2734
2735 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08002736 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2737 */
2738 { PCI_VENDOR_ID_ADDIDATA,
2739 PCI_DEVICE_ID_ADDIDATA_APCI7500,
2740 PCI_ANY_ID,
2741 PCI_ANY_ID,
2742 0,
2743 0,
2744 pbn_b0_4_115200 },
2745
2746 { PCI_VENDOR_ID_ADDIDATA,
2747 PCI_DEVICE_ID_ADDIDATA_APCI7420,
2748 PCI_ANY_ID,
2749 PCI_ANY_ID,
2750 0,
2751 0,
2752 pbn_b0_2_115200 },
2753
2754 { PCI_VENDOR_ID_ADDIDATA,
2755 PCI_DEVICE_ID_ADDIDATA_APCI7300,
2756 PCI_ANY_ID,
2757 PCI_ANY_ID,
2758 0,
2759 0,
2760 pbn_b0_1_115200 },
2761
2762 { PCI_VENDOR_ID_ADDIDATA_OLD,
2763 PCI_DEVICE_ID_ADDIDATA_APCI7800,
2764 PCI_ANY_ID,
2765 PCI_ANY_ID,
2766 0,
2767 0,
2768 pbn_b1_8_115200 },
2769
2770 { PCI_VENDOR_ID_ADDIDATA,
2771 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
2772 PCI_ANY_ID,
2773 PCI_ANY_ID,
2774 0,
2775 0,
2776 pbn_b0_4_115200 },
2777
2778 { PCI_VENDOR_ID_ADDIDATA,
2779 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
2780 PCI_ANY_ID,
2781 PCI_ANY_ID,
2782 0,
2783 0,
2784 pbn_b0_2_115200 },
2785
2786 { PCI_VENDOR_ID_ADDIDATA,
2787 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
2788 PCI_ANY_ID,
2789 PCI_ANY_ID,
2790 0,
2791 0,
2792 pbn_b0_1_115200 },
2793
2794 { PCI_VENDOR_ID_ADDIDATA,
2795 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
2796 PCI_ANY_ID,
2797 PCI_ANY_ID,
2798 0,
2799 0,
2800 pbn_b0_4_115200 },
2801
2802 { PCI_VENDOR_ID_ADDIDATA,
2803 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
2804 PCI_ANY_ID,
2805 PCI_ANY_ID,
2806 0,
2807 0,
2808 pbn_b0_2_115200 },
2809
2810 { PCI_VENDOR_ID_ADDIDATA,
2811 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
2812 PCI_ANY_ID,
2813 PCI_ANY_ID,
2814 0,
2815 0,
2816 pbn_b0_1_115200 },
2817
2818 { PCI_VENDOR_ID_ADDIDATA,
2819 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
2820 PCI_ANY_ID,
2821 PCI_ANY_ID,
2822 0,
2823 0,
2824 pbn_b0_8_115200 },
2825
2826 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002827 * These entries match devices with class COMMUNICATION_SERIAL,
2828 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2829 */
2830 { PCI_ANY_ID, PCI_ANY_ID,
2831 PCI_ANY_ID, PCI_ANY_ID,
2832 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2833 0xffff00, pbn_default },
2834 { PCI_ANY_ID, PCI_ANY_ID,
2835 PCI_ANY_ID, PCI_ANY_ID,
2836 PCI_CLASS_COMMUNICATION_MODEM << 8,
2837 0xffff00, pbn_default },
2838 { PCI_ANY_ID, PCI_ANY_ID,
2839 PCI_ANY_ID, PCI_ANY_ID,
2840 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2841 0xffff00, pbn_default },
2842 { 0, }
2843};
2844
2845static struct pci_driver serial_pci_driver = {
2846 .name = "serial",
2847 .probe = pciserial_init_one,
2848 .remove = __devexit_p(pciserial_remove_one),
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002849#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002850 .suspend = pciserial_suspend_one,
2851 .resume = pciserial_resume_one,
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002852#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002853 .id_table = serial_pci_tbl,
2854};
2855
2856static int __init serial8250_pci_init(void)
2857{
2858 return pci_register_driver(&serial_pci_driver);
2859}
2860
2861static void __exit serial8250_pci_exit(void)
2862{
2863 pci_unregister_driver(&serial_pci_driver);
2864}
2865
2866module_init(serial8250_pci_init);
2867module_exit(serial8250_pci_exit);
2868
2869MODULE_LICENSE("GPL");
2870MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2871MODULE_DEVICE_TABLE(pci, serial_pci_tbl);