Dan Williams | 6f231dd | 2011-07-02 22:56:22 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 3 | * redistributing this file, you may do so under either license. |
| 4 | * |
| 5 | * GPL LICENSE SUMMARY |
| 6 | * |
| 7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of version 2 of the GNU General Public License as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE.GPL. |
| 23 | * |
| 24 | * BSD LICENSE |
| 25 | * |
| 26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
| 27 | * All rights reserved. |
| 28 | * |
| 29 | * Redistribution and use in source and binary forms, with or without |
| 30 | * modification, are permitted provided that the following conditions |
| 31 | * are met: |
| 32 | * |
| 33 | * * Redistributions of source code must retain the above copyright |
| 34 | * notice, this list of conditions and the following disclaimer. |
| 35 | * * Redistributions in binary form must reproduce the above copyright |
| 36 | * notice, this list of conditions and the following disclaimer in |
| 37 | * the documentation and/or other materials provided with the |
| 38 | * distribution. |
| 39 | * * Neither the name of Intel Corporation nor the names of its |
| 40 | * contributors may be used to endorse or promote products derived |
| 41 | * from this software without specific prior written permission. |
| 42 | * |
| 43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 54 | */ |
| 55 | |
| 56 | #ifndef _SCI_BASE_CONTROLLER_H_ |
| 57 | #define _SCI_BASE_CONTROLLER_H_ |
| 58 | |
| 59 | #include "intel_sas.h" |
| 60 | #include "sci_controller_constants.h" |
| 61 | #include "sci_base_state.h" |
| 62 | #include "sci_base_memory_descriptor_list.h" |
| 63 | #include "sci_base_state_machine.h" |
| 64 | #include "sci_object.h" |
| 65 | |
| 66 | struct sci_base_memory_descriptor_list; |
| 67 | |
| 68 | /** |
| 69 | * enum sci_base_controller_states - This enumeration depicts all the states |
| 70 | * for the common controller state machine. |
| 71 | * |
| 72 | * |
| 73 | */ |
| 74 | enum sci_base_controller_states { |
| 75 | /** |
| 76 | * Simply the initial state for the base controller state machine. |
| 77 | */ |
| 78 | SCI_BASE_CONTROLLER_STATE_INITIAL = 0, |
| 79 | |
| 80 | /** |
| 81 | * This state indicates that the controller is reset. The memory for |
| 82 | * the controller is in it's initial state, but the controller requires |
| 83 | * initialization. |
| 84 | * This state is entered from the INITIAL state. |
| 85 | * This state is entered from the RESETTING state. |
| 86 | */ |
| 87 | SCI_BASE_CONTROLLER_STATE_RESET, |
| 88 | |
| 89 | /** |
| 90 | * This state is typically an action state that indicates the controller |
| 91 | * is in the process of initialization. In this state no new IO operations |
| 92 | * are permitted. |
| 93 | * This state is entered from the RESET state. |
| 94 | */ |
| 95 | SCI_BASE_CONTROLLER_STATE_INITIALIZING, |
| 96 | |
| 97 | /** |
| 98 | * This state indicates that the controller has been successfully |
| 99 | * initialized. In this state no new IO operations are permitted. |
| 100 | * This state is entered from the INITIALIZING state. |
| 101 | */ |
| 102 | SCI_BASE_CONTROLLER_STATE_INITIALIZED, |
| 103 | |
| 104 | /** |
| 105 | * This state indicates the the controller is in the process of becoming |
| 106 | * ready (i.e. starting). In this state no new IO operations are permitted. |
| 107 | * This state is entered from the INITIALIZED state. |
| 108 | */ |
| 109 | SCI_BASE_CONTROLLER_STATE_STARTING, |
| 110 | |
| 111 | /** |
| 112 | * This state indicates the controller is now ready. Thus, the user |
| 113 | * is able to perform IO operations on the controller. |
| 114 | * This state is entered from the STARTING state. |
| 115 | */ |
| 116 | SCI_BASE_CONTROLLER_STATE_READY, |
| 117 | |
| 118 | /** |
| 119 | * This state is typically an action state that indicates the controller |
| 120 | * is in the process of resetting. Thus, the user is unable to perform |
| 121 | * IO operations on the controller. A reset is considered destructive in |
| 122 | * most cases. |
| 123 | * This state is entered from the READY state. |
| 124 | * This state is entered from the FAILED state. |
| 125 | * This state is entered from the STOPPED state. |
| 126 | */ |
| 127 | SCI_BASE_CONTROLLER_STATE_RESETTING, |
| 128 | |
| 129 | /** |
| 130 | * This state indicates that the controller is in the process of stopping. |
| 131 | * In this state no new IO operations are permitted, but existing IO |
| 132 | * operations are allowed to complete. |
| 133 | * This state is entered from the READY state. |
| 134 | */ |
| 135 | SCI_BASE_CONTROLLER_STATE_STOPPING, |
| 136 | |
| 137 | /** |
| 138 | * This state indicates that the controller has successfully been stopped. |
| 139 | * In this state no new IO operations are permitted. |
| 140 | * This state is entered from the STOPPING state. |
| 141 | */ |
| 142 | SCI_BASE_CONTROLLER_STATE_STOPPED, |
| 143 | |
| 144 | /** |
| 145 | * This state indicates that the controller could not successfully be |
| 146 | * initialized. In this state no new IO operations are permitted. |
| 147 | * This state is entered from the INITIALIZING state. |
| 148 | * This state is entered from the STARTING state. |
| 149 | * This state is entered from the STOPPING state. |
| 150 | * This state is entered from the RESETTING state. |
| 151 | */ |
| 152 | SCI_BASE_CONTROLLER_STATE_FAILED, |
| 153 | |
| 154 | SCI_BASE_CONTROLLER_MAX_STATES |
| 155 | |
| 156 | }; |
| 157 | |
| 158 | /** |
| 159 | * struct sci_base_controller - The base controller object abstracts the fields |
| 160 | * common to all SCI controller objects. |
| 161 | * |
| 162 | * |
| 163 | */ |
| 164 | struct sci_base_controller { |
| 165 | /** |
| 166 | * The field specifies that the parent object for the base controller |
| 167 | * is the base object itself. |
| 168 | */ |
| 169 | struct sci_base_object parent; |
| 170 | |
| 171 | /** |
| 172 | * This field points to the memory descriptor list associated with this |
| 173 | * controller. The MDL indicates the memory requirements necessary for |
| 174 | * this controller object. |
| 175 | */ |
| 176 | struct sci_base_memory_descriptor_list mdl; |
| 177 | |
| 178 | /** |
| 179 | * This field contains the information for the base controller state |
| 180 | * machine. |
| 181 | */ |
| 182 | struct sci_base_state_machine state_machine; |
| 183 | }; |
| 184 | |
| 185 | /* Forward declarations */ |
| 186 | struct sci_base_remote_device; |
| 187 | struct sci_base_request; |
| 188 | |
| 189 | typedef enum sci_status |
| 190 | (*sci_base_controller_handler_t)(struct sci_base_controller *); |
| 191 | |
| 192 | typedef enum sci_status |
| 193 | (*sci_base_controller_timed_handler_t)(struct sci_base_controller *, u32); |
| 194 | |
| 195 | typedef enum sci_status |
| 196 | (*sci_base_controller_request_handler_t)(struct sci_base_controller *, |
| 197 | struct sci_base_remote_device *, |
| 198 | struct sci_base_request *); |
| 199 | |
| 200 | typedef enum sci_status |
| 201 | (*sci_base_controller_start_request_handler_t)(struct sci_base_controller *, |
| 202 | struct sci_base_remote_device *, |
| 203 | struct sci_base_request *, u16); |
| 204 | |
| 205 | /** |
| 206 | * struct sci_base_controller_state_handler - This structure contains all of |
| 207 | * the state handler methods common to base controller state machines. |
| 208 | * Handler methods provide the ability to change the behavior for user |
| 209 | * requests or transitions depending on the state the machine is in. |
| 210 | * |
| 211 | * |
| 212 | */ |
| 213 | struct sci_base_controller_state_handler { |
| 214 | /** |
| 215 | * The start_handler specifies the method invoked when a user attempts to |
| 216 | * start a controller. |
| 217 | */ |
| 218 | sci_base_controller_timed_handler_t start; |
| 219 | |
| 220 | /** |
| 221 | * The stop_handler specifies the method invoked when a user attempts to |
| 222 | * stop a controller. |
| 223 | */ |
| 224 | sci_base_controller_timed_handler_t stop; |
| 225 | |
| 226 | /** |
| 227 | * The reset_handler specifies the method invoked when a user attempts to |
| 228 | * reset a controller. |
| 229 | */ |
| 230 | sci_base_controller_handler_t reset; |
| 231 | |
| 232 | /** |
| 233 | * The initialize_handler specifies the method invoked when a user |
| 234 | * attempts to initialize a controller. |
| 235 | */ |
| 236 | sci_base_controller_handler_t initialize; |
| 237 | |
| 238 | /** |
| 239 | * The start_io_handler specifies the method invoked when a user |
| 240 | * attempts to start an IO request for a controller. |
| 241 | */ |
| 242 | sci_base_controller_start_request_handler_t start_io; |
| 243 | |
| 244 | /** |
| 245 | * The complete_io_handler specifies the method invoked when a user |
| 246 | * attempts to complete an IO request for a controller. |
| 247 | */ |
| 248 | sci_base_controller_request_handler_t complete_io; |
| 249 | |
| 250 | /** |
| 251 | * The continue_io_handler specifies the method invoked when a user |
| 252 | * attempts to continue an IO request for a controller. |
| 253 | */ |
| 254 | sci_base_controller_request_handler_t continue_io; |
| 255 | |
| 256 | /** |
| 257 | * The start_task_handler specifies the method invoked when a user |
| 258 | * attempts to start a task management request for a controller. |
| 259 | */ |
| 260 | sci_base_controller_start_request_handler_t start_task; |
| 261 | |
| 262 | /** |
| 263 | * The complete_task_handler specifies the method invoked when a user |
| 264 | * attempts to complete a task management request for a controller. |
| 265 | */ |
| 266 | sci_base_controller_request_handler_t complete_task; |
| 267 | |
| 268 | }; |
| 269 | |
| 270 | /** |
| 271 | * sci_base_controller_construct() - Construct the base controller |
| 272 | * @this_controller: This parameter specifies the base controller to be |
| 273 | * constructed. |
| 274 | * @state_table: This parameter specifies the table of state definitions to be |
| 275 | * utilized for the controller state machine. |
| 276 | * @mde_array: This parameter specifies the array of memory descriptor entries |
| 277 | * to be managed by this list. |
| 278 | * @mde_array_length: This parameter specifies the size of the array of entries. |
| 279 | * @next_mdl: This parameter specifies a subsequent MDL object to be managed by |
| 280 | * this MDL object. |
| 281 | * @oem_parameters: This parameter specifies the original equipment |
| 282 | * manufacturer parameters to be utilized by this controller object. |
| 283 | * |
| 284 | */ |
| 285 | static inline void sci_base_controller_construct( |
| 286 | struct sci_base_controller *scic_base, |
| 287 | const struct sci_base_state *state_table, |
| 288 | struct sci_physical_memory_descriptor *mdes, |
| 289 | u32 mde_count, |
| 290 | struct sci_base_memory_descriptor_list *next_mdl) |
| 291 | { |
| 292 | scic_base->parent.private = NULL; |
| 293 | |
| 294 | sci_base_state_machine_construct( |
| 295 | &scic_base->state_machine, |
| 296 | &scic_base->parent, |
| 297 | state_table, |
| 298 | SCI_BASE_CONTROLLER_STATE_INITIAL |
| 299 | ); |
| 300 | |
| 301 | sci_base_mdl_construct(&scic_base->mdl, mdes, mde_count, next_mdl); |
| 302 | |
| 303 | sci_base_state_machine_start(&scic_base->state_machine); |
| 304 | } |
| 305 | |
| 306 | #endif /* _SCI_BASE_CONTROLLER_H_ */ |