Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Renesas R-Car Gen3 for USB2.0 PHY driver |
| 3 | * |
| 4 | * Copyright (C) 2015 Renesas Electronics Corporation |
| 5 | * |
| 6 | * This is based on the phy-rcar-gen2 driver: |
| 7 | * Copyright (C) 2014 Renesas Solutions Corp. |
| 8 | * Copyright (C) 2014 Cogent Embedded, Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 15 | #include <linux/interrupt.h> |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 16 | #include <linux/io.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/of_address.h> |
| 20 | #include <linux/phy/phy.h> |
| 21 | #include <linux/platform_device.h> |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 22 | #include <linux/regulator/consumer.h> |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 23 | |
| 24 | /******* USB2.0 Host registers (original offset is +0x200) *******/ |
| 25 | #define USB2_INT_ENABLE 0x000 |
| 26 | #define USB2_USBCTR 0x00c |
| 27 | #define USB2_SPD_RSM_TIMSET 0x10c |
| 28 | #define USB2_OC_TIMSET 0x110 |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 29 | #define USB2_COMMCTRL 0x600 |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 30 | #define USB2_OBINTSTA 0x604 |
| 31 | #define USB2_OBINTEN 0x608 |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 32 | #define USB2_VBCTRL 0x60c |
| 33 | #define USB2_LINECTRL1 0x610 |
| 34 | #define USB2_ADPCTRL 0x630 |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 35 | |
| 36 | /* INT_ENABLE */ |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 37 | #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 38 | #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) |
| 39 | #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 40 | #define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN | \ |
| 41 | USB2_INT_ENABLE_USBH_INTB_EN | \ |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 42 | USB2_INT_ENABLE_USBH_INTA_EN) |
| 43 | |
| 44 | /* USBCTR */ |
| 45 | #define USB2_USBCTR_DIRPD BIT(2) |
| 46 | #define USB2_USBCTR_PLL_RST BIT(1) |
| 47 | |
| 48 | /* SPD_RSM_TIMSET */ |
| 49 | #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b |
| 50 | |
| 51 | /* OC_TIMSET */ |
| 52 | #define USB2_OC_TIMSET_INIT 0x000209ab |
| 53 | |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 54 | /* COMMCTRL */ |
| 55 | #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ |
| 56 | |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 57 | /* OBINTSTA and OBINTEN */ |
| 58 | #define USB2_OBINT_SESSVLDCHG BIT(12) |
| 59 | #define USB2_OBINT_IDDIGCHG BIT(11) |
| 60 | #define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG | \ |
| 61 | USB2_OBINT_IDDIGCHG) |
| 62 | |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 63 | /* VBCTRL */ |
| 64 | #define USB2_VBCTRL_DRVVBUSSEL BIT(8) |
| 65 | |
| 66 | /* LINECTRL1 */ |
| 67 | #define USB2_LINECTRL1_DPRPD_EN BIT(19) |
| 68 | #define USB2_LINECTRL1_DP_RPD BIT(18) |
| 69 | #define USB2_LINECTRL1_DMRPD_EN BIT(17) |
| 70 | #define USB2_LINECTRL1_DM_RPD BIT(16) |
| 71 | |
| 72 | /* ADPCTRL */ |
| 73 | #define USB2_ADPCTRL_OTGSESSVLD BIT(20) |
| 74 | #define USB2_ADPCTRL_IDDIG BIT(19) |
| 75 | #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ |
| 76 | #define USB2_ADPCTRL_DRVVBUS BIT(4) |
| 77 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 78 | struct rcar_gen3_chan { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 79 | void __iomem *base; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 80 | struct phy *phy; |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 81 | struct regulator *vbus; |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 82 | bool has_otg; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 83 | }; |
| 84 | |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 85 | static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host) |
| 86 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 87 | void __iomem *usb2_base = ch->base; |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 88 | u32 val = readl(usb2_base + USB2_COMMCTRL); |
| 89 | |
| 90 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host); |
| 91 | if (host) |
| 92 | val &= ~USB2_COMMCTRL_OTG_PERI; |
| 93 | else |
| 94 | val |= USB2_COMMCTRL_OTG_PERI; |
| 95 | writel(val, usb2_base + USB2_COMMCTRL); |
| 96 | } |
| 97 | |
| 98 | static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm) |
| 99 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 100 | void __iomem *usb2_base = ch->base; |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 101 | u32 val = readl(usb2_base + USB2_LINECTRL1); |
| 102 | |
| 103 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm); |
| 104 | val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); |
| 105 | if (dp) |
| 106 | val |= USB2_LINECTRL1_DP_RPD; |
| 107 | if (dm) |
| 108 | val |= USB2_LINECTRL1_DM_RPD; |
| 109 | writel(val, usb2_base + USB2_LINECTRL1); |
| 110 | } |
| 111 | |
| 112 | static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus) |
| 113 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 114 | void __iomem *usb2_base = ch->base; |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 115 | u32 val = readl(usb2_base + USB2_ADPCTRL); |
| 116 | |
| 117 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus); |
| 118 | if (vbus) |
| 119 | val |= USB2_ADPCTRL_DRVVBUS; |
| 120 | else |
| 121 | val &= ~USB2_ADPCTRL_DRVVBUS; |
| 122 | writel(val, usb2_base + USB2_ADPCTRL); |
| 123 | } |
| 124 | |
| 125 | static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch) |
| 126 | { |
| 127 | rcar_gen3_set_linectrl(ch, 1, 1); |
| 128 | rcar_gen3_set_host_mode(ch, 1); |
| 129 | rcar_gen3_enable_vbus_ctrl(ch, 1); |
| 130 | } |
| 131 | |
| 132 | static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch) |
| 133 | { |
| 134 | rcar_gen3_set_linectrl(ch, 0, 1); |
| 135 | rcar_gen3_set_host_mode(ch, 0); |
| 136 | rcar_gen3_enable_vbus_ctrl(ch, 0); |
| 137 | } |
| 138 | |
| 139 | static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch) |
| 140 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 141 | return !!(readl(ch->base + USB2_ADPCTRL) & |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 142 | USB2_ADPCTRL_OTGSESSVLD); |
| 143 | } |
| 144 | |
| 145 | static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch) |
| 146 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 147 | return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG); |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch) |
| 151 | { |
| 152 | bool is_host = true; |
| 153 | |
| 154 | /* B-device? */ |
| 155 | if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch)) |
| 156 | is_host = false; |
| 157 | |
| 158 | if (is_host) |
| 159 | rcar_gen3_init_for_host(ch); |
| 160 | else |
| 161 | rcar_gen3_init_for_peri(ch); |
| 162 | } |
| 163 | |
| 164 | static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch) |
| 165 | { |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 166 | void __iomem *usb2_base = ch->base; |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 167 | u32 val; |
| 168 | |
| 169 | val = readl(usb2_base + USB2_VBCTRL); |
| 170 | writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 171 | writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA); |
| 172 | val = readl(usb2_base + USB2_OBINTEN); |
| 173 | writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN); |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 174 | val = readl(usb2_base + USB2_ADPCTRL); |
| 175 | writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); |
| 176 | val = readl(usb2_base + USB2_LINECTRL1); |
| 177 | rcar_gen3_set_linectrl(ch, 0, 0); |
| 178 | writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN, |
| 179 | usb2_base + USB2_LINECTRL1); |
| 180 | |
| 181 | rcar_gen3_device_recognition(ch); |
| 182 | } |
| 183 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 184 | static int rcar_gen3_phy_usb2_init(struct phy *p) |
| 185 | { |
| 186 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 187 | void __iomem *usb2_base = channel->base; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 188 | |
| 189 | /* Initialize USB2 part */ |
| 190 | writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE); |
| 191 | writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET); |
| 192 | writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET); |
| 193 | |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 194 | /* Initialize otg part */ |
| 195 | if (channel->has_otg) |
Yoshihiro Shimoda | 1114e2d | 2015-11-30 10:44:31 +0900 | [diff] [blame] | 196 | rcar_gen3_init_otg(channel); |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static int rcar_gen3_phy_usb2_exit(struct phy *p) |
| 202 | { |
| 203 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); |
| 204 | |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 205 | writel(0, channel->base + USB2_INT_ENABLE); |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | static int rcar_gen3_phy_usb2_power_on(struct phy *p) |
| 211 | { |
| 212 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 213 | void __iomem *usb2_base = channel->base; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 214 | u32 val; |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 215 | int ret; |
| 216 | |
| 217 | if (channel->vbus) { |
| 218 | ret = regulator_enable(channel->vbus); |
| 219 | if (ret) |
| 220 | return ret; |
| 221 | } |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 222 | |
| 223 | val = readl(usb2_base + USB2_USBCTR); |
| 224 | val |= USB2_USBCTR_PLL_RST; |
| 225 | writel(val, usb2_base + USB2_USBCTR); |
| 226 | val &= ~USB2_USBCTR_PLL_RST; |
| 227 | writel(val, usb2_base + USB2_USBCTR); |
| 228 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 229 | return 0; |
| 230 | } |
| 231 | |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 232 | static int rcar_gen3_phy_usb2_power_off(struct phy *p) |
| 233 | { |
| 234 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); |
| 235 | int ret = 0; |
| 236 | |
| 237 | if (channel->vbus) |
| 238 | ret = regulator_disable(channel->vbus); |
| 239 | |
| 240 | return ret; |
| 241 | } |
| 242 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 243 | static struct phy_ops rcar_gen3_phy_usb2_ops = { |
| 244 | .init = rcar_gen3_phy_usb2_init, |
| 245 | .exit = rcar_gen3_phy_usb2_exit, |
| 246 | .power_on = rcar_gen3_phy_usb2_power_on, |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 247 | .power_off = rcar_gen3_phy_usb2_power_off, |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 248 | .owner = THIS_MODULE, |
| 249 | }; |
| 250 | |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 251 | static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch) |
| 252 | { |
| 253 | struct rcar_gen3_chan *ch = _ch; |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 254 | void __iomem *usb2_base = ch->base; |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 255 | u32 status = readl(usb2_base + USB2_OBINTSTA); |
| 256 | irqreturn_t ret = IRQ_NONE; |
| 257 | |
| 258 | if (status & USB2_OBINT_BITS) { |
| 259 | dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status); |
| 260 | writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA); |
| 261 | rcar_gen3_device_recognition(ch); |
| 262 | ret = IRQ_HANDLED; |
| 263 | } |
| 264 | |
| 265 | return ret; |
| 266 | } |
| 267 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 268 | static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { |
| 269 | { .compatible = "renesas,usb2-phy-r8a7795" }, |
Simon Horman | cde7bc3 | 2016-03-07 10:58:41 +0900 | [diff] [blame] | 270 | { .compatible = "renesas,rcar-gen3-usb2-phy" }, |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 271 | { } |
| 272 | }; |
| 273 | MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table); |
| 274 | |
| 275 | static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) |
| 276 | { |
| 277 | struct device *dev = &pdev->dev; |
| 278 | struct rcar_gen3_chan *channel; |
| 279 | struct phy_provider *provider; |
| 280 | struct resource *res; |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 281 | int irq; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 282 | |
| 283 | if (!dev->of_node) { |
| 284 | dev_err(dev, "This driver needs device tree\n"); |
| 285 | return -EINVAL; |
| 286 | } |
| 287 | |
| 288 | channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL); |
| 289 | if (!channel) |
| 290 | return -ENOMEM; |
| 291 | |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 292 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Yoshihiro Shimoda | 801a69c | 2016-03-03 19:09:04 +0900 | [diff] [blame] | 293 | channel->base = devm_ioremap_resource(dev, res); |
| 294 | if (IS_ERR(channel->base)) |
| 295 | return PTR_ERR(channel->base); |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 296 | |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 297 | /* call request_irq for OTG */ |
| 298 | irq = platform_get_irq(pdev, 0); |
| 299 | if (irq >= 0) { |
| 300 | irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq, |
| 301 | IRQF_SHARED, dev_name(dev), channel); |
Yoshihiro Shimoda | 9f391c5 | 2015-11-30 10:44:32 +0900 | [diff] [blame] | 302 | if (irq < 0) |
| 303 | dev_err(dev, "No irq handler (%d)\n", irq); |
Yoshihiro Shimoda | b956401 | 2016-01-07 18:16:44 +0900 | [diff] [blame] | 304 | channel->has_otg = true; |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* devm_phy_create() will call pm_runtime_enable(dev); */ |
| 308 | channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops); |
| 309 | if (IS_ERR(channel->phy)) { |
| 310 | dev_err(dev, "Failed to create USB2 PHY\n"); |
| 311 | return PTR_ERR(channel->phy); |
| 312 | } |
| 313 | |
Yoshihiro Shimoda | 6dcfd7c | 2016-03-03 19:09:05 +0900 | [diff] [blame^] | 314 | channel->vbus = devm_regulator_get_optional(dev, "vbus"); |
| 315 | if (IS_ERR(channel->vbus)) { |
| 316 | if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) |
| 317 | return PTR_ERR(channel->vbus); |
| 318 | channel->vbus = NULL; |
| 319 | } |
| 320 | |
Yoshihiro Shimoda | f3b5a8d | 2015-11-30 10:44:30 +0900 | [diff] [blame] | 321 | phy_set_drvdata(channel->phy, channel); |
| 322 | |
| 323 | provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
| 324 | if (IS_ERR(provider)) |
| 325 | dev_err(dev, "Failed to register PHY provider\n"); |
| 326 | |
| 327 | return PTR_ERR_OR_ZERO(provider); |
| 328 | } |
| 329 | |
| 330 | static struct platform_driver rcar_gen3_phy_usb2_driver = { |
| 331 | .driver = { |
| 332 | .name = "phy_rcar_gen3_usb2", |
| 333 | .of_match_table = rcar_gen3_phy_usb2_match_table, |
| 334 | }, |
| 335 | .probe = rcar_gen3_phy_usb2_probe, |
| 336 | }; |
| 337 | module_platform_driver(rcar_gen3_phy_usb2_driver); |
| 338 | |
| 339 | MODULE_LICENSE("GPL v2"); |
| 340 | MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY"); |
| 341 | MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); |