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Thierry Redinga1702852009-03-27 00:12:24 -07001/*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/etherdevice.h>
15#include <linux/crc32.h>
16#include <linux/io.h>
17#include <linux/mii.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040020#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Thierry Redinga1702852009-03-27 00:12:24 -070022#include <net/ethoc.h>
23
Thomas Chou0baa0802009-10-04 23:33:20 +000024static int buffer_size = 0x8000; /* 32 KBytes */
25module_param(buffer_size, int, 0);
26MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
27
Thierry Redinga1702852009-03-27 00:12:24 -070028/* register offsets */
29#define MODER 0x00
30#define INT_SOURCE 0x04
31#define INT_MASK 0x08
32#define IPGT 0x0c
33#define IPGR1 0x10
34#define IPGR2 0x14
35#define PACKETLEN 0x18
36#define COLLCONF 0x1c
37#define TX_BD_NUM 0x20
38#define CTRLMODER 0x24
39#define MIIMODER 0x28
40#define MIICOMMAND 0x2c
41#define MIIADDRESS 0x30
42#define MIITX_DATA 0x34
43#define MIIRX_DATA 0x38
44#define MIISTATUS 0x3c
45#define MAC_ADDR0 0x40
46#define MAC_ADDR1 0x44
47#define ETH_HASH0 0x48
48#define ETH_HASH1 0x4c
49#define ETH_TXCTRL 0x50
50
51/* mode register */
52#define MODER_RXEN (1 << 0) /* receive enable */
53#define MODER_TXEN (1 << 1) /* transmit enable */
54#define MODER_NOPRE (1 << 2) /* no preamble */
55#define MODER_BRO (1 << 3) /* broadcast address */
56#define MODER_IAM (1 << 4) /* individual address mode */
57#define MODER_PRO (1 << 5) /* promiscuous mode */
58#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59#define MODER_LOOP (1 << 7) /* loopback */
60#define MODER_NBO (1 << 8) /* no back-off */
61#define MODER_EDE (1 << 9) /* excess defer enable */
62#define MODER_FULLD (1 << 10) /* full duplex */
63#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64#define MODER_DCRC (1 << 12) /* delayed CRC enable */
65#define MODER_CRC (1 << 13) /* CRC enable */
66#define MODER_HUGE (1 << 14) /* huge packets enable */
67#define MODER_PAD (1 << 15) /* padding enabled */
68#define MODER_RSM (1 << 16) /* receive small packets */
69
70/* interrupt source and mask registers */
71#define INT_MASK_TXF (1 << 0) /* transmit frame */
72#define INT_MASK_TXE (1 << 1) /* transmit error */
73#define INT_MASK_RXF (1 << 2) /* receive frame */
74#define INT_MASK_RXE (1 << 3) /* receive error */
75#define INT_MASK_BUSY (1 << 4)
76#define INT_MASK_TXC (1 << 5) /* transmit control frame */
77#define INT_MASK_RXC (1 << 6) /* receive control frame */
78
79#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81
82#define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
86 INT_MASK_BUSY \
87 )
88
89/* packet length register */
90#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
93 PACKETLEN_MAX(max))
94
95/* transmit buffer number register */
96#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97
98/* control module mode register */
99#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102
103/* MII mode register */
104#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105#define MIIMODER_NOPRE (1 << 8) /* no preamble */
106
107/* MII command register */
108#define MIICOMMAND_SCAN (1 << 0) /* scan status */
109#define MIICOMMAND_READ (1 << 1) /* read status */
110#define MIICOMMAND_WRITE (1 << 2) /* write control data */
111
112/* MII address register */
113#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
117
118/* MII transmit data register */
119#define MIITX_DATA_VAL(x) ((x) & 0xffff)
120
121/* MII receive data register */
122#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123
124/* MII status register */
125#define MIISTATUS_LINKFAIL (1 << 0)
126#define MIISTATUS_BUSY (1 << 1)
127#define MIISTATUS_INVALID (1 << 2)
128
129/* TX buffer descriptor */
130#define TX_BD_CS (1 << 0) /* carrier sense lost */
131#define TX_BD_DF (1 << 1) /* defer indication */
132#define TX_BD_LC (1 << 2) /* late collision */
133#define TX_BD_RL (1 << 3) /* retransmission limit */
134#define TX_BD_RETRY_MASK (0x00f0)
135#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136#define TX_BD_UR (1 << 8) /* transmitter underrun */
137#define TX_BD_CRC (1 << 11) /* TX CRC enable */
138#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139#define TX_BD_WRAP (1 << 13)
140#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141#define TX_BD_READY (1 << 15) /* TX buffer ready */
142#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143#define TX_BD_LEN_MASK (0xffff << 16)
144
145#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147
148/* RX buffer descriptor */
149#define RX_BD_LC (1 << 0) /* late collision */
150#define RX_BD_CRC (1 << 1) /* RX CRC error */
151#define RX_BD_SF (1 << 2) /* short frame */
152#define RX_BD_TL (1 << 3) /* too long */
153#define RX_BD_DN (1 << 4) /* dribble nibble */
154#define RX_BD_IS (1 << 5) /* invalid symbol */
155#define RX_BD_OR (1 << 6) /* receiver overrun */
156#define RX_BD_MISS (1 << 7)
157#define RX_BD_CF (1 << 8) /* control frame */
158#define RX_BD_WRAP (1 << 13)
159#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160#define RX_BD_EMPTY (1 << 15)
161#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162
163#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165
166#define ETHOC_BUFSIZ 1536
167#define ETHOC_ZLEN 64
168#define ETHOC_BD_BASE 0x400
169#define ETHOC_TIMEOUT (HZ / 2)
170#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
171
172/**
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
Thomas Chou0baa0802009-10-04 23:33:20 +0000176 * @dma_alloc: dma allocated buffer size
Thierry Redinga1702852009-03-27 00:12:24 -0700177 * @num_tx: number of send buffers
178 * @cur_tx: last send buffer written
179 * @dty_tx: last buffer actually sent
180 * @num_rx: number of receive buffers
181 * @cur_rx: current receive buffer
182 * @netdev: pointer to network device structure
183 * @napi: NAPI structure
184 * @stats: network device statistics
185 * @msg_enable: device state flags
186 * @rx_lock: receive lock
187 * @lock: device lock
188 * @phy: attached PHY
189 * @mdio: MDIO bus for PHY access
190 * @phy_id: address of attached PHY
191 */
192struct ethoc {
193 void __iomem *iobase;
194 void __iomem *membase;
Thomas Chou0baa0802009-10-04 23:33:20 +0000195 int dma_alloc;
Thierry Redinga1702852009-03-27 00:12:24 -0700196
197 unsigned int num_tx;
198 unsigned int cur_tx;
199 unsigned int dty_tx;
200
201 unsigned int num_rx;
202 unsigned int cur_rx;
203
204 struct net_device *netdev;
205 struct napi_struct napi;
206 struct net_device_stats stats;
207 u32 msg_enable;
208
209 spinlock_t rx_lock;
210 spinlock_t lock;
211
212 struct phy_device *phy;
213 struct mii_bus *mdio;
214 s8 phy_id;
215};
216
217/**
218 * struct ethoc_bd - buffer descriptor
219 * @stat: buffer statistics
220 * @addr: physical memory address
221 */
222struct ethoc_bd {
223 u32 stat;
224 u32 addr;
225};
226
Thomas Chou16dd18b2009-10-07 14:16:42 +0000227static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
Thierry Redinga1702852009-03-27 00:12:24 -0700228{
229 return ioread32(dev->iobase + offset);
230}
231
Thomas Chou16dd18b2009-10-07 14:16:42 +0000232static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
Thierry Redinga1702852009-03-27 00:12:24 -0700233{
234 iowrite32(data, dev->iobase + offset);
235}
236
Thomas Chou16dd18b2009-10-07 14:16:42 +0000237static inline void ethoc_read_bd(struct ethoc *dev, int index,
238 struct ethoc_bd *bd)
Thierry Redinga1702852009-03-27 00:12:24 -0700239{
240 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
241 bd->stat = ethoc_read(dev, offset + 0);
242 bd->addr = ethoc_read(dev, offset + 4);
243}
244
Thomas Chou16dd18b2009-10-07 14:16:42 +0000245static inline void ethoc_write_bd(struct ethoc *dev, int index,
Thierry Redinga1702852009-03-27 00:12:24 -0700246 const struct ethoc_bd *bd)
247{
248 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
249 ethoc_write(dev, offset + 0, bd->stat);
250 ethoc_write(dev, offset + 4, bd->addr);
251}
252
Thomas Chou16dd18b2009-10-07 14:16:42 +0000253static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700254{
255 u32 imask = ethoc_read(dev, INT_MASK);
256 imask |= mask;
257 ethoc_write(dev, INT_MASK, imask);
258}
259
Thomas Chou16dd18b2009-10-07 14:16:42 +0000260static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700261{
262 u32 imask = ethoc_read(dev, INT_MASK);
263 imask &= ~mask;
264 ethoc_write(dev, INT_MASK, imask);
265}
266
Thomas Chou16dd18b2009-10-07 14:16:42 +0000267static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700268{
269 ethoc_write(dev, INT_SOURCE, mask);
270}
271
Thomas Chou16dd18b2009-10-07 14:16:42 +0000272static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700273{
274 u32 mode = ethoc_read(dev, MODER);
275 mode |= MODER_RXEN | MODER_TXEN;
276 ethoc_write(dev, MODER, mode);
277}
278
Thomas Chou16dd18b2009-10-07 14:16:42 +0000279static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700280{
281 u32 mode = ethoc_read(dev, MODER);
282 mode &= ~(MODER_RXEN | MODER_TXEN);
283 ethoc_write(dev, MODER, mode);
284}
285
286static int ethoc_init_ring(struct ethoc *dev)
287{
288 struct ethoc_bd bd;
289 int i;
290
291 dev->cur_tx = 0;
292 dev->dty_tx = 0;
293 dev->cur_rx = 0;
294
295 /* setup transmission buffers */
Thomas Chou3ee19a82009-10-04 23:33:18 +0000296 bd.addr = virt_to_phys(dev->membase);
Thierry Redinga1702852009-03-27 00:12:24 -0700297 bd.stat = TX_BD_IRQ | TX_BD_CRC;
298
299 for (i = 0; i < dev->num_tx; i++) {
300 if (i == dev->num_tx - 1)
301 bd.stat |= TX_BD_WRAP;
302
303 ethoc_write_bd(dev, i, &bd);
304 bd.addr += ETHOC_BUFSIZ;
305 }
306
Thierry Redinga1702852009-03-27 00:12:24 -0700307 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
308
309 for (i = 0; i < dev->num_rx; i++) {
310 if (i == dev->num_rx - 1)
311 bd.stat |= RX_BD_WRAP;
312
313 ethoc_write_bd(dev, dev->num_tx + i, &bd);
314 bd.addr += ETHOC_BUFSIZ;
315 }
316
317 return 0;
318}
319
320static int ethoc_reset(struct ethoc *dev)
321{
322 u32 mode;
323
324 /* TODO: reset controller? */
325
326 ethoc_disable_rx_and_tx(dev);
327
328 /* TODO: setup registers */
329
330 /* enable FCS generation and automatic padding */
331 mode = ethoc_read(dev, MODER);
332 mode |= MODER_CRC | MODER_PAD;
333 ethoc_write(dev, MODER, mode);
334
335 /* set full-duplex mode */
336 mode = ethoc_read(dev, MODER);
337 mode |= MODER_FULLD;
338 ethoc_write(dev, MODER, mode);
339 ethoc_write(dev, IPGT, 0x15);
340
341 ethoc_ack_irq(dev, INT_MASK_ALL);
342 ethoc_enable_irq(dev, INT_MASK_ALL);
343 ethoc_enable_rx_and_tx(dev);
344 return 0;
345}
346
347static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
348 struct ethoc_bd *bd)
349{
350 struct net_device *netdev = dev->netdev;
351 unsigned int ret = 0;
352
353 if (bd->stat & RX_BD_TL) {
354 dev_err(&netdev->dev, "RX: frame too long\n");
355 dev->stats.rx_length_errors++;
356 ret++;
357 }
358
359 if (bd->stat & RX_BD_SF) {
360 dev_err(&netdev->dev, "RX: frame too short\n");
361 dev->stats.rx_length_errors++;
362 ret++;
363 }
364
365 if (bd->stat & RX_BD_DN) {
366 dev_err(&netdev->dev, "RX: dribble nibble\n");
367 dev->stats.rx_frame_errors++;
368 }
369
370 if (bd->stat & RX_BD_CRC) {
371 dev_err(&netdev->dev, "RX: wrong CRC\n");
372 dev->stats.rx_crc_errors++;
373 ret++;
374 }
375
376 if (bd->stat & RX_BD_OR) {
377 dev_err(&netdev->dev, "RX: overrun\n");
378 dev->stats.rx_over_errors++;
379 ret++;
380 }
381
382 if (bd->stat & RX_BD_MISS)
383 dev->stats.rx_missed_errors++;
384
385 if (bd->stat & RX_BD_LC) {
386 dev_err(&netdev->dev, "RX: late collision\n");
387 dev->stats.collisions++;
388 ret++;
389 }
390
391 return ret;
392}
393
394static int ethoc_rx(struct net_device *dev, int limit)
395{
396 struct ethoc *priv = netdev_priv(dev);
397 int count;
398
399 for (count = 0; count < limit; ++count) {
400 unsigned int entry;
401 struct ethoc_bd bd;
402
403 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
404 ethoc_read_bd(priv, entry, &bd);
405 if (bd.stat & RX_BD_EMPTY)
406 break;
407
408 if (ethoc_update_rx_stats(priv, &bd) == 0) {
409 int size = bd.stat >> 16;
Eric Dumazet89d71a62009-10-13 05:34:20 +0000410 struct sk_buff *skb;
Thomas Chou050f91d2009-10-04 23:33:19 +0000411
412 size -= 4; /* strip the CRC */
Eric Dumazet89d71a62009-10-13 05:34:20 +0000413 skb = netdev_alloc_skb_ip_align(dev, size);
Thomas Chou050f91d2009-10-04 23:33:19 +0000414
Thierry Redinga1702852009-03-27 00:12:24 -0700415 if (likely(skb)) {
Thomas Chou3ee19a82009-10-04 23:33:18 +0000416 void *src = phys_to_virt(bd.addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700417 memcpy_fromio(skb_put(skb, size), src, size);
418 skb->protocol = eth_type_trans(skb, dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700419 priv->stats.rx_packets++;
420 priv->stats.rx_bytes += size;
421 netif_receive_skb(skb);
422 } else {
423 if (net_ratelimit())
424 dev_warn(&dev->dev, "low on memory - "
425 "packet dropped\n");
426
427 priv->stats.rx_dropped++;
428 break;
429 }
430 }
431
432 /* clear the buffer descriptor so it can be reused */
433 bd.stat &= ~RX_BD_STATS;
434 bd.stat |= RX_BD_EMPTY;
435 ethoc_write_bd(priv, entry, &bd);
436 priv->cur_rx++;
437 }
438
439 return count;
440}
441
442static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
443{
444 struct net_device *netdev = dev->netdev;
445
446 if (bd->stat & TX_BD_LC) {
447 dev_err(&netdev->dev, "TX: late collision\n");
448 dev->stats.tx_window_errors++;
449 }
450
451 if (bd->stat & TX_BD_RL) {
452 dev_err(&netdev->dev, "TX: retransmit limit\n");
453 dev->stats.tx_aborted_errors++;
454 }
455
456 if (bd->stat & TX_BD_UR) {
457 dev_err(&netdev->dev, "TX: underrun\n");
458 dev->stats.tx_fifo_errors++;
459 }
460
461 if (bd->stat & TX_BD_CS) {
462 dev_err(&netdev->dev, "TX: carrier sense lost\n");
463 dev->stats.tx_carrier_errors++;
464 }
465
466 if (bd->stat & TX_BD_STATS)
467 dev->stats.tx_errors++;
468
469 dev->stats.collisions += (bd->stat >> 4) & 0xf;
470 dev->stats.tx_bytes += bd->stat >> 16;
471 dev->stats.tx_packets++;
472 return 0;
473}
474
475static void ethoc_tx(struct net_device *dev)
476{
477 struct ethoc *priv = netdev_priv(dev);
478
479 spin_lock(&priv->lock);
480
481 while (priv->dty_tx != priv->cur_tx) {
482 unsigned int entry = priv->dty_tx % priv->num_tx;
483 struct ethoc_bd bd;
484
485 ethoc_read_bd(priv, entry, &bd);
486 if (bd.stat & TX_BD_READY)
487 break;
488
489 entry = (++priv->dty_tx) % priv->num_tx;
490 (void)ethoc_update_tx_stats(priv, &bd);
491 }
492
493 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
494 netif_wake_queue(dev);
495
496 ethoc_ack_irq(priv, INT_MASK_TX);
497 spin_unlock(&priv->lock);
498}
499
500static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
501{
502 struct net_device *dev = (struct net_device *)dev_id;
503 struct ethoc *priv = netdev_priv(dev);
504 u32 pending;
505
506 ethoc_disable_irq(priv, INT_MASK_ALL);
507 pending = ethoc_read(priv, INT_SOURCE);
508 if (unlikely(pending == 0)) {
509 ethoc_enable_irq(priv, INT_MASK_ALL);
510 return IRQ_NONE;
511 }
512
Thomas Chou50c54a52009-10-07 14:16:43 +0000513 ethoc_ack_irq(priv, pending);
Thierry Redinga1702852009-03-27 00:12:24 -0700514
515 if (pending & INT_MASK_BUSY) {
516 dev_err(&dev->dev, "packet dropped\n");
517 priv->stats.rx_dropped++;
518 }
519
520 if (pending & INT_MASK_RX) {
521 if (napi_schedule_prep(&priv->napi))
522 __napi_schedule(&priv->napi);
523 } else {
524 ethoc_enable_irq(priv, INT_MASK_RX);
525 }
526
527 if (pending & INT_MASK_TX)
528 ethoc_tx(dev);
529
530 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
531 return IRQ_HANDLED;
532}
533
534static int ethoc_get_mac_address(struct net_device *dev, void *addr)
535{
536 struct ethoc *priv = netdev_priv(dev);
537 u8 *mac = (u8 *)addr;
538 u32 reg;
539
540 reg = ethoc_read(priv, MAC_ADDR0);
541 mac[2] = (reg >> 24) & 0xff;
542 mac[3] = (reg >> 16) & 0xff;
543 mac[4] = (reg >> 8) & 0xff;
544 mac[5] = (reg >> 0) & 0xff;
545
546 reg = ethoc_read(priv, MAC_ADDR1);
547 mac[0] = (reg >> 8) & 0xff;
548 mac[1] = (reg >> 0) & 0xff;
549
550 return 0;
551}
552
553static int ethoc_poll(struct napi_struct *napi, int budget)
554{
555 struct ethoc *priv = container_of(napi, struct ethoc, napi);
556 int work_done = 0;
557
558 work_done = ethoc_rx(priv->netdev, budget);
559 if (work_done < budget) {
560 ethoc_enable_irq(priv, INT_MASK_RX);
561 napi_complete(napi);
562 }
563
564 return work_done;
565}
566
567static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
568{
569 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
570 struct ethoc *priv = bus->priv;
571
572 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
573 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
574
575 while (time_before(jiffies, timeout)) {
576 u32 status = ethoc_read(priv, MIISTATUS);
577 if (!(status & MIISTATUS_BUSY)) {
578 u32 data = ethoc_read(priv, MIIRX_DATA);
579 /* reset MII command register */
580 ethoc_write(priv, MIICOMMAND, 0);
581 return data;
582 }
583
584 schedule();
585 }
586
587 return -EBUSY;
588}
589
590static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
591{
592 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
593 struct ethoc *priv = bus->priv;
594
595 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
596 ethoc_write(priv, MIITX_DATA, val);
597 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
598
599 while (time_before(jiffies, timeout)) {
600 u32 stat = ethoc_read(priv, MIISTATUS);
601 if (!(stat & MIISTATUS_BUSY))
602 return 0;
603
604 schedule();
605 }
606
607 return -EBUSY;
608}
609
610static int ethoc_mdio_reset(struct mii_bus *bus)
611{
612 return 0;
613}
614
615static void ethoc_mdio_poll(struct net_device *dev)
616{
617}
618
619static int ethoc_mdio_probe(struct net_device *dev)
620{
621 struct ethoc *priv = netdev_priv(dev);
622 struct phy_device *phy;
623 int i;
624
625 for (i = 0; i < PHY_MAX_ADDR; i++) {
626 phy = priv->mdio->phy_map[i];
627 if (phy) {
628 if (priv->phy_id != -1) {
629 /* attach to specified PHY */
630 if (priv->phy_id == phy->addr)
631 break;
632 } else {
633 /* autoselect PHY if none was specified */
634 if (phy->addr != 0)
635 break;
636 }
637 }
638 }
639
640 if (!phy) {
641 dev_err(&dev->dev, "no PHY found\n");
642 return -ENXIO;
643 }
644
Julia Lawalldddcb442009-11-18 08:21:04 +0000645 phy = phy_connect(dev, dev_name(&phy->dev), ethoc_mdio_poll, 0,
Thierry Redinga1702852009-03-27 00:12:24 -0700646 PHY_INTERFACE_MODE_GMII);
647 if (IS_ERR(phy)) {
648 dev_err(&dev->dev, "could not attach to PHY\n");
649 return PTR_ERR(phy);
650 }
651
652 priv->phy = phy;
653 return 0;
654}
655
656static int ethoc_open(struct net_device *dev)
657{
658 struct ethoc *priv = netdev_priv(dev);
659 unsigned int min_tx = 2;
660 unsigned int num_bd;
661 int ret;
662
663 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
664 dev->name, dev);
665 if (ret)
666 return ret;
667
Thomas Choua4d63a92009-10-06 03:25:25 +0000668 /* calculate the number of TX/RX buffers, maximum 128 supported */
Alan Cox4ce22532009-10-12 05:27:55 +0000669 num_bd = min_t(unsigned int,
670 128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
Thomas Chou639b62a2009-10-04 23:33:17 +0000671 priv->num_tx = max(min_tx, num_bd / 4);
Thierry Redinga1702852009-03-27 00:12:24 -0700672 priv->num_rx = num_bd - priv->num_tx;
673 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
674
675 ethoc_init_ring(priv);
676 ethoc_reset(priv);
677
678 if (netif_queue_stopped(dev)) {
679 dev_dbg(&dev->dev, " resuming queue\n");
680 netif_wake_queue(dev);
681 } else {
682 dev_dbg(&dev->dev, " starting queue\n");
683 netif_start_queue(dev);
684 }
685
686 phy_start(priv->phy);
687 napi_enable(&priv->napi);
688
689 if (netif_msg_ifup(priv)) {
690 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
691 dev->base_addr, dev->mem_start, dev->mem_end);
692 }
693
694 return 0;
695}
696
697static int ethoc_stop(struct net_device *dev)
698{
699 struct ethoc *priv = netdev_priv(dev);
700
701 napi_disable(&priv->napi);
702
703 if (priv->phy)
704 phy_stop(priv->phy);
705
706 ethoc_disable_rx_and_tx(priv);
707 free_irq(dev->irq, dev);
708
709 if (!netif_queue_stopped(dev))
710 netif_stop_queue(dev);
711
712 return 0;
713}
714
715static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
716{
717 struct ethoc *priv = netdev_priv(dev);
718 struct mii_ioctl_data *mdio = if_mii(ifr);
719 struct phy_device *phy = NULL;
720
721 if (!netif_running(dev))
722 return -EINVAL;
723
724 if (cmd != SIOCGMIIPHY) {
725 if (mdio->phy_id >= PHY_MAX_ADDR)
726 return -ERANGE;
727
728 phy = priv->mdio->phy_map[mdio->phy_id];
729 if (!phy)
730 return -ENODEV;
731 } else {
732 phy = priv->phy;
733 }
734
735 return phy_mii_ioctl(phy, mdio, cmd);
736}
737
738static int ethoc_config(struct net_device *dev, struct ifmap *map)
739{
740 return -ENOSYS;
741}
742
743static int ethoc_set_mac_address(struct net_device *dev, void *addr)
744{
745 struct ethoc *priv = netdev_priv(dev);
746 u8 *mac = (u8 *)addr;
747
748 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
749 (mac[4] << 8) | (mac[5] << 0));
750 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
751
752 return 0;
753}
754
755static void ethoc_set_multicast_list(struct net_device *dev)
756{
757 struct ethoc *priv = netdev_priv(dev);
758 u32 mode = ethoc_read(priv, MODER);
Jiri Pirko48e2f182010-02-22 09:22:26 +0000759 struct dev_mc_list *mc;
Thierry Redinga1702852009-03-27 00:12:24 -0700760 u32 hash[2] = { 0, 0 };
761
762 /* set loopback mode if requested */
763 if (dev->flags & IFF_LOOPBACK)
764 mode |= MODER_LOOP;
765 else
766 mode &= ~MODER_LOOP;
767
768 /* receive broadcast frames if requested */
769 if (dev->flags & IFF_BROADCAST)
770 mode &= ~MODER_BRO;
771 else
772 mode |= MODER_BRO;
773
774 /* enable promiscuous mode if requested */
775 if (dev->flags & IFF_PROMISC)
776 mode |= MODER_PRO;
777 else
778 mode &= ~MODER_PRO;
779
780 ethoc_write(priv, MODER, mode);
781
782 /* receive multicast frames */
783 if (dev->flags & IFF_ALLMULTI) {
784 hash[0] = 0xffffffff;
785 hash[1] = 0xffffffff;
786 } else {
Jiri Pirko48e2f182010-02-22 09:22:26 +0000787 netdev_for_each_mc_addr(mc, dev) {
788 u32 crc = ether_crc(ETH_ALEN, mc->dmi_addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700789 int bit = (crc >> 26) & 0x3f;
790 hash[bit >> 5] |= 1 << (bit & 0x1f);
791 }
792 }
793
794 ethoc_write(priv, ETH_HASH0, hash[0]);
795 ethoc_write(priv, ETH_HASH1, hash[1]);
796}
797
798static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
799{
800 return -ENOSYS;
801}
802
803static void ethoc_tx_timeout(struct net_device *dev)
804{
805 struct ethoc *priv = netdev_priv(dev);
806 u32 pending = ethoc_read(priv, INT_SOURCE);
807 if (likely(pending))
808 ethoc_interrupt(dev->irq, dev);
809}
810
811static struct net_device_stats *ethoc_stats(struct net_device *dev)
812{
813 struct ethoc *priv = netdev_priv(dev);
814 return &priv->stats;
815}
816
Stephen Hemminger613573252009-08-31 19:50:58 +0000817static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700818{
819 struct ethoc *priv = netdev_priv(dev);
820 struct ethoc_bd bd;
821 unsigned int entry;
822 void *dest;
823
824 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
825 priv->stats.tx_errors++;
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000826 goto out;
Thierry Redinga1702852009-03-27 00:12:24 -0700827 }
828
829 entry = priv->cur_tx % priv->num_tx;
830 spin_lock_irq(&priv->lock);
831 priv->cur_tx++;
832
833 ethoc_read_bd(priv, entry, &bd);
834 if (unlikely(skb->len < ETHOC_ZLEN))
835 bd.stat |= TX_BD_PAD;
836 else
837 bd.stat &= ~TX_BD_PAD;
838
Thomas Chou3ee19a82009-10-04 23:33:18 +0000839 dest = phys_to_virt(bd.addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700840 memcpy_toio(dest, skb->data, skb->len);
841
842 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
843 bd.stat |= TX_BD_LEN(skb->len);
844 ethoc_write_bd(priv, entry, &bd);
845
846 bd.stat |= TX_BD_READY;
847 ethoc_write_bd(priv, entry, &bd);
848
849 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
850 dev_dbg(&dev->dev, "stopping queue\n");
851 netif_stop_queue(dev);
852 }
853
854 dev->trans_start = jiffies;
Thierry Redinga1702852009-03-27 00:12:24 -0700855 spin_unlock_irq(&priv->lock);
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000856out:
857 dev_kfree_skb(skb);
Thierry Redinga1702852009-03-27 00:12:24 -0700858 return NETDEV_TX_OK;
859}
860
861static const struct net_device_ops ethoc_netdev_ops = {
862 .ndo_open = ethoc_open,
863 .ndo_stop = ethoc_stop,
864 .ndo_do_ioctl = ethoc_ioctl,
865 .ndo_set_config = ethoc_config,
866 .ndo_set_mac_address = ethoc_set_mac_address,
867 .ndo_set_multicast_list = ethoc_set_multicast_list,
868 .ndo_change_mtu = ethoc_change_mtu,
869 .ndo_tx_timeout = ethoc_tx_timeout,
870 .ndo_get_stats = ethoc_stats,
871 .ndo_start_xmit = ethoc_start_xmit,
872};
873
874/**
875 * ethoc_probe() - initialize OpenCores ethernet MAC
876 * pdev: platform device
877 */
878static int ethoc_probe(struct platform_device *pdev)
879{
880 struct net_device *netdev = NULL;
881 struct resource *res = NULL;
882 struct resource *mmio = NULL;
883 struct resource *mem = NULL;
884 struct ethoc *priv = NULL;
885 unsigned int phy;
886 int ret = 0;
887
888 /* allocate networking device */
889 netdev = alloc_etherdev(sizeof(struct ethoc));
890 if (!netdev) {
891 dev_err(&pdev->dev, "cannot allocate network device\n");
892 ret = -ENOMEM;
893 goto out;
894 }
895
896 SET_NETDEV_DEV(netdev, &pdev->dev);
897 platform_set_drvdata(pdev, netdev);
898
899 /* obtain I/O memory space */
900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 if (!res) {
902 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
903 ret = -ENXIO;
904 goto free;
905 }
906
907 mmio = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800908 resource_size(res), res->name);
Julia Lawall463889e2009-07-27 06:13:30 +0000909 if (!mmio) {
Thierry Redinga1702852009-03-27 00:12:24 -0700910 dev_err(&pdev->dev, "cannot request I/O memory space\n");
911 ret = -ENXIO;
912 goto free;
913 }
914
915 netdev->base_addr = mmio->start;
916
917 /* obtain buffer memory space */
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Thomas Chou0baa0802009-10-04 23:33:20 +0000919 if (res) {
920 mem = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800921 resource_size(res), res->name);
Thomas Chou0baa0802009-10-04 23:33:20 +0000922 if (!mem) {
923 dev_err(&pdev->dev, "cannot request memory space\n");
924 ret = -ENXIO;
925 goto free;
926 }
927
928 netdev->mem_start = mem->start;
929 netdev->mem_end = mem->end;
Thierry Redinga1702852009-03-27 00:12:24 -0700930 }
931
Thierry Redinga1702852009-03-27 00:12:24 -0700932
933 /* obtain device IRQ number */
934 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
935 if (!res) {
936 dev_err(&pdev->dev, "cannot obtain IRQ\n");
937 ret = -ENXIO;
938 goto free;
939 }
940
941 netdev->irq = res->start;
942
943 /* setup driver-private data */
944 priv = netdev_priv(netdev);
945 priv->netdev = netdev;
Thomas Chou0baa0802009-10-04 23:33:20 +0000946 priv->dma_alloc = 0;
Thierry Redinga1702852009-03-27 00:12:24 -0700947
948 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
Tobias Klauserd8645842010-01-15 01:48:22 -0800949 resource_size(mmio));
Thierry Redinga1702852009-03-27 00:12:24 -0700950 if (!priv->iobase) {
951 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
952 ret = -ENXIO;
953 goto error;
954 }
955
Thomas Chou0baa0802009-10-04 23:33:20 +0000956 if (netdev->mem_end) {
957 priv->membase = devm_ioremap_nocache(&pdev->dev,
Tobias Klauserd8645842010-01-15 01:48:22 -0800958 netdev->mem_start, resource_size(mem));
Thomas Chou0baa0802009-10-04 23:33:20 +0000959 if (!priv->membase) {
960 dev_err(&pdev->dev, "cannot remap memory space\n");
961 ret = -ENXIO;
962 goto error;
963 }
964 } else {
965 /* Allocate buffer memory */
966 priv->membase = dma_alloc_coherent(NULL,
967 buffer_size, (void *)&netdev->mem_start,
968 GFP_KERNEL);
969 if (!priv->membase) {
970 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
971 buffer_size);
972 ret = -ENOMEM;
973 goto error;
974 }
975 netdev->mem_end = netdev->mem_start + buffer_size;
976 priv->dma_alloc = buffer_size;
Thierry Redinga1702852009-03-27 00:12:24 -0700977 }
978
979 /* Allow the platform setup code to pass in a MAC address. */
980 if (pdev->dev.platform_data) {
981 struct ethoc_platform_data *pdata =
982 (struct ethoc_platform_data *)pdev->dev.platform_data;
983 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
984 priv->phy_id = pdata->phy_id;
985 }
986
987 /* Check that the given MAC address is valid. If it isn't, read the
988 * current MAC from the controller. */
989 if (!is_valid_ether_addr(netdev->dev_addr))
990 ethoc_get_mac_address(netdev, netdev->dev_addr);
991
992 /* Check the MAC again for validity, if it still isn't choose and
993 * program a random one. */
994 if (!is_valid_ether_addr(netdev->dev_addr))
995 random_ether_addr(netdev->dev_addr);
996
997 ethoc_set_mac_address(netdev, netdev->dev_addr);
998
999 /* register MII bus */
1000 priv->mdio = mdiobus_alloc();
1001 if (!priv->mdio) {
1002 ret = -ENOMEM;
1003 goto free;
1004 }
1005
1006 priv->mdio->name = "ethoc-mdio";
1007 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1008 priv->mdio->name, pdev->id);
1009 priv->mdio->read = ethoc_mdio_read;
1010 priv->mdio->write = ethoc_mdio_write;
1011 priv->mdio->reset = ethoc_mdio_reset;
1012 priv->mdio->priv = priv;
1013
1014 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1015 if (!priv->mdio->irq) {
1016 ret = -ENOMEM;
1017 goto free_mdio;
1018 }
1019
1020 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1021 priv->mdio->irq[phy] = PHY_POLL;
1022
1023 ret = mdiobus_register(priv->mdio);
1024 if (ret) {
1025 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1026 goto free_mdio;
1027 }
1028
1029 ret = ethoc_mdio_probe(netdev);
1030 if (ret) {
1031 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1032 goto error;
1033 }
1034
1035 ether_setup(netdev);
1036
1037 /* setup the net_device structure */
1038 netdev->netdev_ops = &ethoc_netdev_ops;
1039 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1040 netdev->features |= 0;
1041
1042 /* setup NAPI */
1043 memset(&priv->napi, 0, sizeof(priv->napi));
1044 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1045
1046 spin_lock_init(&priv->rx_lock);
1047 spin_lock_init(&priv->lock);
1048
1049 ret = register_netdev(netdev);
1050 if (ret < 0) {
1051 dev_err(&netdev->dev, "failed to register interface\n");
1052 goto error;
1053 }
1054
1055 goto out;
1056
1057error:
1058 mdiobus_unregister(priv->mdio);
1059free_mdio:
1060 kfree(priv->mdio->irq);
1061 mdiobus_free(priv->mdio);
1062free:
Thomas Chou0baa0802009-10-04 23:33:20 +00001063 if (priv->dma_alloc)
1064 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1065 netdev->mem_start);
Thierry Redinga1702852009-03-27 00:12:24 -07001066 free_netdev(netdev);
1067out:
1068 return ret;
1069}
1070
1071/**
1072 * ethoc_remove() - shutdown OpenCores ethernet MAC
1073 * @pdev: platform device
1074 */
1075static int ethoc_remove(struct platform_device *pdev)
1076{
1077 struct net_device *netdev = platform_get_drvdata(pdev);
1078 struct ethoc *priv = netdev_priv(netdev);
1079
1080 platform_set_drvdata(pdev, NULL);
1081
1082 if (netdev) {
1083 phy_disconnect(priv->phy);
1084 priv->phy = NULL;
1085
1086 if (priv->mdio) {
1087 mdiobus_unregister(priv->mdio);
1088 kfree(priv->mdio->irq);
1089 mdiobus_free(priv->mdio);
1090 }
Thomas Chou0baa0802009-10-04 23:33:20 +00001091 if (priv->dma_alloc)
1092 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1093 netdev->mem_start);
Thierry Redinga1702852009-03-27 00:12:24 -07001094 unregister_netdev(netdev);
1095 free_netdev(netdev);
1096 }
1097
1098 return 0;
1099}
1100
1101#ifdef CONFIG_PM
1102static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1103{
1104 return -ENOSYS;
1105}
1106
1107static int ethoc_resume(struct platform_device *pdev)
1108{
1109 return -ENOSYS;
1110}
1111#else
1112# define ethoc_suspend NULL
1113# define ethoc_resume NULL
1114#endif
1115
1116static struct platform_driver ethoc_driver = {
1117 .probe = ethoc_probe,
1118 .remove = ethoc_remove,
1119 .suspend = ethoc_suspend,
1120 .resume = ethoc_resume,
1121 .driver = {
1122 .name = "ethoc",
1123 },
1124};
1125
1126static int __init ethoc_init(void)
1127{
1128 return platform_driver_register(&ethoc_driver);
1129}
1130
1131static void __exit ethoc_exit(void)
1132{
1133 platform_driver_unregister(&ethoc_driver);
1134}
1135
1136module_init(ethoc_init);
1137module_exit(ethoc_exit);
1138
1139MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1140MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1141MODULE_LICENSE("GPL v2");
1142