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Bo Shen32b16d42013-12-13 14:41:49 +08001/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
Alexandre Belloni472ac3d2015-05-25 18:11:49 +020011#include <linux/delay.h>
Bo Shen32b16d42013-12-13 14:41:49 +080012#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
Alexandre Belloni472ac3d2015-05-25 18:11:49 +020015#include <linux/mutex.h>
Bo Shen32b16d42013-12-13 14:41:49 +080016#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21
22/* The following is global registers for PWM controller */
23#define PWM_ENA 0x04
24#define PWM_DIS 0x08
25#define PWM_SR 0x0C
Alexandre Belloni472ac3d2015-05-25 18:11:49 +020026#define PWM_ISR 0x1C
Bo Shen32b16d42013-12-13 14:41:49 +080027/* Bit field in SR */
28#define PWM_SR_ALL_CH_ON 0x0F
29
30/* The following register is PWM channel related registers */
31#define PWM_CH_REG_OFFSET 0x200
32#define PWM_CH_REG_SIZE 0x20
33
34#define PWM_CMR 0x0
35/* Bit field in CMR */
36#define PWM_CMR_CPOL (1 << 9)
37#define PWM_CMR_UPD_CDTY (1 << 10)
Alexandre Belloni8db9e292014-03-14 15:19:08 +010038#define PWM_CMR_CPRE_MSK 0xF
Bo Shen32b16d42013-12-13 14:41:49 +080039
40/* The following registers for PWM v1 */
41#define PWMV1_CDTY 0x04
42#define PWMV1_CPRD 0x08
43#define PWMV1_CUPD 0x10
44
45/* The following registers for PWM v2 */
46#define PWMV2_CDTY 0x04
47#define PWMV2_CDTYUPD 0x08
48#define PWMV2_CPRD 0x0C
49#define PWMV2_CPRDUPD 0x10
50
51/*
52 * Max value for duty and period
53 *
54 * Although the duty and period register is 32 bit,
55 * however only the LSB 16 bits are significant.
56 */
57#define PWM_MAX_DTY 0xFFFF
58#define PWM_MAX_PRD 0xFFFF
59#define PRD_MAX_PRES 10
60
61struct atmel_pwm_chip {
62 struct pwm_chip chip;
63 struct clk *clk;
64 void __iomem *base;
65
Alexandre Belloni472ac3d2015-05-25 18:11:49 +020066 unsigned int updated_pwms;
67 struct mutex isr_lock; /* ISR is cleared when read, ensure only one thread does that */
68
Bo Shen32b16d42013-12-13 14:41:49 +080069 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
70 unsigned long dty, unsigned long prd);
71};
72
73static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
74{
75 return container_of(chip, struct atmel_pwm_chip, chip);
76}
77
78static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
79 unsigned long offset)
80{
81 return readl_relaxed(chip->base + offset);
82}
83
84static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
85 unsigned long offset, unsigned long val)
86{
87 writel_relaxed(val, chip->base + offset);
88}
89
90static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
91 unsigned int ch, unsigned long offset)
92{
93 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
94
95 return readl_relaxed(chip->base + base + offset);
96}
97
98static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
99 unsigned int ch, unsigned long offset,
100 unsigned long val)
101{
102 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
103
104 writel_relaxed(val, chip->base + base + offset);
105}
106
107static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
108 int duty_ns, int period_ns)
109{
110 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
Nikolaus Vosse2e08972014-09-23 15:30:21 +0200111 unsigned long prd, dty;
Bo Shen32b16d42013-12-13 14:41:49 +0800112 unsigned long long div;
113 unsigned int pres = 0;
Alexandre Belloni8db9e292014-03-14 15:19:08 +0100114 u32 val;
Bo Shen32b16d42013-12-13 14:41:49 +0800115 int ret;
116
117 if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) {
118 dev_err(chip->dev, "cannot change PWM period while enabled\n");
119 return -EBUSY;
120 }
121
Nikolaus Vosse2e08972014-09-23 15:30:21 +0200122 /* Calculate the period cycles and prescale value */
123 div = (unsigned long long)clk_get_rate(atmel_pwm->clk) * period_ns;
124 do_div(div, NSEC_PER_SEC);
Bo Shen32b16d42013-12-13 14:41:49 +0800125
Bo Shen32b16d42013-12-13 14:41:49 +0800126 while (div > PWM_MAX_PRD) {
Nikolaus Vosse2e08972014-09-23 15:30:21 +0200127 div >>= 1;
128 pres++;
129 }
Bo Shen32b16d42013-12-13 14:41:49 +0800130
Nikolaus Vosse2e08972014-09-23 15:30:21 +0200131 if (pres > PRD_MAX_PRES) {
132 dev_err(chip->dev, "pres exceeds the maximum value\n");
133 return -EINVAL;
Bo Shen32b16d42013-12-13 14:41:49 +0800134 }
135
136 /* Calculate the duty cycles */
137 prd = div;
138 div *= duty_ns;
139 do_div(div, period_ns);
Alexandre Belloni916030d2014-03-14 15:19:09 +0100140 dty = prd - div;
Bo Shen32b16d42013-12-13 14:41:49 +0800141
142 ret = clk_enable(atmel_pwm->clk);
143 if (ret) {
144 dev_err(chip->dev, "failed to enable PWM clock\n");
145 return ret;
146 }
147
Alexandre Belloni8db9e292014-03-14 15:19:08 +0100148 /* It is necessary to preserve CPOL, inside CMR */
149 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
150 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
151 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
Bo Shen32b16d42013-12-13 14:41:49 +0800152 atmel_pwm->config(chip, pwm, dty, prd);
Alexandre Belloni472ac3d2015-05-25 18:11:49 +0200153 mutex_lock(&atmel_pwm->isr_lock);
154 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
155 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
156 mutex_unlock(&atmel_pwm->isr_lock);
Bo Shen32b16d42013-12-13 14:41:49 +0800157
158 clk_disable(atmel_pwm->clk);
159 return ret;
160}
161
162static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
163 unsigned long dty, unsigned long prd)
164{
165 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
166 unsigned int val;
167
Bo Shen32b16d42013-12-13 14:41:49 +0800168
Alexandre Belloni4c027f72015-05-25 15:19:55 +0200169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
170
171 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
172 val &= ~PWM_CMR_UPD_CDTY;
173 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
174
175 /*
176 * If the PWM channel is enabled, only update CDTY by using the update
177 * register, it needs to set bit 10 of CMR to 0
178 */
179 if (test_bit(PWMF_ENABLED, &pwm->flags))
180 return;
181 /*
182 * If the PWM channel is disabled, write value to duty and period
183 * registers directly.
184 */
185 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
186 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
Bo Shen32b16d42013-12-13 14:41:49 +0800187}
188
189static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
190 unsigned long dty, unsigned long prd)
191{
192 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
193
194 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
195 /*
196 * If the PWM channel is enabled, using the duty update register
197 * to update the value.
198 */
199 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
200 } else {
201 /*
202 * If the PWM channel is disabled, write value to duty and
203 * period registers directly.
204 */
205 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
206 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
207 }
208}
209
210static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
211 enum pwm_polarity polarity)
212{
213 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
214 u32 val;
215 int ret;
216
217 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
218
219 if (polarity == PWM_POLARITY_NORMAL)
220 val &= ~PWM_CMR_CPOL;
221 else
222 val |= PWM_CMR_CPOL;
223
224 ret = clk_enable(atmel_pwm->clk);
225 if (ret) {
226 dev_err(chip->dev, "failed to enable PWM clock\n");
227 return ret;
228 }
229
230 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
231
232 clk_disable(atmel_pwm->clk);
233
234 return 0;
235}
236
237static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
238{
239 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
240 int ret;
241
242 ret = clk_enable(atmel_pwm->clk);
243 if (ret) {
244 dev_err(chip->dev, "failed to enable PWM clock\n");
245 return ret;
246 }
247
248 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
249
250 return 0;
251}
252
253static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
254{
255 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
Alexandre Belloni472ac3d2015-05-25 18:11:49 +0200256 unsigned long timeout = jiffies + 2 * HZ;
Bo Shen32b16d42013-12-13 14:41:49 +0800257
Alexandre Belloni472ac3d2015-05-25 18:11:49 +0200258 /*
259 * Wait for at least a complete period to have passed before disabling a
260 * channel to be sure that CDTY has been updated
261 */
262 mutex_lock(&atmel_pwm->isr_lock);
263 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
264
265 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
266 time_before(jiffies, timeout)) {
267 usleep_range(10, 100);
268 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
269 }
270
271 mutex_unlock(&atmel_pwm->isr_lock);
Bo Shen32b16d42013-12-13 14:41:49 +0800272 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
273
274 clk_disable(atmel_pwm->clk);
275}
276
277static const struct pwm_ops atmel_pwm_ops = {
278 .config = atmel_pwm_config,
279 .set_polarity = atmel_pwm_set_polarity,
280 .enable = atmel_pwm_enable,
281 .disable = atmel_pwm_disable,
282 .owner = THIS_MODULE,
283};
284
285struct atmel_pwm_data {
286 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
287 unsigned long dty, unsigned long prd);
288};
289
290static const struct atmel_pwm_data atmel_pwm_data_v1 = {
291 .config = atmel_pwm_config_v1,
292};
293
294static const struct atmel_pwm_data atmel_pwm_data_v2 = {
295 .config = atmel_pwm_config_v2,
296};
297
298static const struct platform_device_id atmel_pwm_devtypes[] = {
299 {
300 .name = "at91sam9rl-pwm",
301 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
302 }, {
303 .name = "sama5d3-pwm",
304 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
305 }, {
306 /* sentinel */
307 },
308};
309MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
310
311static const struct of_device_id atmel_pwm_dt_ids[] = {
312 {
313 .compatible = "atmel,at91sam9rl-pwm",
314 .data = &atmel_pwm_data_v1,
315 }, {
316 .compatible = "atmel,sama5d3-pwm",
317 .data = &atmel_pwm_data_v2,
318 }, {
319 /* sentinel */
320 },
321};
322MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
323
324static inline const struct atmel_pwm_data *
325atmel_pwm_get_driver_data(struct platform_device *pdev)
326{
327 if (pdev->dev.of_node) {
328 const struct of_device_id *match;
329
330 match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
331 if (!match)
332 return NULL;
333
334 return match->data;
335 } else {
336 const struct platform_device_id *id;
337
338 id = platform_get_device_id(pdev);
339
340 return (struct atmel_pwm_data *)id->driver_data;
341 }
342}
343
344static int atmel_pwm_probe(struct platform_device *pdev)
345{
346 const struct atmel_pwm_data *data;
347 struct atmel_pwm_chip *atmel_pwm;
348 struct resource *res;
349 int ret;
350
351 data = atmel_pwm_get_driver_data(pdev);
352 if (!data)
353 return -ENODEV;
354
355 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
356 if (!atmel_pwm)
357 return -ENOMEM;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(atmel_pwm->base))
362 return PTR_ERR(atmel_pwm->base);
363
364 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
365 if (IS_ERR(atmel_pwm->clk))
366 return PTR_ERR(atmel_pwm->clk);
367
368 ret = clk_prepare(atmel_pwm->clk);
369 if (ret) {
370 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
371 return ret;
372 }
373
374 atmel_pwm->chip.dev = &pdev->dev;
375 atmel_pwm->chip.ops = &atmel_pwm_ops;
376
377 if (pdev->dev.of_node) {
378 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
379 atmel_pwm->chip.of_pwm_n_cells = 3;
380 }
381
382 atmel_pwm->chip.base = -1;
383 atmel_pwm->chip.npwm = 4;
Alexandre Bellonicf3a3842014-04-09 20:26:09 +0200384 atmel_pwm->chip.can_sleep = true;
Bo Shen32b16d42013-12-13 14:41:49 +0800385 atmel_pwm->config = data->config;
Alexandre Belloni472ac3d2015-05-25 18:11:49 +0200386 atmel_pwm->updated_pwms = 0;
387 mutex_init(&atmel_pwm->isr_lock);
Bo Shen32b16d42013-12-13 14:41:49 +0800388
389 ret = pwmchip_add(&atmel_pwm->chip);
390 if (ret < 0) {
391 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
392 goto unprepare_clk;
393 }
394
395 platform_set_drvdata(pdev, atmel_pwm);
396
Bo Shen6a683352013-12-19 11:42:22 +0800397 return ret;
398
Bo Shen32b16d42013-12-13 14:41:49 +0800399unprepare_clk:
400 clk_unprepare(atmel_pwm->clk);
401 return ret;
402}
403
404static int atmel_pwm_remove(struct platform_device *pdev)
405{
406 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
407
408 clk_unprepare(atmel_pwm->clk);
Alexandre Belloni472ac3d2015-05-25 18:11:49 +0200409 mutex_destroy(&atmel_pwm->isr_lock);
Bo Shen32b16d42013-12-13 14:41:49 +0800410
411 return pwmchip_remove(&atmel_pwm->chip);
412}
413
414static struct platform_driver atmel_pwm_driver = {
415 .driver = {
416 .name = "atmel-pwm",
417 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
418 },
419 .id_table = atmel_pwm_devtypes,
420 .probe = atmel_pwm_probe,
421 .remove = atmel_pwm_remove,
422};
423module_platform_driver(atmel_pwm_driver);
424
425MODULE_ALIAS("platform:atmel-pwm");
426MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
427MODULE_DESCRIPTION("Atmel PWM driver");
428MODULE_LICENSE("GPL v2");