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Dan Williamsd044af12011-03-08 09:52:49 -08001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55#ifndef _ISCI_PROBE_ROMS_H_
56#define _ISCI_PROBE_ROMS_H_
57
58#ifdef __KERNEL__
59#include <linux/firmware.h>
60#include <linux/pci.h>
61
62struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
63
64union scic_oem_parameters;
65struct isci_orom;
66
67enum sci_status isci_parse_oem_parameters(
68 union scic_oem_parameters *oem_params,
69 struct isci_orom *orom,
70 int scu_index);
71struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
Dave Jiang8db37aa2011-02-23 00:02:24 -080072struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
Dan Williams3b67c1f2011-03-08 09:53:51 -080073
74struct isci_oem_hdr {
75 u8 sig[4];
76 u8 rev_major;
77 u8 rev_minor;
78 u16 len;
79 u8 checksum;
80 u8 reserved1;
81 u16 reserved2;
82} __attribute__ ((packed));
83
Dan Williamsd044af12011-03-08 09:52:49 -080084#else
85#define SCI_MAX_PORTS 4
86#define SCI_MAX_PHYS 4
Dave Jiangca507b92011-02-24 13:09:39 -070087#define SCI_MAX_CONTROLLERS 2
Dan Williamsd044af12011-03-08 09:52:49 -080088#endif
89
90#define ISCI_FW_NAME "isci/isci_firmware.bin"
91
92#define ROMSIGNATURE 0xaa55
93
Dan Williams3b67c1f2011-03-08 09:53:51 -080094#define ISCI_OEM_SIG "$OEM"
95#define ISCI_OEM_SIG_SIZE 4
Dan Williamsd044af12011-03-08 09:52:49 -080096#define ISCI_ROM_SIG "ISCUOEMB"
97#define ISCI_ROM_SIG_SIZE 8
98
Dan Williams4711ba12011-03-11 10:43:57 -080099#define ISCI_PREBOOT_SOURCE_INIT (0x00)
100#define ISCI_PREBOOT_SOURCE_OROM (0x80)
101#define ISCI_PREBOOT_SOURCE_EFI (0x81)
102
Dave Jiangca507b92011-02-24 13:09:39 -0700103#define ISCI_EFI_VENDOR_GUID \
104 EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
105 0x1a, 0x04, 0xc6)
Dan Williamsd044af12011-03-08 09:52:49 -0800106#define ISCI_EFI_ATTRIBUTES 0
Dave Jiang2e8320f2011-03-11 14:04:43 -0800107#define ISCI_EFI_VAR_NAME "RstScuO"
Dan Williamsd044af12011-03-08 09:52:49 -0800108
Henryk Dembkowski07373a52011-02-23 16:55:11 -0800109/* Allowed PORT configuration modes APC Automatic PORT configuration mode is
110 * defined by the OEM configuration parameters providing no PHY_MASK parameters
111 * for any PORT. i.e. There are no phys assigned to any of the ports at start.
112 * MPC Manual PORT configuration mode is defined by the OEM configuration
113 * parameters providing a PHY_MASK value for any PORT. It is assumed that any
114 * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
115 * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
116 * being assigned is sufficient to declare manual PORT configuration.
117 */
118enum SCIC_PORT_CONFIGURATION_MODE {
Dan Williams4711ba12011-03-11 10:43:57 -0800119 SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 0,
120 SCIC_PORT_MANUAL_CONFIGURATION_MODE = 1
Henryk Dembkowski07373a52011-02-23 16:55:11 -0800121};
122
Dan Williamsd044af12011-03-08 09:52:49 -0800123struct sci_bios_oem_param_block_hdr {
124 uint8_t signature[ISCI_ROM_SIG_SIZE];
125 uint16_t total_block_length;
126 uint8_t hdr_length;
127 uint8_t version;
128 uint8_t preboot_source;
129 uint8_t num_elements;
130 uint8_t element_length;
131 uint8_t reserved[8];
132} __attribute__ ((packed));
133
134struct scic_sds_oem_params {
135 struct {
136 uint8_t mode_type;
137 uint8_t max_concurrent_dev_spin_up;
138 uint8_t do_enable_ssc;
139 uint8_t reserved;
140 } controller;
141
142 struct {
143 uint8_t phy_mask;
144 } ports[SCI_MAX_PORTS];
145
146 struct sci_phy_oem_params {
147 struct {
148 uint32_t high;
149 uint32_t low;
150 } sas_address;
151
152 uint32_t afe_tx_amp_control0;
153 uint32_t afe_tx_amp_control1;
154 uint32_t afe_tx_amp_control2;
155 uint32_t afe_tx_amp_control3;
156 } phys[SCI_MAX_PHYS];
157} __attribute__ ((packed));
158
159struct isci_orom {
160 struct sci_bios_oem_param_block_hdr hdr;
Dave Jiangca507b92011-02-24 13:09:39 -0700161 struct scic_sds_oem_params ctrl[SCI_MAX_CONTROLLERS];
Dan Williamsd044af12011-03-08 09:52:49 -0800162} __attribute__ ((packed));
163
164#endif