| Johannes Thumshirn | 3764e82 | 2014-02-26 17:29:05 +0100 | [diff] [blame^] | 1 | #ifndef __MCB_INTERNAL |
| 2 | #define __MCB_INTERNAL |
| 3 | |
| 4 | #include <linux/types.h> |
| 5 | |
| 6 | #define CHAMELEON_FILENAME_LEN 12 |
| 7 | #define CHAMELEONV2_MAGIC 0xabce |
| 8 | |
| 9 | enum chameleon_descriptor_type { |
| 10 | CHAMELEON_DTYPE_GENERAL = 0x0, |
| 11 | CHAMELEON_DTYPE_BRIDGE = 0x1, |
| 12 | CHAMELEON_DTYPE_CPU = 0x2, |
| 13 | CHAMELEON_DTYPE_BAR = 0x3, |
| 14 | CHAMELEON_DTYPE_END = 0xf, |
| 15 | }; |
| 16 | |
| 17 | enum chameleon_bus_type { |
| 18 | CHAMELEON_BUS_WISHBONE, |
| 19 | CHAMELEON_BUS_AVALON, |
| 20 | CHAMELEON_BUS_LPC, |
| 21 | CHAMELEON_BUS_ISA, |
| 22 | }; |
| 23 | |
| 24 | /** |
| 25 | * struct chameleon_fpga_header |
| 26 | * |
| 27 | * @revision: Revison of Chameleon table in FPGA |
| 28 | * @model: Chameleon table model ASCII char |
| 29 | * @minor: Revision minor |
| 30 | * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE) |
| 31 | * @magic: Chameleon header magic number (0xabce for version 2) |
| 32 | * @reserved: Reserved |
| 33 | * @filename: Filename of FPGA bitstream |
| 34 | */ |
| 35 | struct chameleon_fpga_header { |
| 36 | u8 revision; |
| 37 | char model; |
| 38 | u8 minor; |
| 39 | u8 bus_type; |
| 40 | u16 magic; |
| 41 | u16 reserved; |
| 42 | /* This one has no '\0' at the end!!! */ |
| 43 | char filename[CHAMELEON_FILENAME_LEN]; |
| 44 | } __packed; |
| 45 | #define HEADER_MAGIC_OFFSET 0x4 |
| 46 | |
| 47 | /** |
| 48 | * struct chameleon_gdd - Chameleon General Device Descriptor |
| 49 | * |
| 50 | * @irq: the position in the FPGA's IRQ controller vector |
| 51 | * @rev: the revision of the variant's implementation |
| 52 | * @var: the variant of the IP core |
| 53 | * @dev: the device the IP core is |
| 54 | * @dtype: device descriptor type |
| 55 | * @bar: BAR offset that must be added to module offset |
| 56 | * @inst: the instance number of the device, 0 is first instance |
| 57 | * @group: the group the device belongs to (0 = no group) |
| 58 | * @reserved: reserved |
| 59 | * @offset: beginning of the address window of desired module |
| 60 | * @size: size of the module's address window |
| 61 | */ |
| 62 | struct chameleon_gdd { |
| 63 | __le32 reg1; |
| 64 | __le32 reg2; |
| 65 | __le32 offset; |
| 66 | __le32 size; |
| 67 | |
| 68 | } __packed; |
| 69 | |
| 70 | /* GDD Register 1 fields */ |
| 71 | #define GDD_IRQ(x) ((x) & 0x1f) |
| 72 | #define GDD_REV(x) (((x) >> 5) & 0x3f) |
| 73 | #define GDD_VAR(x) (((x) >> 11) & 0x3f) |
| 74 | #define GDD_DEV(x) (((x) >> 18) & 0x3ff) |
| 75 | #define GDD_DTY(x) (((x) >> 28) & 0xf) |
| 76 | |
| 77 | /* GDD Register 2 fields */ |
| 78 | #define GDD_BAR(x) ((x) & 0x7) |
| 79 | #define GDD_INS(x) (((x) >> 3) & 0x3f) |
| 80 | #define GDD_GRP(x) (((x) >> 9) & 0x3f) |
| 81 | |
| 82 | /** |
| 83 | * struct chameleon_bdd - Chameleon Bridge Device Descriptor |
| 84 | * |
| 85 | * @irq: the position in the FPGA's IRQ controller vector |
| 86 | * @rev: the revision of the variant's implementation |
| 87 | * @var: the variant of the IP core |
| 88 | * @dev: the device the IP core is |
| 89 | * @dtype: device descriptor type |
| 90 | * @bar: BAR offset that must be added to module offset |
| 91 | * @inst: the instance number of the device, 0 is first instance |
| 92 | * @dbar: destination bar from the bus _behind_ the bridge |
| 93 | * @chamoff: offset within the BAR of the source bus |
| 94 | * @offset: |
| 95 | * @size: |
| 96 | */ |
| 97 | struct chameleon_bdd { |
| 98 | unsigned int irq:6; |
| 99 | unsigned int rev:6; |
| 100 | unsigned int var:6; |
| 101 | unsigned int dev:10; |
| 102 | unsigned int dtype:4; |
| 103 | unsigned int bar:3; |
| 104 | unsigned int inst:6; |
| 105 | unsigned int dbar:3; |
| 106 | unsigned int group:6; |
| 107 | unsigned int reserved:14; |
| 108 | u32 chamoff; |
| 109 | u32 offset; |
| 110 | u32 size; |
| 111 | } __packed; |
| 112 | |
| 113 | int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, |
| 114 | void __iomem *base); |
| 115 | |
| 116 | #endif |