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Russell King5e742ad2005-08-18 10:08:15 +01001/*
2 * linux/drivers/mfd/mcp-sa11x0.c
3 *
4 * Copyright (C) 2001-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * SA11x0 MCP (Multimedia Communications Port) driver.
11 *
12 * MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/spinlock.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010020#include <linux/platform_device.h>
Thomas Kunzec8602ed2009-02-10 14:54:57 +010021#include <linux/mfd/mcp.h>
Russell King5e742ad2005-08-18 10:08:15 +010022
Russell Kingdcea83a2008-11-29 11:40:28 +000023#include <mach/dma.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010024#include <mach/hardware.h>
Russell King5e742ad2005-08-18 10:08:15 +010025#include <asm/mach-types.h>
26#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/mcp.h>
Russell King5e742ad2005-08-18 10:08:15 +010028
Russell King216f63c2012-01-20 17:37:21 +000029#include <mach/assabet.h>
30
Russell King5e742ad2005-08-18 10:08:15 +010031
32struct mcp_sa11x0 {
Russell King216f63c2012-01-20 17:37:21 +000033 u32 mccr0;
34 u32 mccr1;
Russell King5e742ad2005-08-18 10:08:15 +010035};
36
37#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
38
39static void
40mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
41{
Russell King216f63c2012-01-20 17:37:21 +000042 unsigned int mccr0;
Russell King5e742ad2005-08-18 10:08:15 +010043
44 divisor /= 32;
45
Russell King216f63c2012-01-20 17:37:21 +000046 mccr0 = Ser4MCCR0 & ~0x00007f00;
47 mccr0 |= divisor << 8;
48 Ser4MCCR0 = mccr0;
Russell King5e742ad2005-08-18 10:08:15 +010049}
50
51static void
52mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
53{
Russell King216f63c2012-01-20 17:37:21 +000054 unsigned int mccr0;
Russell King5e742ad2005-08-18 10:08:15 +010055
56 divisor /= 32;
57
Russell King216f63c2012-01-20 17:37:21 +000058 mccr0 = Ser4MCCR0 & ~0x0000007f;
59 mccr0 |= divisor;
60 Ser4MCCR0 = mccr0;
Russell King5e742ad2005-08-18 10:08:15 +010061}
62
63/*
64 * Write data to the device. The bit should be set after 3 subframe
65 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
66 * We really should try doing something more productive while we
67 * wait.
68 */
69static void
70mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
71{
72 int ret = -ETIME;
73 int i;
74
Russell King216f63c2012-01-20 17:37:21 +000075 Ser4MCDR2 = reg << 17 | MCDR2_Wr | (val & 0xffff);
Russell King5e742ad2005-08-18 10:08:15 +010076
77 for (i = 0; i < 2; i++) {
78 udelay(mcp->rw_timeout);
Russell King216f63c2012-01-20 17:37:21 +000079 if (Ser4MCSR & MCSR_CWC) {
Russell King5e742ad2005-08-18 10:08:15 +010080 ret = 0;
81 break;
82 }
83 }
84
85 if (ret < 0)
86 printk(KERN_WARNING "mcp: write timed out\n");
87}
88
89/*
90 * Read data from the device. The bit should be set after 3 subframe
91 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
92 * We really should try doing something more productive while we
93 * wait.
94 */
95static unsigned int
96mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
97{
98 int ret = -ETIME;
99 int i;
100
Russell King216f63c2012-01-20 17:37:21 +0000101 Ser4MCDR2 = reg << 17 | MCDR2_Rd;
Russell King5e742ad2005-08-18 10:08:15 +0100102
103 for (i = 0; i < 2; i++) {
104 udelay(mcp->rw_timeout);
Russell King216f63c2012-01-20 17:37:21 +0000105 if (Ser4MCSR & MCSR_CRC) {
106 ret = Ser4MCDR2 & 0xffff;
Russell King5e742ad2005-08-18 10:08:15 +0100107 break;
108 }
109 }
110
111 if (ret < 0)
112 printk(KERN_WARNING "mcp: read timed out\n");
113
114 return ret;
115}
116
117static void mcp_sa11x0_enable(struct mcp *mcp)
118{
Russell King216f63c2012-01-20 17:37:21 +0000119 Ser4MCSR = -1;
120 Ser4MCCR0 |= MCCR0_MCE;
Russell King5e742ad2005-08-18 10:08:15 +0100121}
122
123static void mcp_sa11x0_disable(struct mcp *mcp)
124{
Russell King216f63c2012-01-20 17:37:21 +0000125 Ser4MCCR0 &= ~MCCR0_MCE;
Russell King5e742ad2005-08-18 10:08:15 +0100126}
127
128/*
129 * Our methods.
130 */
131static struct mcp_ops mcp_sa11x0 = {
132 .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
133 .set_audio_divisor = mcp_sa11x0_set_audio_divisor,
134 .reg_write = mcp_sa11x0_write,
135 .reg_read = mcp_sa11x0_read,
136 .enable = mcp_sa11x0_enable,
137 .disable = mcp_sa11x0_disable,
138};
139
Russell King3ae5eae2005-11-09 22:32:44 +0000140static int mcp_sa11x0_probe(struct platform_device *pdev)
Russell King5e742ad2005-08-18 10:08:15 +0100141{
Russell King323cdfc2005-08-18 10:10:46 +0100142 struct mcp_plat_data *data = pdev->dev.platform_data;
Russell King5e742ad2005-08-18 10:08:15 +0100143 struct mcp *mcp;
144 int ret;
145
Russell King323cdfc2005-08-18 10:10:46 +0100146 if (!data)
Russell King5e742ad2005-08-18 10:08:15 +0100147 return -ENODEV;
148
Russell King216f63c2012-01-20 17:37:21 +0000149 if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp"))
Russell King5e742ad2005-08-18 10:08:15 +0100150 return -EBUSY;
151
152 mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
153 if (!mcp) {
154 ret = -ENOMEM;
Russell King216f63c2012-01-20 17:37:21 +0000155 goto release;
Russell King5e742ad2005-08-18 10:08:15 +0100156 }
157
158 mcp->owner = THIS_MODULE;
159 mcp->ops = &mcp_sa11x0;
Russell King323cdfc2005-08-18 10:10:46 +0100160 mcp->sclk_rate = data->sclk_rate;
Russell King216f63c2012-01-20 17:37:21 +0000161 mcp->dma_audio_rd = DMA_Ser4MCP0Rd;
162 mcp->dma_audio_wr = DMA_Ser4MCP0Wr;
163 mcp->dma_telco_rd = DMA_Ser4MCP1Rd;
164 mcp->dma_telco_wr = DMA_Ser4MCP1Wr;
Russell King65f2e752012-01-20 17:38:58 +0000165 mcp->gpio_base = data->gpio_base;
Russell King5e742ad2005-08-18 10:08:15 +0100166
Russell King3ae5eae2005-11-09 22:32:44 +0000167 platform_set_drvdata(pdev, mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100168
Russell King216f63c2012-01-20 17:37:21 +0000169 if (machine_is_assabet()) {
170 ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
171 }
172
173 /*
174 * Setup the PPC unit correctly.
175 */
176 PPDR &= ~PPC_RXD4;
177 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
178 PSDR |= PPC_RXD4;
179 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
180 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
181
Russell King323cdfc2005-08-18 10:10:46 +0100182 /*
183 * Initialise device. Note that we initially
184 * set the sampling rate to minimum.
185 */
Russell King216f63c2012-01-20 17:37:21 +0000186 Ser4MCSR = -1;
187 Ser4MCCR1 = data->mccr1;
188 Ser4MCCR0 = data->mccr0 | 0x7f7f;
Russell King5e742ad2005-08-18 10:08:15 +0100189
190 /*
191 * Calculate the read/write timeout (us) from the bit clock
192 * rate. This is the period for 3 64-bit frames. Always
193 * round this time up.
194 */
195 mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
196 mcp->sclk_rate;
197
Russell King30816ac2012-01-20 22:51:07 +0000198 ret = mcp_host_add(mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100199 if (ret == 0)
200 goto out;
201
Russell King30816ac2012-01-20 22:51:07 +0000202 mcp_host_free(mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100203 release:
Russell King216f63c2012-01-20 17:37:21 +0000204 release_mem_region(0x80060000, 0x60);
Russell King3ae5eae2005-11-09 22:32:44 +0000205 platform_set_drvdata(pdev, NULL);
Russell King5e742ad2005-08-18 10:08:15 +0100206
207 out:
208 return ret;
209}
210
Russell King216f63c2012-01-20 17:37:21 +0000211static int mcp_sa11x0_remove(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100212{
Russell King216f63c2012-01-20 17:37:21 +0000213 struct mcp *mcp = platform_get_drvdata(dev);
Russell King5e742ad2005-08-18 10:08:15 +0100214
Russell King216f63c2012-01-20 17:37:21 +0000215 platform_set_drvdata(dev, NULL);
Russell King30816ac2012-01-20 22:51:07 +0000216 mcp_host_del(mcp);
217 mcp_host_free(mcp);
Russell King216f63c2012-01-20 17:37:21 +0000218 release_mem_region(0x80060000, 0x60);
Russell King5e742ad2005-08-18 10:08:15 +0100219
220 return 0;
221}
222
Russell King3ae5eae2005-11-09 22:32:44 +0000223static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
Russell King5e742ad2005-08-18 10:08:15 +0100224{
Russell King3ae5eae2005-11-09 22:32:44 +0000225 struct mcp *mcp = platform_get_drvdata(dev);
Russell King5e742ad2005-08-18 10:08:15 +0100226
Russell King216f63c2012-01-20 17:37:21 +0000227 priv(mcp)->mccr0 = Ser4MCCR0;
228 priv(mcp)->mccr1 = Ser4MCCR1;
229 Ser4MCCR0 &= ~MCCR0_MCE;
Russell King9480e302005-10-28 09:52:56 -0700230
Russell King5e742ad2005-08-18 10:08:15 +0100231 return 0;
232}
233
Russell King3ae5eae2005-11-09 22:32:44 +0000234static int mcp_sa11x0_resume(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100235{
Russell King3ae5eae2005-11-09 22:32:44 +0000236 struct mcp *mcp = platform_get_drvdata(dev);
Russell King5e742ad2005-08-18 10:08:15 +0100237
Russell King216f63c2012-01-20 17:37:21 +0000238 Ser4MCCR1 = priv(mcp)->mccr1;
239 Ser4MCCR0 = priv(mcp)->mccr0;
Russell King9480e302005-10-28 09:52:56 -0700240
Russell King5e742ad2005-08-18 10:08:15 +0100241 return 0;
242}
243
244/*
245 * The driver for the SA11x0 MCP port.
246 */
Kay Sievers4f46d6e2008-07-25 01:45:47 -0700247MODULE_ALIAS("platform:sa11x0-mcp");
248
Russell King3ae5eae2005-11-09 22:32:44 +0000249static struct platform_driver mcp_sa11x0_driver = {
Russell King5e742ad2005-08-18 10:08:15 +0100250 .probe = mcp_sa11x0_probe,
251 .remove = mcp_sa11x0_remove,
252 .suspend = mcp_sa11x0_suspend,
253 .resume = mcp_sa11x0_resume,
Russell King3ae5eae2005-11-09 22:32:44 +0000254 .driver = {
255 .name = "sa11x0-mcp",
256 },
Russell King5e742ad2005-08-18 10:08:15 +0100257};
258
259/*
260 * This needs re-working
261 */
Mark Brown65349d62011-11-23 22:58:34 +0000262module_platform_driver(mcp_sa11x0_driver);
Russell King5e742ad2005-08-18 10:08:15 +0100263
264MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
265MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
266MODULE_LICENSE("GPL");