blob: 826270147b5a07c8661d64fc31f6066dfd4826d7 [file] [log] [blame]
Thomas Gleixner13a9cd42007-10-11 11:14:21 +02001#define VSYSCALL_ADDR (-10*1024*1024)
Sam Ravnborg0a3ec212009-04-26 23:07:42 +02002#define VSYSCALL_PHYS_ADDR ((LOADADDR(.data.read_mostly) + \
3 SIZEOF(.data.read_mostly) + 4095) & ~(4095))
4#define VSYSCALL_VIRT_ADDR ((ADDR(.data.read_mostly) + \
5 SIZEOF(.data.read_mostly) + 4095) & ~(4095))
Thomas Gleixner13a9cd42007-10-11 11:14:21 +02006
7#define VLOAD_OFFSET (VSYSCALL_ADDR - VSYSCALL_PHYS_ADDR)
8#define VLOAD(x) (ADDR(x) - VLOAD_OFFSET)
9
10#define VVIRT_OFFSET (VSYSCALL_ADDR - VSYSCALL_VIRT_ADDR)
11#define VVIRT(x) (ADDR(x) - VVIRT_OFFSET)
12
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020013 . = VSYSCALL_ADDR;
14 .vsyscall_0 : AT(VSYSCALL_PHYS_ADDR) {
15 *(.vsyscall_0)
16 } :user
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020017
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020018 __vsyscall_0 = VSYSCALL_VIRT_ADDR;
19
20 . = ALIGN(CONFIG_X86_L1_CACHE_BYTES);
21 .vsyscall_fn : AT(VLOAD(.vsyscall_fn)) {
22 *(.vsyscall_fn)
23 }
24
25 . = ALIGN(CONFIG_X86_L1_CACHE_BYTES);
26 .vsyscall_gtod_data : AT(VLOAD(.vsyscall_gtod_data)) {
27 *(.vsyscall_gtod_data)
28 }
29
30 vsyscall_gtod_data = VVIRT(.vsyscall_gtod_data);
31 .vsyscall_clock : AT(VLOAD(.vsyscall_clock)) {
32 *(.vsyscall_clock)
33 }
34 vsyscall_clock = VVIRT(.vsyscall_clock);
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020035
36
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020037 .vsyscall_1 ADDR(.vsyscall_0) + 1024: AT(VLOAD(.vsyscall_1)) {
38 *(.vsyscall_1)
39 }
40 .vsyscall_2 ADDR(.vsyscall_0) + 2048: AT(VLOAD(.vsyscall_2)) {
41 *(.vsyscall_2)
42 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020043
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020044 .vgetcpu_mode : AT(VLOAD(.vgetcpu_mode)) {
45 *(.vgetcpu_mode)
46 }
47 vgetcpu_mode = VVIRT(.vgetcpu_mode);
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020048
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020049 . = ALIGN(CONFIG_X86_L1_CACHE_BYTES);
50 .jiffies : AT(VLOAD(.jiffies)) {
51 *(.jiffies)
52 }
53 jiffies = VVIRT(.jiffies);
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020054
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020055 .vsyscall_3 ADDR(.vsyscall_0) + 3072: AT(VLOAD(.vsyscall_3)) {
56 *(.vsyscall_3)
57 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020058
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020059 . = VSYSCALL_VIRT_ADDR + PAGE_SIZE;
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020060
61#undef VSYSCALL_ADDR
62#undef VSYSCALL_PHYS_ADDR
63#undef VSYSCALL_VIRT_ADDR
64#undef VLOAD_OFFSET
65#undef VLOAD
66#undef VVIRT_OFFSET
67#undef VVIRT
68
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020069 /* init_task */
70 .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
71 . = ALIGN(THREAD_SIZE);
72 *(.data.init_task)
73 } :data.init
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020074
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020075 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
76 /* might get freed after init */
77 . = ALIGN(PAGE_SIZE);
78 __smp_alt_begin = .;
79 __smp_locks = .;
80 *(.smp_locks)
81 __smp_locks_end = .;
82 . = ALIGN(PAGE_SIZE);
83 __smp_alt_end = .;
84 }
85
86 /* Init code and data */
Jeremy Fitzhardingeb9719a42009-03-10 11:19:18 -070087 . = ALIGN(PAGE_SIZE);
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020088 __init_begin = .; /* paired with __init_end */
89 .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
90 _sinittext = .;
91 INIT_TEXT
92 _einittext = .;
93 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +020094
Sam Ravnborg0a3ec212009-04-26 23:07:42 +020095 .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
96 __initdata_begin = .;
97 INIT_DATA
98 __initdata_end = .;
99 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200100
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200101 .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
102 . = ALIGN(16);
103 __setup_start = .;
104 *(.init.setup)
105 __setup_end = .;
106 }
Sam Ravnborg01ba2bd2008-01-20 14:15:03 +0100107
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200108 .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
109 __initcall_start = .;
110 INITCALLS
111 __initcall_end = .;
112 }
Glauber de Oliveira Costafbf51922008-01-30 13:33:19 +0100113
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200114 .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
115 __con_initcall_start = .;
116 *(.con_initcall.init)
117 __con_initcall_end = .;
118 }
Glauber de Oliveira Costafbf51922008-01-30 13:33:19 +0100119
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200120 .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
121 __x86_cpu_dev_start = .;
122 *(.x86_cpu_dev.init)
123 __x86_cpu_dev_end = .;
124 }
125
126 SECURITY_INIT
127
Jeremy Fitzhardingeb9719a42009-03-10 11:19:18 -0700128 . = ALIGN(8);
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200129 .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) {
130 __parainstructions = .;
131 *(.parainstructions)
132 __parainstructions_end = .;
133 }
134
135 .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
136 . = ALIGN(8);
137 __alt_instructions = .;
138 *(.altinstructions)
139 __alt_instructions_end = .;
140 }
141
142 .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
143 *(.altinstr_replacement)
144 }
145
146 /*
147 * .exit.text is discard at runtime, not link time, to deal with
148 * references from .altinstructions and .eh_frame
149 */
150 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
151 EXIT_TEXT
152 }
153
154 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
155 EXIT_DATA
156 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200157
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200158#ifdef CONFIG_BLK_DEV_INITRD
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200159 . = ALIGN(PAGE_SIZE);
160 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
161 __initramfs_start = .;
162 *(.init.ramfs)
163 __initramfs_end = .;
164 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200165#endif
166
Tejun Heo3e5d8f92009-01-13 20:41:35 +0900167#ifdef CONFIG_SMP
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200168 /*
169 * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the
170 * output PHDR, so the next output section - __data_nosave - should
171 * start another section data.init2. Also, pda should be at the head of
172 * percpu area. Preallocate it and define the percpu offset symbol
173 * so that it can be accessed as a percpu variable.
174 */
175 . = ALIGN(PAGE_SIZE);
176 PERCPU_VADDR(0, :percpu)
Tejun Heo3e5d8f92009-01-13 20:41:35 +0900177#else
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200178 PERCPU(PAGE_SIZE)
Tejun Heo3e5d8f92009-01-13 20:41:35 +0900179#endif
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200180
Jeremy Fitzhardingeb9719a42009-03-10 11:19:18 -0700181 . = ALIGN(PAGE_SIZE);
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200182 __init_end = .;
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200183
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200184 .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
185 . = ALIGN(PAGE_SIZE);
186 __nosave_begin = .;
187 *(.data.nosave)
188 . = ALIGN(PAGE_SIZE);
189 __nosave_end = .;
190 } :data.init2
191 /* use another section data.init2, see PERCPU_VADDR() above */
Jeremy Fitzhardinge93dbda72009-02-26 17:35:44 -0800192
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200193 .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
194 . = ALIGN(PAGE_SIZE);
195 __bss_start = .; /* BSS */
196 *(.bss.page_aligned)
197 *(.bss)
198 __bss_stop = .;
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200199 }
200
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200201 .brk : AT(ADDR(.brk) - LOAD_OFFSET) {
202 . = ALIGN(PAGE_SIZE);
203 __brk_base = .;
204 . += 64 * 1024; /* 64k alignment slop space */
205 *(.brk_reservation) /* areas brk users have reserved */
206 __brk_limit = .;
207 }
Thomas Gleixner13a9cd42007-10-11 11:14:21 +0200208
Sam Ravnborg0a3ec212009-04-26 23:07:42 +0200209 _end = . ;
210
211 /* Sections to be discarded */
212 /DISCARD/ : {
213 *(.exitcall.exit)
214 *(.eh_frame)
215 *(.discard)
216 }