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android-review.linaro.org / kernel / hikey-linaro / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / drivers / video / aty / atyfb.h
blob: 09de173c1164bc7f6835b67d51f4e0a5c525be2d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * ATI Frame Buffer Device Driver Core Definitions
3 */
4
5#include <linux/config.h>
6#include <linux/spinlock.h>
7#include <linux/wait.h>
8 /*
9 * Elements of the hardware specific atyfb_par structure
10 */
11
12struct crtc {
13 u32 vxres;
14 u32 vyres;
15 u32 xoffset;
16 u32 yoffset;
17 u32 bpp;
18 u32 h_tot_disp;
19 u32 h_sync_strt_wid;
20 u32 v_tot_disp;
21 u32 v_sync_strt_wid;
22 u32 vline_crnt_vline;
23 u32 off_pitch;
24 u32 gen_cntl;
25 u32 dp_pix_width; /* acceleration */
26 u32 dp_chain_mask; /* acceleration */
27#ifdef CONFIG_FB_ATY_GENERIC_LCD
28 u32 horz_stretching;
29 u32 vert_stretching;
30 u32 ext_vert_stretch;
31 u32 shadow_h_tot_disp;
32 u32 shadow_h_sync_strt_wid;
33 u32 shadow_v_tot_disp;
34 u32 shadow_v_sync_strt_wid;
35 u32 lcd_gen_cntl;
36 u32 lcd_config_panel;
37 u32 lcd_index;
38#endif
39};
40
41struct aty_interrupt {
42 wait_queue_head_t wait;
43 unsigned int count;
44 int pan_display;
45};
46
47struct pll_info {
48 int pll_max;
49 int pll_min;
50 int sclk, mclk, mclk_pm, xclk;
51 int ref_div;
52 int ref_clk;
53};
54
55typedef struct {
56 u16 unknown1;
57 u16 PCLK_min_freq;
58 u16 PCLK_max_freq;
59 u16 unknown2;
60 u16 ref_freq;
61 u16 ref_divider;
62 u16 unknown3;
63 u16 MCLK_pwd;
64 u16 MCLK_max_freq;
65 u16 XCLK_max_freq;
66 u16 SCLK_freq;
67} __attribute__ ((packed)) PLL_BLOCK_MACH64;
68
69struct pll_514 {
70 u8 m;
71 u8 n;
72};
73
74struct pll_18818 {
75 u32 program_bits;
76 u32 locationAddr;
77 u32 period_in_ps;
78 u32 post_divider;
79};
80
81struct pll_ct {
82 u8 pll_ref_div;
83 u8 pll_gen_cntl;
84 u8 mclk_fb_div;
85 u8 mclk_fb_mult; /* 2 ro 4 */
86 u8 sclk_fb_div;
87 u8 pll_vclk_cntl;
88 u8 vclk_post_div;
89 u8 vclk_fb_div;
90 u8 pll_ext_cntl;
91 u8 ext_vpll_cntl;
92 u8 spll_cntl2;
93 u32 dsp_config; /* Mach64 GTB DSP */
94 u32 dsp_on_off; /* Mach64 GTB DSP */
95 u32 dsp_loop_latency;
96 u32 fifo_size;
97 u32 xclkpagefaultdelay;
98 u32 xclkmaxrasdelay;
99 u8 xclk_ref_div;
100 u8 xclk_post_div;
101 u8 mclk_post_div_real;
102 u8 xclk_post_div_real;
103 u8 vclk_post_div_real;
104 u8 features;
105#ifdef CONFIG_FB_ATY_GENERIC_LCD
106 u32 xres; /* use for LCD stretching/scaling */
107#endif
108};
109
110/*
111 for pll_ct.features
112*/
113#define DONT_USE_SPLL 0x1
114#define DONT_USE_XDLL 0x2
115#define USE_CPUCLK 0x4
116#define POWERDOWN_PLL 0x8
117
118union aty_pll {
119 struct pll_ct ct;
120 struct pll_514 ibm514;
121 struct pll_18818 ics2595;
122};
123
124 /*
125 * The hardware parameters for each card
126 */
127
128struct atyfb_par {
129 struct aty_cmap_regs __iomem *aty_cmap_regs;
130 struct { u8 red, green, blue; } palette[256];
131 const struct aty_dac_ops *dac_ops;
132 const struct aty_pll_ops *pll_ops;
133 void __iomem *ati_regbase;
134 unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
135 struct crtc crtc;
136 union aty_pll pll;
137 struct pll_info pll_limits;
138 u32 features;
139 u32 ref_clk_per;
140 u32 pll_per;
141 u32 mclk_per;
142 u32 xclk_per;
143 u8 bus_type;
144 u8 ram_type;
145 u8 mem_refresh_rate;
146 u16 pci_id;
147 u32 accel_flags;
148 int blitter_may_be_busy;
149 int asleep;
150 int lock_blank;
151 unsigned long res_start;
152 unsigned long res_size;
153#ifdef __sparc__
154 struct pci_mmap_map *mmap_map;
155 u8 mmaped;
156#endif
157 int open;
158#ifdef CONFIG_FB_ATY_GENERIC_LCD
159 unsigned long bios_base_phys;
160 unsigned long bios_base;
161 unsigned long lcd_table;
162 u16 lcd_width;
163 u16 lcd_height;
164 u32 lcd_pixclock;
165 u16 lcd_refreshrate;
166 u16 lcd_htotal;
167 u16 lcd_hdisp;
168 u16 lcd_hsync_dly;
169 u16 lcd_hsync_len;
170 u16 lcd_vtotal;
171 u16 lcd_vdisp;
172 u16 lcd_vsync_len;
173 u16 lcd_right_margin;
174 u16 lcd_lower_margin;
175 u16 lcd_hblank_len;
176 u16 lcd_vblank_len;
177#endif
178 unsigned long aux_start; /* auxiliary aperture */
179 unsigned long aux_size;
180 struct aty_interrupt vblank;
181 unsigned long irq_flags;
182 unsigned int irq;
183 spinlock_t int_lock;
184#ifdef CONFIG_MTRR
185 int mtrr_aper;
186 int mtrr_reg;
187#endif
188};
189
190 /*
191 * ATI Mach64 features
192 */
193
194#define M64_HAS(feature) ((par)->features & (M64F_##feature))
195
196#define M64F_RESET_3D 0x00000001
197#define M64F_MAGIC_FIFO 0x00000002
198#define M64F_GTB_DSP 0x00000004
199#define M64F_FIFO_32 0x00000008
200#define M64F_SDRAM_MAGIC_PLL 0x00000010
201#define M64F_MAGIC_POSTDIV 0x00000020
202#define M64F_INTEGRATED 0x00000040
203#define M64F_CT_BUS 0x00000080
204#define M64F_VT_BUS 0x00000100
205#define M64F_MOBIL_BUS 0x00000200
206#define M64F_GX 0x00000400
207#define M64F_CT 0x00000800
208#define M64F_VT 0x00001000
209#define M64F_GT 0x00002000
210#define M64F_MAGIC_VRAM_SIZE 0x00004000
211#define M64F_G3_PB_1_1 0x00008000
212#define M64F_G3_PB_1024x768 0x00010000
213#define M64F_EXTRA_BRIGHT 0x00020000
214#define M64F_LT_LCD_REGS 0x00040000
215#define M64F_XL_DLL 0x00080000
216#define M64F_MFB_FORCE_4 0x00100000
217#define M64F_HW_TRIPLE 0x00200000
218 /*
219 * Register access
220 */
221
222static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
223{
224 /* Hack for bloc 1, should be cleanly optimized by compiler */
225 if (regindex >= 0x400)
226 regindex -= 0x800;
227
228#ifdef CONFIG_ATARI
229 return in_le32((volatile u32 *)(par->ati_regbase + regindex));
230#else
231 return readl(par->ati_regbase + regindex);
232#endif
233}
234
235static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
236{
237 /* Hack for bloc 1, should be cleanly optimized by compiler */
238 if (regindex >= 0x400)
239 regindex -= 0x800;
240
241#ifdef CONFIG_ATARI
242 out_le32((volatile u32 *)(par->ati_regbase + regindex), val);
243#else
244 writel(val, par->ati_regbase + regindex);
245#endif
246}
247
248static inline void aty_st_le16(int regindex, u16 val,
249 const struct atyfb_par *par)
250{
251 /* Hack for bloc 1, should be cleanly optimized by compiler */
252 if (regindex >= 0x400)
253 regindex -= 0x800;
254#ifdef CONFIG_ATARI
255 out_le16((volatile u16 *)(par->ati_regbase + regindex), val);
256#else
257 writel(val, par->ati_regbase + regindex);
258#endif
259}
260
261static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
262{
263 /* Hack for bloc 1, should be cleanly optimized by compiler */
264 if (regindex >= 0x400)
265 regindex -= 0x800;
266#ifdef CONFIG_ATARI
267 return in_8(par->ati_regbase + regindex);
268#else
269 return readb(par->ati_regbase + regindex);
270#endif
271}
272
273static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
274{
275 /* Hack for bloc 1, should be cleanly optimized by compiler */
276 if (regindex >= 0x400)
277 regindex -= 0x800;
278
279#ifdef CONFIG_ATARI
280 out_8(par->ati_regbase + regindex, val);
281#else
282 writeb(val, par->ati_regbase + regindex);
283#endif
284}
285
286#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
287extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
288extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
289#endif
290
291 /*
292 * DAC operations
293 */
294
295struct aty_dac_ops {
296 int (*set_dac) (const struct fb_info * info,
297 const union aty_pll * pll, u32 bpp, u32 accel);
298};
299
300extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
301extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
302extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
303extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
304extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
305
306
307 /*
308 * Clock operations
309 */
310
311struct aty_pll_ops {
312 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
313 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
314 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
315 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
316 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
317};
318
319extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
320extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
321extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
322extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
323extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
324extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
325extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
326
327
328extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
329extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
330
331
332 /*
333 * Hardware cursor support
334 */
335
336extern int aty_init_cursor(struct fb_info *info);
337
338 /*
339 * Hardware acceleration
340 */
341
342static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
343{
344 while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
345 ((u32) (0x8000 >> entries)));
346}
347
348static inline void wait_for_idle(struct atyfb_par *par)
349{
350 wait_for_fifo(16, par);
351 while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
352 par->blitter_may_be_busy = 0;
353}
354
355extern void aty_reset_engine(const struct atyfb_par *par);
356extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
357extern int atyfb_xl_init(struct fb_info *info);
358extern void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par);
359extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);