| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * A collection of structures, addresses, and values associated with |
| 3 | * the Motorola MPC8260ADS/MPC8266ADS-PCI boards. |
| 4 | * Copied from the RPX-Classic and SBS8260 stuff. |
| 5 | * |
| 6 | * Copyright (c) 2001 Dan Malek (dan@mvista.com) |
| 7 | */ |
| 8 | #ifdef __KERNEL__ |
| 9 | #ifndef __MACH_ADS8260_DEFS |
| 10 | #define __MACH_ADS8260_DEFS |
| 11 | |
| 12 | #include <linux/config.h> |
| 13 | |
| 14 | #include <asm/ppcboot.h> |
| 15 | |
| 16 | /* Memory map is configured by the PROM startup. |
| 17 | * We just map a few things we need. The CSR is actually 4 byte-wide |
| 18 | * registers that can be accessed as 8-, 16-, or 32-bit values. |
| 19 | */ |
| 20 | #define CPM_MAP_ADDR ((uint)0xf0000000) |
| 21 | #define BCSR_ADDR ((uint)0xf4500000) |
| 22 | #define BCSR_SIZE ((uint)(32 * 1024)) |
| 23 | |
| 24 | #define BOOTROM_RESTART_ADDR ((uint)0xff000104) |
| 25 | |
| 26 | /* For our show_cpuinfo hooks. */ |
| 27 | #define CPUINFO_VENDOR "Motorola" |
| 28 | #define CPUINFO_MACHINE "PQ2 ADS PowerPC" |
| 29 | |
| 30 | /* The ADS8260 has 16, 32-bit wide control/status registers, accessed |
| 31 | * only on word boundaries. |
| 32 | * Not all are used (yet), or are interesting to us (yet). |
| 33 | */ |
| 34 | |
| 35 | /* Things of interest in the CSR. |
| 36 | */ |
| 37 | #define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */ |
| 38 | #define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */ |
| 39 | #define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */ |
| 40 | #define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */ |
| 41 | #define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */ |
| 42 | #define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */ |
| 43 | #define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable */ |
| 44 | #define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */ |
| 45 | |
| 46 | #define PHY_INTERRUPT SIU_INT_IRQ7 |
| 47 | |
| 48 | #ifdef CONFIG_PCI |
| 49 | /* PCI interrupt controller */ |
| 50 | #define PCI_INT_STAT_REG 0xF8200000 |
| 51 | #define PCI_INT_MASK_REG 0xF8200004 |
| 52 | #define PIRQA (NR_SIU_INTS + 0) |
| 53 | #define PIRQB (NR_SIU_INTS + 1) |
| 54 | #define PIRQC (NR_SIU_INTS + 2) |
| 55 | #define PIRQD (NR_SIU_INTS + 3) |
| 56 | |
| 57 | /* |
| 58 | * PCI memory map definitions for MPC8266ADS-PCI. |
| 59 | * |
| 60 | * processor view |
| 61 | * local address PCI address target |
| 62 | * 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch |
| 63 | * 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch |
| 64 | * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO |
| 65 | * |
| 66 | * PCI master view |
| 67 | * local address PCI address target |
| 68 | * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory |
| 69 | */ |
| 70 | |
| 71 | /* window for a PCI master to access MPC8266 memory */ |
| 72 | #define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */ |
| 73 | #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ |
| 74 | |
| 75 | /* window for the processor to access PCI memory with prefetching */ |
| 76 | #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ |
| 77 | #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ |
| 78 | #define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ |
| 79 | |
| 80 | /* window for the processor to access PCI memory without prefetching */ |
| 81 | #define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ |
| 82 | #define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ |
| 83 | #define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ |
| 84 | |
| 85 | /* window for the processor to access PCI I/O */ |
| 86 | #define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ |
| 87 | #define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ |
| 88 | #define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ |
| 89 | |
| 90 | #define _IO_BASE PCI_MSTR_IO_LOCAL |
| 91 | #define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL |
| 92 | #define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS |
| 93 | #endif /* CONFIG_PCI */ |
| 94 | |
| 95 | #endif /* __MACH_ADS8260_DEFS */ |
| 96 | #endif /* __KERNEL__ */ |