Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/setup.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2001 Russell King |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/export.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/stddef.h> |
| 23 | #include <linux/ioport.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/utsname.h> |
| 26 | #include <linux/initrd.h> |
| 27 | #include <linux/console.h> |
| 28 | #include <linux/bootmem.h> |
| 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/screen_info.h> |
| 31 | #include <linux/init.h> |
| 32 | #include <linux/kexec.h> |
| 33 | #include <linux/crash_dump.h> |
| 34 | #include <linux/root_dev.h> |
Catalin Marinas | de79a64 | 2013-02-08 12:18:15 +0000 | [diff] [blame] | 35 | #include <linux/clk-provider.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 36 | #include <linux/cpu.h> |
| 37 | #include <linux/interrupt.h> |
| 38 | #include <linux/smp.h> |
| 39 | #include <linux/fs.h> |
| 40 | #include <linux/proc_fs.h> |
| 41 | #include <linux/memblock.h> |
| 42 | #include <linux/of_fdt.h> |
Catalin Marinas | d6bafb9 | 2012-12-07 17:47:17 +0000 | [diff] [blame] | 43 | #include <linux/of_platform.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 44 | |
| 45 | #include <asm/cputype.h> |
| 46 | #include <asm/elf.h> |
| 47 | #include <asm/cputable.h> |
Mark Rutland | e8765b2 | 2013-10-24 20:30:17 +0100 | [diff] [blame] | 48 | #include <asm/cpu_ops.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 49 | #include <asm/sections.h> |
| 50 | #include <asm/setup.h> |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 51 | #include <asm/smp_plat.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 52 | #include <asm/cacheflush.h> |
| 53 | #include <asm/tlbflush.h> |
| 54 | #include <asm/traps.h> |
| 55 | #include <asm/memblock.h> |
Will Deacon | e790f1d | 2012-12-18 17:53:14 +0000 | [diff] [blame] | 56 | #include <asm/psci.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 57 | |
| 58 | unsigned int processor_id; |
| 59 | EXPORT_SYMBOL(processor_id); |
| 60 | |
Steve Capper | 25804e6 | 2013-09-18 16:14:28 +0100 | [diff] [blame] | 61 | unsigned long elf_hwcap __read_mostly; |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 62 | EXPORT_SYMBOL_GPL(elf_hwcap); |
| 63 | |
Sudeep KarkadaNagesha | 46efe54 | 2013-08-13 15:57:53 +0100 | [diff] [blame] | 64 | #ifdef CONFIG_COMPAT |
| 65 | #define COMPAT_ELF_HWCAP_DEFAULT \ |
| 66 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ |
| 67 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ |
| 68 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ |
| 69 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ |
| 70 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) |
| 71 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; |
Ard Biesheuvel | 28964d3 | 2014-03-03 07:34:45 +0000 | [diff] [blame] | 72 | unsigned int compat_elf_hwcap2 __read_mostly; |
Sudeep KarkadaNagesha | 46efe54 | 2013-08-13 15:57:53 +0100 | [diff] [blame] | 73 | #endif |
| 74 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 75 | static const char *cpu_name; |
| 76 | static const char *machine_name; |
| 77 | phys_addr_t __fdt_pointer __initdata; |
| 78 | |
| 79 | /* |
| 80 | * Standard memory resources |
| 81 | */ |
| 82 | static struct resource mem_res[] = { |
| 83 | { |
| 84 | .name = "Kernel code", |
| 85 | .start = 0, |
| 86 | .end = 0, |
| 87 | .flags = IORESOURCE_MEM |
| 88 | }, |
| 89 | { |
| 90 | .name = "Kernel data", |
| 91 | .start = 0, |
| 92 | .end = 0, |
| 93 | .flags = IORESOURCE_MEM |
| 94 | } |
| 95 | }; |
| 96 | |
| 97 | #define kernel_code mem_res[0] |
| 98 | #define kernel_data mem_res[1] |
| 99 | |
| 100 | void __init early_print(const char *str, ...) |
| 101 | { |
| 102 | char buf[256]; |
| 103 | va_list ap; |
| 104 | |
| 105 | va_start(ap, str); |
| 106 | vsnprintf(buf, sizeof(buf), str, ap); |
| 107 | va_end(ap); |
| 108 | |
| 109 | printk("%s", buf); |
| 110 | } |
| 111 | |
Will Deacon | 7158627 | 2013-11-05 18:10:47 +0000 | [diff] [blame] | 112 | void __init smp_setup_processor_id(void) |
| 113 | { |
| 114 | /* |
| 115 | * clear __my_cpu_offset on boot CPU to avoid hang caused by |
| 116 | * using percpu variable early, for example, lockdep will |
| 117 | * access percpu variable inside lock_release |
| 118 | */ |
| 119 | set_my_cpu_offset(0); |
| 120 | } |
| 121 | |
Sudeep KarkadaNagesha | 6e15d0e | 2013-10-21 13:29:42 +0100 | [diff] [blame] | 122 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
| 123 | { |
| 124 | return phys_id == cpu_logical_map(cpu); |
| 125 | } |
| 126 | |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 127 | struct mpidr_hash mpidr_hash; |
| 128 | #ifdef CONFIG_SMP |
| 129 | /** |
| 130 | * smp_build_mpidr_hash - Pre-compute shifts required at each affinity |
| 131 | * level in order to build a linear index from an |
| 132 | * MPIDR value. Resulting algorithm is a collision |
| 133 | * free hash carried out through shifting and ORing |
| 134 | */ |
| 135 | static void __init smp_build_mpidr_hash(void) |
| 136 | { |
| 137 | u32 i, affinity, fs[4], bits[4], ls; |
| 138 | u64 mask = 0; |
| 139 | /* |
| 140 | * Pre-scan the list of MPIDRS and filter out bits that do |
| 141 | * not contribute to affinity levels, ie they never toggle. |
| 142 | */ |
| 143 | for_each_possible_cpu(i) |
| 144 | mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); |
| 145 | pr_debug("mask of set bits %#llx\n", mask); |
| 146 | /* |
| 147 | * Find and stash the last and first bit set at all affinity levels to |
| 148 | * check how many bits are required to represent them. |
| 149 | */ |
| 150 | for (i = 0; i < 4; i++) { |
| 151 | affinity = MPIDR_AFFINITY_LEVEL(mask, i); |
| 152 | /* |
| 153 | * Find the MSB bit and LSB bits position |
| 154 | * to determine how many bits are required |
| 155 | * to express the affinity level. |
| 156 | */ |
| 157 | ls = fls(affinity); |
| 158 | fs[i] = affinity ? ffs(affinity) - 1 : 0; |
| 159 | bits[i] = ls - fs[i]; |
| 160 | } |
| 161 | /* |
| 162 | * An index can be created from the MPIDR_EL1 by isolating the |
| 163 | * significant bits at each affinity level and by shifting |
| 164 | * them in order to compress the 32 bits values space to a |
| 165 | * compressed set of values. This is equivalent to hashing |
| 166 | * the MPIDR_EL1 through shifting and ORing. It is a collision free |
| 167 | * hash though not minimal since some levels might contain a number |
| 168 | * of CPUs that is not an exact power of 2 and their bit |
| 169 | * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. |
| 170 | */ |
| 171 | mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; |
| 172 | mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; |
| 173 | mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - |
| 174 | (bits[1] + bits[0]); |
| 175 | mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + |
| 176 | fs[3] - (bits[2] + bits[1] + bits[0]); |
| 177 | mpidr_hash.mask = mask; |
| 178 | mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; |
| 179 | pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", |
| 180 | mpidr_hash.shift_aff[0], |
| 181 | mpidr_hash.shift_aff[1], |
| 182 | mpidr_hash.shift_aff[2], |
| 183 | mpidr_hash.shift_aff[3], |
| 184 | mpidr_hash.mask, |
| 185 | mpidr_hash.bits); |
| 186 | /* |
| 187 | * 4x is an arbitrary value used to warn on a hash table much bigger |
| 188 | * than expected on most systems. |
| 189 | */ |
| 190 | if (mpidr_hash_size() > 4 * num_possible_cpus()) |
| 191 | pr_warn("Large number of MPIDR hash buckets detected\n"); |
| 192 | __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); |
| 193 | } |
| 194 | #endif |
| 195 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 196 | static void __init setup_processor(void) |
| 197 | { |
| 198 | struct cpu_info *cpu_info; |
Steve Capper | 4bff28c | 2013-12-16 21:04:36 +0000 | [diff] [blame] | 199 | u64 features, block; |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 200 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 201 | cpu_info = lookup_processor_type(read_cpuid_id()); |
| 202 | if (!cpu_info) { |
| 203 | printk("CPU configuration botched (ID %08x), unable to continue.\n", |
| 204 | read_cpuid_id()); |
| 205 | while (1); |
| 206 | } |
| 207 | |
| 208 | cpu_name = cpu_info->cpu_name; |
| 209 | |
| 210 | printk("CPU: %s [%08x] revision %d\n", |
| 211 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15); |
| 212 | |
Will Deacon | 94ed1f2 | 2013-10-11 14:52:11 +0100 | [diff] [blame] | 213 | sprintf(init_utsname()->machine, ELF_PLATFORM); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 214 | elf_hwcap = 0; |
Steve Capper | 4bff28c | 2013-12-16 21:04:36 +0000 | [diff] [blame] | 215 | |
| 216 | /* |
| 217 | * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. |
| 218 | * The blocks we test below represent incremental functionality |
| 219 | * for non-negative values. Negative values are reserved. |
| 220 | */ |
| 221 | features = read_cpuid(ID_AA64ISAR0_EL1); |
| 222 | block = (features >> 4) & 0xf; |
| 223 | if (!(block & 0x8)) { |
| 224 | switch (block) { |
| 225 | default: |
| 226 | case 2: |
| 227 | elf_hwcap |= HWCAP_PMULL; |
| 228 | case 1: |
| 229 | elf_hwcap |= HWCAP_AES; |
| 230 | case 0: |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | block = (features >> 8) & 0xf; |
| 236 | if (block && !(block & 0x8)) |
| 237 | elf_hwcap |= HWCAP_SHA1; |
| 238 | |
| 239 | block = (features >> 12) & 0xf; |
| 240 | if (block && !(block & 0x8)) |
| 241 | elf_hwcap |= HWCAP_SHA2; |
| 242 | |
| 243 | block = (features >> 16) & 0xf; |
| 244 | if (block && !(block & 0x8)) |
| 245 | elf_hwcap |= HWCAP_CRC32; |
Ard Biesheuvel | 4cf761c | 2014-03-03 07:34:46 +0000 | [diff] [blame] | 246 | |
| 247 | #ifdef CONFIG_COMPAT |
| 248 | /* |
| 249 | * ID_ISAR5_EL1 carries similar information as above, but pertaining to |
| 250 | * the Aarch32 32-bit execution state. |
| 251 | */ |
| 252 | features = read_cpuid(ID_ISAR5_EL1); |
| 253 | block = (features >> 4) & 0xf; |
| 254 | if (!(block & 0x8)) { |
| 255 | switch (block) { |
| 256 | default: |
| 257 | case 2: |
| 258 | compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL; |
| 259 | case 1: |
| 260 | compat_elf_hwcap2 |= COMPAT_HWCAP2_AES; |
| 261 | case 0: |
| 262 | break; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | block = (features >> 8) & 0xf; |
| 267 | if (block && !(block & 0x8)) |
| 268 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1; |
| 269 | |
| 270 | block = (features >> 12) & 0xf; |
| 271 | if (block && !(block & 0x8)) |
| 272 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2; |
| 273 | |
| 274 | block = (features >> 16) & 0xf; |
| 275 | if (block && !(block & 0x8)) |
| 276 | compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32; |
| 277 | #endif |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static void __init setup_machine_fdt(phys_addr_t dt_phys) |
| 281 | { |
Rob Herring | d5189cc | 2013-08-26 10:14:32 -0500 | [diff] [blame] | 282 | if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 283 | early_print("\n" |
| 284 | "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" |
Rob Herring | d5189cc | 2013-08-26 10:14:32 -0500 | [diff] [blame] | 285 | "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 286 | "\nPlease check your bootloader.\n", |
Rob Herring | d5189cc | 2013-08-26 10:14:32 -0500 | [diff] [blame] | 287 | dt_phys, phys_to_virt(dt_phys)); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 288 | |
| 289 | while (true) |
| 290 | cpu_relax(); |
| 291 | } |
| 292 | |
Rob Herring | f2b99bc | 2013-08-27 21:44:37 -0500 | [diff] [blame] | 293 | machine_name = of_flat_dt_get_machine_name(); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 294 | } |
| 295 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 296 | /* |
| 297 | * Limit the memory size that was specified via FDT. |
| 298 | */ |
| 299 | static int __init early_mem(char *p) |
| 300 | { |
| 301 | phys_addr_t limit; |
| 302 | |
| 303 | if (!p) |
| 304 | return 1; |
| 305 | |
| 306 | limit = memparse(p, &p) & PAGE_MASK; |
| 307 | pr_notice("Memory limited to %lldMB\n", limit >> 20); |
| 308 | |
| 309 | memblock_enforce_memory_limit(limit); |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | early_param("mem", early_mem); |
| 314 | |
| 315 | static void __init request_standard_resources(void) |
| 316 | { |
| 317 | struct memblock_region *region; |
| 318 | struct resource *res; |
| 319 | |
| 320 | kernel_code.start = virt_to_phys(_text); |
| 321 | kernel_code.end = virt_to_phys(_etext - 1); |
| 322 | kernel_data.start = virt_to_phys(_sdata); |
| 323 | kernel_data.end = virt_to_phys(_end - 1); |
| 324 | |
| 325 | for_each_memblock(memory, region) { |
| 326 | res = alloc_bootmem_low(sizeof(*res)); |
| 327 | res->name = "System RAM"; |
| 328 | res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); |
| 329 | res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; |
| 330 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
| 331 | |
| 332 | request_resource(&iomem_resource, res); |
| 333 | |
| 334 | if (kernel_code.start >= res->start && |
| 335 | kernel_code.end <= res->end) |
| 336 | request_resource(res, &kernel_code); |
| 337 | if (kernel_data.start >= res->start && |
| 338 | kernel_data.end <= res->end) |
| 339 | request_resource(res, &kernel_data); |
| 340 | } |
| 341 | } |
| 342 | |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 343 | u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; |
| 344 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 345 | void __init setup_arch(char **cmdline_p) |
| 346 | { |
Catalin Marinas | b3bf6aa | 2013-11-21 14:46:17 +0000 | [diff] [blame] | 347 | /* |
| 348 | * Unmask asynchronous aborts early to catch possible system errors. |
| 349 | */ |
| 350 | local_async_enable(); |
| 351 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 352 | setup_processor(); |
| 353 | |
| 354 | setup_machine_fdt(__fdt_pointer); |
| 355 | |
| 356 | init_mm.start_code = (unsigned long) _text; |
| 357 | init_mm.end_code = (unsigned long) _etext; |
| 358 | init_mm.end_data = (unsigned long) _edata; |
| 359 | init_mm.brk = (unsigned long) _end; |
| 360 | |
| 361 | *cmdline_p = boot_command_line; |
| 362 | |
Mark Salter | 0bf757c | 2014-04-07 15:39:51 -0700 | [diff] [blame^] | 363 | init_mem_pgprot(); |
| 364 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 365 | parse_early_param(); |
| 366 | |
| 367 | arm64_memblock_init(); |
| 368 | |
| 369 | paging_init(); |
| 370 | request_standard_resources(); |
| 371 | |
| 372 | unflatten_device_tree(); |
| 373 | |
Will Deacon | e790f1d | 2012-12-18 17:53:14 +0000 | [diff] [blame] | 374 | psci_init(); |
| 375 | |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 376 | cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
Mark Rutland | e8765b2 | 2013-10-24 20:30:17 +0100 | [diff] [blame] | 377 | cpu_read_bootcpu_ops(); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 378 | #ifdef CONFIG_SMP |
| 379 | smp_init_cpus(); |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 380 | smp_build_mpidr_hash(); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 381 | #endif |
| 382 | |
| 383 | #ifdef CONFIG_VT |
| 384 | #if defined(CONFIG_VGA_CONSOLE) |
| 385 | conswitchp = &vga_con; |
| 386 | #elif defined(CONFIG_DUMMY_CONSOLE) |
| 387 | conswitchp = &dummy_con; |
| 388 | #endif |
| 389 | #endif |
| 390 | } |
| 391 | |
Catalin Marinas | c560ecf | 2013-05-14 10:51:18 +0100 | [diff] [blame] | 392 | static int __init arm64_device_init(void) |
Catalin Marinas | de79a64 | 2013-02-08 12:18:15 +0000 | [diff] [blame] | 393 | { |
| 394 | of_clk_init(NULL); |
Catalin Marinas | c560ecf | 2013-05-14 10:51:18 +0100 | [diff] [blame] | 395 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
Catalin Marinas | de79a64 | 2013-02-08 12:18:15 +0000 | [diff] [blame] | 396 | return 0; |
| 397 | } |
Catalin Marinas | c560ecf | 2013-05-14 10:51:18 +0100 | [diff] [blame] | 398 | arch_initcall(arm64_device_init); |
Catalin Marinas | de79a64 | 2013-02-08 12:18:15 +0000 | [diff] [blame] | 399 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 400 | static DEFINE_PER_CPU(struct cpu, cpu_data); |
| 401 | |
| 402 | static int __init topology_init(void) |
| 403 | { |
| 404 | int i; |
| 405 | |
| 406 | for_each_possible_cpu(i) { |
| 407 | struct cpu *cpu = &per_cpu(cpu_data, i); |
| 408 | cpu->hotpluggable = 1; |
| 409 | register_cpu(cpu, i); |
| 410 | } |
| 411 | |
| 412 | return 0; |
| 413 | } |
| 414 | subsys_initcall(topology_init); |
| 415 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 416 | static const char *hwcap_str[] = { |
| 417 | "fp", |
| 418 | "asimd", |
Sudeep KarkadaNagesha | 46efe54 | 2013-08-13 15:57:53 +0100 | [diff] [blame] | 419 | "evtstrm", |
Steve Capper | 4bff28c | 2013-12-16 21:04:36 +0000 | [diff] [blame] | 420 | "aes", |
| 421 | "pmull", |
| 422 | "sha1", |
| 423 | "sha2", |
| 424 | "crc32", |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 425 | NULL |
| 426 | }; |
| 427 | |
| 428 | static int c_show(struct seq_file *m, void *v) |
| 429 | { |
| 430 | int i; |
| 431 | |
| 432 | seq_printf(m, "Processor\t: %s rev %d (%s)\n", |
| 433 | cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); |
| 434 | |
| 435 | for_each_online_cpu(i) { |
| 436 | /* |
| 437 | * glibc reads /proc/cpuinfo to determine the number of |
| 438 | * online processors, looking for lines beginning with |
| 439 | * "processor". Give glibc what it expects. |
| 440 | */ |
| 441 | #ifdef CONFIG_SMP |
| 442 | seq_printf(m, "processor\t: %d\n", i); |
| 443 | #endif |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | /* dump out the processor features */ |
| 447 | seq_puts(m, "Features\t: "); |
| 448 | |
| 449 | for (i = 0; hwcap_str[i]; i++) |
| 450 | if (elf_hwcap & (1 << i)) |
| 451 | seq_printf(m, "%s ", hwcap_str[i]); |
| 452 | |
| 453 | seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); |
| 454 | seq_printf(m, "CPU architecture: AArch64\n"); |
| 455 | seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); |
| 456 | seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); |
| 457 | seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); |
| 458 | |
| 459 | seq_puts(m, "\n"); |
| 460 | |
| 461 | seq_printf(m, "Hardware\t: %s\n", machine_name); |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | static void *c_start(struct seq_file *m, loff_t *pos) |
| 467 | { |
| 468 | return *pos < 1 ? (void *)1 : NULL; |
| 469 | } |
| 470 | |
| 471 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) |
| 472 | { |
| 473 | ++*pos; |
| 474 | return NULL; |
| 475 | } |
| 476 | |
| 477 | static void c_stop(struct seq_file *m, void *v) |
| 478 | { |
| 479 | } |
| 480 | |
| 481 | const struct seq_operations cpuinfo_op = { |
| 482 | .start = c_start, |
| 483 | .next = c_next, |
| 484 | .stop = c_stop, |
| 485 | .show = c_show |
| 486 | }; |