Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
| 21 | /** |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 22 | * dynamic_irq_init - initialize a dynamically allocated irq |
| 23 | * @irq: irq number to initialize |
| 24 | */ |
| 25 | void dynamic_irq_init(unsigned int irq) |
| 26 | { |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame^] | 27 | struct irq_desc *desc; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 28 | unsigned long flags; |
| 29 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame^] | 30 | desc = irq_to_desc(irq); |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 31 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 32 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 33 | return; |
| 34 | } |
| 35 | |
| 36 | /* Ensure we don't have left over values from a previous use of this irq */ |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 37 | spin_lock_irqsave(&desc->lock, flags); |
| 38 | desc->status = IRQ_DISABLED; |
| 39 | desc->chip = &no_irq_chip; |
| 40 | desc->handle_irq = handle_bad_irq; |
| 41 | desc->depth = 1; |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 42 | desc->msi_desc = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 43 | desc->handler_data = NULL; |
| 44 | desc->chip_data = NULL; |
| 45 | desc->action = NULL; |
| 46 | desc->irq_count = 0; |
| 47 | desc->irqs_unhandled = 0; |
| 48 | #ifdef CONFIG_SMP |
Mike Travis | d366f8c | 2008-04-04 18:11:12 -0700 | [diff] [blame] | 49 | cpus_setall(desc->affinity); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 50 | #endif |
| 51 | spin_unlock_irqrestore(&desc->lock, flags); |
| 52 | } |
| 53 | |
| 54 | /** |
| 55 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq |
| 56 | * @irq: irq number to initialize |
| 57 | */ |
| 58 | void dynamic_irq_cleanup(unsigned int irq) |
| 59 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 60 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 61 | unsigned long flags; |
| 62 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 63 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 64 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 65 | return; |
| 66 | } |
| 67 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 68 | spin_lock_irqsave(&desc->lock, flags); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 69 | if (desc->action) { |
| 70 | spin_unlock_irqrestore(&desc->lock, flags); |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 71 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 72 | irq); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 73 | return; |
| 74 | } |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 75 | desc->msi_desc = NULL; |
| 76 | desc->handler_data = NULL; |
| 77 | desc->chip_data = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 78 | desc->handle_irq = handle_bad_irq; |
| 79 | desc->chip = &no_irq_chip; |
Dean Nelson | b6f3b78 | 2008-10-18 16:06:56 -0700 | [diff] [blame] | 80 | desc->name = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 81 | spin_unlock_irqrestore(&desc->lock, flags); |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 86 | * set_irq_chip - set the irq chip for an irq |
| 87 | * @irq: irq number |
| 88 | * @chip: pointer to irq chip description structure |
| 89 | */ |
| 90 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) |
| 91 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 92 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 93 | unsigned long flags; |
| 94 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 95 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 96 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 97 | return -EINVAL; |
| 98 | } |
| 99 | |
| 100 | if (!chip) |
| 101 | chip = &no_irq_chip; |
| 102 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 103 | spin_lock_irqsave(&desc->lock, flags); |
| 104 | irq_chip_set_defaults(chip); |
| 105 | desc->chip = chip; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 106 | spin_unlock_irqrestore(&desc->lock, flags); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | EXPORT_SYMBOL(set_irq_chip); |
| 111 | |
| 112 | /** |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 113 | * set_irq_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 114 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 115 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 116 | */ |
| 117 | int set_irq_type(unsigned int irq, unsigned int type) |
| 118 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 119 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 120 | unsigned long flags; |
| 121 | int ret = -ENXIO; |
| 122 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 123 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 124 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
| 125 | return -ENODEV; |
| 126 | } |
| 127 | |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 128 | if (type == IRQ_TYPE_NONE) |
| 129 | return 0; |
| 130 | |
| 131 | spin_lock_irqsave(&desc->lock, flags); |
Chris Friesen | 0b3682ba3 | 2008-10-20 12:41:58 -0600 | [diff] [blame] | 132 | ret = __irq_set_trigger(desc, irq, type); |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 133 | spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 134 | return ret; |
| 135 | } |
| 136 | EXPORT_SYMBOL(set_irq_type); |
| 137 | |
| 138 | /** |
| 139 | * set_irq_data - set irq type data for an irq |
| 140 | * @irq: Interrupt number |
| 141 | * @data: Pointer to interrupt specific data |
| 142 | * |
| 143 | * Set the hardware irq controller data for an irq |
| 144 | */ |
| 145 | int set_irq_data(unsigned int irq, void *data) |
| 146 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 147 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 148 | unsigned long flags; |
| 149 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 150 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 151 | printk(KERN_ERR |
| 152 | "Trying to install controller data for IRQ%d\n", irq); |
| 153 | return -EINVAL; |
| 154 | } |
| 155 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 156 | spin_lock_irqsave(&desc->lock, flags); |
| 157 | desc->handler_data = data; |
| 158 | spin_unlock_irqrestore(&desc->lock, flags); |
| 159 | return 0; |
| 160 | } |
| 161 | EXPORT_SYMBOL(set_irq_data); |
| 162 | |
| 163 | /** |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 164 | * set_irq_data - set irq type data for an irq |
| 165 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 166 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 167 | * |
| 168 | * Set the hardware irq controller data for an irq |
| 169 | */ |
| 170 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) |
| 171 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 172 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 173 | unsigned long flags; |
| 174 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 175 | if (!desc) { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 176 | printk(KERN_ERR |
| 177 | "Trying to install msi data for IRQ%d\n", irq); |
| 178 | return -EINVAL; |
| 179 | } |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 180 | |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 181 | spin_lock_irqsave(&desc->lock, flags); |
| 182 | desc->msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 183 | if (entry) |
| 184 | entry->irq = irq; |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 185 | spin_unlock_irqrestore(&desc->lock, flags); |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 190 | * set_irq_chip_data - set irq chip data for an irq |
| 191 | * @irq: Interrupt number |
| 192 | * @data: Pointer to chip specific data |
| 193 | * |
| 194 | * Set the hardware irq chip data for an irq |
| 195 | */ |
| 196 | int set_irq_chip_data(unsigned int irq, void *data) |
| 197 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 198 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 199 | unsigned long flags; |
| 200 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 201 | if (!desc) { |
| 202 | printk(KERN_ERR |
| 203 | "Trying to install chip data for IRQ%d\n", irq); |
| 204 | return -EINVAL; |
| 205 | } |
| 206 | |
| 207 | if (!desc->chip) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 208 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
| 209 | return -EINVAL; |
| 210 | } |
| 211 | |
| 212 | spin_lock_irqsave(&desc->lock, flags); |
| 213 | desc->chip_data = data; |
| 214 | spin_unlock_irqrestore(&desc->lock, flags); |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | EXPORT_SYMBOL(set_irq_chip_data); |
| 219 | |
| 220 | /* |
| 221 | * default enable function |
| 222 | */ |
| 223 | static void default_enable(unsigned int irq) |
| 224 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 225 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 226 | |
| 227 | desc->chip->unmask(irq); |
| 228 | desc->status &= ~IRQ_MASKED; |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * default disable function |
| 233 | */ |
| 234 | static void default_disable(unsigned int irq) |
| 235 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | /* |
| 239 | * default startup function |
| 240 | */ |
| 241 | static unsigned int default_startup(unsigned int irq) |
| 242 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 243 | struct irq_desc *desc = irq_to_desc(irq); |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 244 | |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 245 | desc->chip->enable(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | /* |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 250 | * default shutdown function |
| 251 | */ |
| 252 | static void default_shutdown(unsigned int irq) |
| 253 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 254 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 255 | |
| 256 | desc->chip->mask(irq); |
| 257 | desc->status |= IRQ_MASKED; |
| 258 | } |
| 259 | |
| 260 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 261 | * Fixup enable/disable function pointers |
| 262 | */ |
| 263 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 264 | { |
| 265 | if (!chip->enable) |
| 266 | chip->enable = default_enable; |
| 267 | if (!chip->disable) |
| 268 | chip->disable = default_disable; |
| 269 | if (!chip->startup) |
| 270 | chip->startup = default_startup; |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 271 | /* |
| 272 | * We use chip->disable, when the user provided its own. When |
| 273 | * we have default_disable set for chip->disable, then we need |
| 274 | * to use default_shutdown, otherwise the irq line is not |
| 275 | * disabled on free_irq(): |
| 276 | */ |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 277 | if (!chip->shutdown) |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 278 | chip->shutdown = chip->disable != default_disable ? |
| 279 | chip->disable : default_shutdown; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 280 | if (!chip->name) |
| 281 | chip->name = chip->typename; |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 282 | if (!chip->end) |
| 283 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) |
| 287 | { |
| 288 | if (desc->chip->mask_ack) |
| 289 | desc->chip->mask_ack(irq); |
| 290 | else { |
| 291 | desc->chip->mask(irq); |
| 292 | desc->chip->ack(irq); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | /** |
| 297 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 298 | * @irq: the interrupt number |
| 299 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 300 | * |
| 301 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 302 | * handler or come from hardware, where no interrupt hardware control |
| 303 | * is necessary. |
| 304 | * |
| 305 | * Note: The caller is expected to handle the ack, clear, mask and |
| 306 | * unmask issues if necessary. |
| 307 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 308 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 309 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 310 | { |
| 311 | struct irqaction *action; |
| 312 | irqreturn_t action_ret; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 313 | |
| 314 | spin_lock(&desc->lock); |
| 315 | |
| 316 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 317 | goto out_unlock; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 318 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 319 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 320 | |
| 321 | action = desc->action; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 322 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 323 | goto out_unlock; |
| 324 | |
| 325 | desc->status |= IRQ_INPROGRESS; |
| 326 | spin_unlock(&desc->lock); |
| 327 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 328 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 329 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 330 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 331 | |
| 332 | spin_lock(&desc->lock); |
| 333 | desc->status &= ~IRQ_INPROGRESS; |
| 334 | out_unlock: |
| 335 | spin_unlock(&desc->lock); |
| 336 | } |
| 337 | |
| 338 | /** |
| 339 | * handle_level_irq - Level type irq handler |
| 340 | * @irq: the interrupt number |
| 341 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 342 | * |
| 343 | * Level type interrupts are active as long as the hardware line has |
| 344 | * the active level. This may require to mask the interrupt and unmask |
| 345 | * it after the associated handler has acknowledged the device, so the |
| 346 | * interrupt line is back to inactive. |
| 347 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 348 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 349 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 350 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 351 | struct irqaction *action; |
| 352 | irqreturn_t action_ret; |
| 353 | |
| 354 | spin_lock(&desc->lock); |
| 355 | mask_ack_irq(desc, irq); |
| 356 | |
| 357 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 358 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 359 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 360 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 361 | |
| 362 | /* |
| 363 | * If its disabled or no action available |
| 364 | * keep it masked and get out of here |
| 365 | */ |
| 366 | action = desc->action; |
Thomas Gleixner | 4966342 | 2007-08-12 15:46:34 +0000 | [diff] [blame] | 367 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 368 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 369 | |
| 370 | desc->status |= IRQ_INPROGRESS; |
| 371 | spin_unlock(&desc->lock); |
| 372 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 373 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 374 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 375 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 376 | |
| 377 | spin_lock(&desc->lock); |
| 378 | desc->status &= ~IRQ_INPROGRESS; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 379 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
| 380 | desc->chip->unmask(irq); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 381 | out_unlock: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 382 | spin_unlock(&desc->lock); |
| 383 | } |
| 384 | |
| 385 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 386 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 387 | * @irq: the interrupt number |
| 388 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 389 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 390 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 391 | * call when the interrupt has been serviced. This enables support |
| 392 | * for modern forms of interrupt handlers, which handle the flow |
| 393 | * details in hardware, transparently. |
| 394 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 395 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 396 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 397 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 398 | struct irqaction *action; |
| 399 | irqreturn_t action_ret; |
| 400 | |
| 401 | spin_lock(&desc->lock); |
| 402 | |
| 403 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 404 | goto out; |
| 405 | |
| 406 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 407 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 408 | |
| 409 | /* |
| 410 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 411 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 412 | */ |
| 413 | action = desc->action; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 414 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
| 415 | desc->status |= IRQ_PENDING; |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 416 | if (desc->chip->mask) |
| 417 | desc->chip->mask(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 418 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 419 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 420 | |
| 421 | desc->status |= IRQ_INPROGRESS; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 422 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 423 | spin_unlock(&desc->lock); |
| 424 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 425 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 426 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 427 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 428 | |
| 429 | spin_lock(&desc->lock); |
| 430 | desc->status &= ~IRQ_INPROGRESS; |
| 431 | out: |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 432 | desc->chip->eoi(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 433 | |
| 434 | spin_unlock(&desc->lock); |
| 435 | } |
| 436 | |
| 437 | /** |
| 438 | * handle_edge_irq - edge type IRQ handler |
| 439 | * @irq: the interrupt number |
| 440 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 441 | * |
| 442 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 443 | * signal. The occurence is latched into the irq controller hardware |
| 444 | * and must be acked in order to be reenabled. After the ack another |
| 445 | * interrupt can happen on the same source even before the first one |
| 446 | * is handled by the assosiacted event handler. If this happens it |
| 447 | * might be necessary to disable (mask) the interrupt depending on the |
| 448 | * controller hardware. This requires to reenable the interrupt inside |
| 449 | * of the loop which handles the interrupts which have arrived while |
| 450 | * the handler was running. If all pending interrupts are handled, the |
| 451 | * loop is left. |
| 452 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 453 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 454 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 455 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 456 | spin_lock(&desc->lock); |
| 457 | |
| 458 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
| 459 | |
| 460 | /* |
| 461 | * If we're currently running this IRQ, or its disabled, |
| 462 | * we shouldn't process the IRQ. Mark it pending, handle |
| 463 | * the necessary masking and go out |
| 464 | */ |
| 465 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || |
| 466 | !desc->action)) { |
| 467 | desc->status |= (IRQ_PENDING | IRQ_MASKED); |
| 468 | mask_ack_irq(desc, irq); |
| 469 | goto out_unlock; |
| 470 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 471 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 472 | |
| 473 | /* Start handling the irq */ |
| 474 | desc->chip->ack(irq); |
| 475 | |
| 476 | /* Mark the IRQ currently in progress.*/ |
| 477 | desc->status |= IRQ_INPROGRESS; |
| 478 | |
| 479 | do { |
| 480 | struct irqaction *action = desc->action; |
| 481 | irqreturn_t action_ret; |
| 482 | |
| 483 | if (unlikely(!action)) { |
| 484 | desc->chip->mask(irq); |
| 485 | goto out_unlock; |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * When another irq arrived while we were handling |
| 490 | * one, we could have masked the irq. |
| 491 | * Renable it, if it was not disabled in meantime. |
| 492 | */ |
| 493 | if (unlikely((desc->status & |
| 494 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == |
| 495 | (IRQ_PENDING | IRQ_MASKED))) { |
| 496 | desc->chip->unmask(irq); |
| 497 | desc->status &= ~IRQ_MASKED; |
| 498 | } |
| 499 | |
| 500 | desc->status &= ~IRQ_PENDING; |
| 501 | spin_unlock(&desc->lock); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 502 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 503 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 504 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 505 | spin_lock(&desc->lock); |
| 506 | |
| 507 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); |
| 508 | |
| 509 | desc->status &= ~IRQ_INPROGRESS; |
| 510 | out_unlock: |
| 511 | spin_unlock(&desc->lock); |
| 512 | } |
| 513 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 514 | /** |
| 515 | * handle_percpu_IRQ - Per CPU local irq handler |
| 516 | * @irq: the interrupt number |
| 517 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 518 | * |
| 519 | * Per CPU interrupts on SMP machines without locking requirements |
| 520 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 521 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 522 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 523 | { |
| 524 | irqreturn_t action_ret; |
| 525 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 526 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 527 | |
| 528 | if (desc->chip->ack) |
| 529 | desc->chip->ack(irq); |
| 530 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 531 | action_ret = handle_IRQ_event(irq, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 533 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 534 | |
| 535 | if (desc->chip->eoi) |
| 536 | desc->chip->eoi(irq); |
| 537 | } |
| 538 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 | void |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 540 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 541 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 542 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 543 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | unsigned long flags; |
| 545 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 546 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 547 | printk(KERN_ERR |
| 548 | "Trying to install type control for IRQ%d\n", irq); |
| 549 | return; |
| 550 | } |
| 551 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 552 | if (!handle) |
| 553 | handle = handle_bad_irq; |
Thomas Gleixner | 9d7ac8b | 2006-12-22 01:08:14 -0800 | [diff] [blame] | 554 | else if (desc->chip == &no_irq_chip) { |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 555 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
Geert Uytterhoeven | b039db8 | 2006-12-20 15:59:48 +0100 | [diff] [blame] | 556 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 557 | /* |
| 558 | * Some ARM implementations install a handler for really dumb |
| 559 | * interrupt hardware without setting an irq_chip. This worked |
| 560 | * with the ARM no_irq_chip but the check in setup_irq would |
| 561 | * prevent us to setup the interrupt at all. Switch it to |
| 562 | * dummy_irq_chip for easy transition. |
| 563 | */ |
| 564 | desc->chip = &dummy_irq_chip; |
| 565 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 566 | |
| 567 | spin_lock_irqsave(&desc->lock, flags); |
| 568 | |
| 569 | /* Uninstall? */ |
| 570 | if (handle == handle_bad_irq) { |
Jan Beulich | 5575ddf | 2007-02-16 01:28:26 -0800 | [diff] [blame] | 571 | if (desc->chip != &no_irq_chip) |
| 572 | mask_ack_irq(desc, irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 573 | desc->status |= IRQ_DISABLED; |
| 574 | desc->depth = 1; |
| 575 | } |
| 576 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 577 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 578 | |
| 579 | if (handle != handle_bad_irq && is_chained) { |
| 580 | desc->status &= ~IRQ_DISABLED; |
| 581 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
| 582 | desc->depth = 0; |
Pawel MOLL | 7e6e178 | 2008-09-01 10:12:11 +0100 | [diff] [blame] | 583 | desc->chip->startup(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | } |
| 585 | spin_unlock_irqrestore(&desc->lock, flags); |
| 586 | } |
| 587 | |
| 588 | void |
| 589 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 590 | irq_flow_handler_t handle) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 591 | { |
| 592 | set_irq_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 593 | __set_irq_handler(irq, handle, 0, NULL); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 594 | } |
| 595 | |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 596 | void |
| 597 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
| 598 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 599 | { |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 600 | set_irq_chip(irq, chip); |
| 601 | __set_irq_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 602 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 603 | |
| 604 | void __init set_irq_noprobe(unsigned int irq) |
| 605 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 606 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 607 | unsigned long flags; |
| 608 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 609 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 610 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 611 | return; |
| 612 | } |
| 613 | |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 614 | spin_lock_irqsave(&desc->lock, flags); |
| 615 | desc->status |= IRQ_NOPROBE; |
| 616 | spin_unlock_irqrestore(&desc->lock, flags); |
| 617 | } |
| 618 | |
| 619 | void __init set_irq_probe(unsigned int irq) |
| 620 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 621 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 622 | unsigned long flags; |
| 623 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 624 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 625 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 626 | return; |
| 627 | } |
| 628 | |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 629 | spin_lock_irqsave(&desc->lock, flags); |
| 630 | desc->status &= ~IRQ_NOPROBE; |
| 631 | spin_unlock_irqrestore(&desc->lock, flags); |
| 632 | } |