Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
Date:		April 2015
KernelVersion:  4.01
Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(RW) Enable/disable tracing on this specific trace entiry.
		Enabling a source implies the source has been configured
		properly and a sink has been identidifed for it.  The path
		of coresight components linking the source to the sink is
		configured and managed automatically by the coresight framework.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) The CPU this tracing entity is associated with.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of PE comparator inputs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of address comparator pairs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of counters that are available for
		tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates how many external inputs are implemented.

What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of Context ID comparators that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of VMID comparators that are available
		for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of sequencer states that are
		implemented.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of resource selection pairs that are
		available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description:	(R) Indicates the number of single-shot comparator controls that
		are available for tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(W) Cancels all configuration on a trace unit and set it back
		to its boot configuration.

What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls various modes supported by this ETM, for example
		P0 instruction tracing, branch broadcast, cycle counting and
		context ID tracing.

What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls which PE to trace.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the behavior of the events in bank 0 to 3.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls the insertion of global timestamps in the trace
		streams.

What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls how often trace synchronization requests occur.

What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Sets the threshold value for cycle counting.

What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls which regions in the memory map are enabled to
		use branch broadcasting.

What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) Controls instruction trace filtering.

What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) In Secure state, each bit controls whether instruction
		tracing is enabled for the corresponding exception level.

What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
Date:		April 2015
KernelVersion:	4.01
Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
Description: 	(RW) In non-secure state, each bit controls whether instruction
		tracing is enabled for the corresponding exception level.