| Victor Liu | ab669fd | 2024-01-23 11:40:42 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the UWB stack for linux. |
| 3 | * |
| 4 | * Copyright (c) 2020-2021 Qorvo US, Inc. |
| 5 | * |
| 6 | * This software is provided under the GNU General Public License, version 2 |
| 7 | * (GPLv2), as well as under a Qorvo commercial license. |
| 8 | * |
| 9 | * You may choose to use this software under the terms of the GPLv2 License, |
| 10 | * version 2 ("GPLv2"), as published by the Free Software Foundation. |
| 11 | * You should have received a copy of the GPLv2 along with this program. If |
| 12 | * not, see <http://www.gnu.org/licenses/>. |
| 13 | * |
| 14 | * This program is distributed under the GPLv2 in the hope that it will be |
| 15 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GPLv2 for more |
| 17 | * details. |
| 18 | * |
| 19 | * If you cannot meet the requirements of the GPLv2, you may not use this |
| 20 | * software for any purpose without first obtaining a commercial license from |
| 21 | * Qorvo. Please contact Qorvo to inquire about licensing terms. |
| 22 | */ |
| 23 | #ifndef __DW3000_CHIP_D0_H |
| 24 | #define __DW3000_CHIP_D0_H |
| 25 | |
| 26 | /* Register PLL_COARSE_CODE */ |
| 27 | #define DW3000_PLL_COARSE_CODE_ID 0x90004 |
| 28 | #define DW3000_PLL_COARSE_CODE_LEN (4U) |
| 29 | #define DW3000_PLL_COARSE_CODE_MASK 0xFFFFFFFFUL |
| 30 | #define DW3000_PLL_COARSE_CODE_CH5_VCO_COARSE_TUNE_BIT_OFFSET (8U) |
| 31 | #define DW3000_PLL_COARSE_CODE_CH5_VCO_COARSE_TUNE_BIT_LEN (14U) |
| 32 | #define DW3000_PLL_COARSE_CODE_CH5_VCO_COARSE_TUNE_BIT_MASK 0x3fff00UL |
| 33 | #define DW3000_PLL_COARSE_CODE_CH9_VCO_COARSE_TUNE_BIT_OFFSET (0U) |
| 34 | #define DW3000_PLL_COARSE_CODE_CH9_VCO_COARSE_TUNE_BIT_LEN (5U) |
| 35 | #define DW3000_PLL_COARSE_CODE_CH9_VCO_COARSE_TUNE_BIT_MASK 0x1fU |
| 36 | |
| 37 | /* Time to wait before reading the calibration status register |
| 38 | * when a calibration from scratch is executed */ |
| 39 | #define DW3000_D0_PLL_CALIBRATION_FROM_SCRATCH_DELAY_US (400) |
| 40 | |
| 41 | /* RSSI constants */ |
| 42 | #define DW3000_RSSI_OFFSET_PRF64_STS 121 |
| 43 | #define DW3000_RSSI_OFFSET_PRF64_IPATOV 122 |
| 44 | #define DW3000_RSSI_OFFSET_PRF16 114 |
| 45 | #define DW3000_RSSI_CONSTANT \ |
| 46 | 51 /* 3 * log2(2^17) because log2 used instead of log10 */ |
| 47 | |
| 48 | #endif /* __DW3000_CHIP_D0_H */ |